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109 files changed

+1061
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lines changed

‎.gitignore

+1
Original file line numberDiff line numberDiff line change
@@ -61,3 +61,4 @@ untracked_files/
6161

6262
# Just in case
6363
/dmd
64+
.DS_Store

‎VERSION

+1-1
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
v2.110.0-rc.1
1+
v2.111.0-beta.1

‎changelog/dmd.auto-ref-return.dd

+12
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
Keywords `auto` and `ref` must be adjacent for `auto ref` return.
2+
3+
Similar to `auto ref` parameters in 2.111, it's now deprecated to declare an `auto ref` return type without putting those two keywords next to each other as well.
4+
5+
---
6+
ref auto int f() => 3;
7+
auto { ref int g() => 3; }
8+
9+
// Correction:
10+
auto ref f() => 3;
11+
auto ref g() => 3;
12+
---

‎changelog/dmd.copying-to-void-arrays.dd

-15
This file was deleted.

‎changelog/dmd.extern-std-cpp23.dd

+4
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
The compiler now accepts `-extern-std=c++23`
2+
3+
The compiler now accepts c++23 as a supported standard for `-extern-std=`.
4+
Currently this only changes the value of `__traits(getTargetInfo, "cppStd")`.

‎changelog/dmd.import-exp-hexstring.dd

-12
This file was deleted.

‎changelog/dmd.isCOMClass.dd

-5
This file was deleted.

‎changelog/dmd.unsafe-boolean-values.dd

-15
This file was deleted.

‎changelog/druntime.int128.dd

+14
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
`core.int128`: Add `mul` and `udivmod` overloads for 64-bit operands
2+
3+
These map to a single x86_64 instruction and have accordingly been optimized via inline assembly.
4+
5+
---
6+
import core.int128;
7+
8+
ulong a, b;
9+
Cent product128 = mul(a, b);
10+
11+
ulong divisor64 = …;
12+
ulong modulus64;
13+
ulong quotient64 = udivmod(product128, divisor64, modulus64);
14+
---

‎compiler/src/dmd/aggregate.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -196,7 +196,7 @@ class StructDeclaration : public AggregateDeclaration
196196

197197
unsigned numArgTypes() const;
198198
Type *argType(unsigned index);
199-
bool hasRegularCtor(bool checkDisabled = false);
199+
bool hasRegularCtor(bool ignoreDisabled = false);
200200
};
201201

202202
class UnionDeclaration final : public StructDeclaration

‎compiler/src/dmd/backend/arm/cod1.d

+8-4
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,8 @@ nothrow:
5858
void loadFromEA(ref code cs, reg_t reg, uint szw, uint szr)
5959
{
6060
//debug printf("loadFromEA() reg: %d, szw: %d, szr: %d\n", reg, szw, szr);
61+
//debug printf("EV1.Voffset: %d\n", cast(int)cs.IEV1.Voffset);
62+
assert(szr <= szw);
6163
cs.Iop = INSTR.nop;
6264
assert(reg != NOREG);
6365
if (mask(reg) & INSTR.FLOATREGS) // if floating point store
@@ -85,7 +87,7 @@ void loadFromEA(ref code cs, reg_t reg, uint szw, uint szr)
8587
return;
8688
}
8789

88-
bool signExtend = (cs.Sextend & 7) == Extend.SXTB;
90+
bool signExtend = (cs.Sextend & 4) != 0; // SXTB, SXTH, SXTW, SXTX
8991

9092
if (cs.reg != NOREG)
9193
{
@@ -113,7 +115,8 @@ void loadFromEA(ref code cs, reg_t reg, uint szw, uint szr)
113115
cs.Iop = signExtend ? INSTR.ldrsh_imm(szw == 8, reg, cs.base, 0)
114116
: INSTR.ldrh_imm (szw == 8, reg, cs.base, 0);
115117
else
116-
cs.Iop = INSTR.ldr_imm_gen(szw == 8, reg, cs.base, 0);
118+
cs.Iop = signExtend ? INSTR.ldrsw_imm(0, cs.base, reg)
119+
: INSTR.ldr_imm_gen(szw == 8, reg, cs.base, 0);
117120
}
118121
else
119122
assert(0);
@@ -495,6 +498,7 @@ void loadea(ref CodeBuilder cdb,elem* e,ref code cs,uint op,reg_t reg,targ_size_
495498
getlvalue(cdb, cs, e, keepmsk, rmx);
496499
cs.IEV1.Voffset += offset;
497500

501+
assert(op != LEA); // AArch64 does not have LEA
498502
loadFromEA(cs,reg,sz == 8 ? 8 : 4,sz);
499503

500504
getregs(cdb, desmsk); // save any regs we destroy
@@ -1435,9 +1439,9 @@ void cdfunc(ref CGstate cg, ref CodeBuilder cdb, elem* e, ref regm_t pretregs)
14351439
/* stack for parameters is allocated all at once - no pushing
14361440
* and ensure it is aligned
14371441
*/
1438-
printf("STACKALIGN: %d\n", STACKALIGN);
1442+
//printf("STACKALIGN: %d\n", STACKALIGN);
14391443
uint numalign = -numpara & (STACKALIGN - 1);
1440-
printf("numalign: %d numpara: %d\n", numalign, numpara);
1444+
//printf("numalign: %d numpara: %d\n", numalign, numpara);
14411445
cod3_stackadj(cdb, numalign + numpara);
14421446
cdb.genadjesp(numalign + numpara);
14431447
cgstate.stackpush += numalign + numpara;

‎compiler/src/dmd/backend/arm/cod2.d

+36-18
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ import dmd.backend.oper;
3737
import dmd.backend.ty;
3838
import dmd.backend.type;
3939
import dmd.backend.x86.xmm;
40-
import dmd.backend.arm.cod1 : loadFromEA, storeToEA;
40+
import dmd.backend.arm.cod1 : loadFromEA, storeToEA, getlvalue;
4141
import dmd.backend.arm.cod3 : conditionCode, genBranch, gentstreg, movregconst, COND;
4242
import dmd.backend.arm.instr;
4343

@@ -453,14 +453,13 @@ void cdcom(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
453453
assert(0);
454454
}
455455

456-
const posregs = cgstate.allregs;
457-
regm_t retregs1 = posregs;
456+
regm_t retregs1 = cg.allregs;
458457
codelem(cgstate,cdb,e.E1,retregs1,false);
459458

460459
regm_t retregs = pretregs & cg.allregs;
461460
if (retregs == 0) /* if no return regs speced */
462461
/* (like if wanted flags only) */
463-
retregs = ALLREGS & posregs; // give us some
462+
retregs = cg.allregs; // give us some
464463
reg_t Rd = allocreg(cdb, retregs, tyml);
465464

466465
const Rm = findreg(retregs1);
@@ -1068,7 +1067,7 @@ void cdind(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
10681067

10691068
uint decode(uint to, uint from, bool uns) { return to * 4 * 2 + from * 2 + uns; }
10701069

1071-
switch (decode(4, sz, uns))
1070+
switch (decode(sz == 8 ? 8 : 4, sz, uns))
10721071
{
10731072
/*
10741073
int = *byte ldrsb w0,[x1] 39C00020
@@ -1331,6 +1330,8 @@ static if (0)
13311330
{ cgstate.stackchanged = 1;
13321331
cs.Iop = 0x68; /* PUSH immed16 */
13331332
cdb.genadjesp(REGSIZE);
1333+
cs.IFL1 = fl;
1334+
cdb.gen(&cs);
13341335
}
13351336
else
13361337
{
@@ -1339,10 +1340,12 @@ static if (0)
13391340

13401341
cs.Iop = INSTR.addsub_imm(1,0,0,0,0,reg,reg); // ADD reg,reg,#0
13411342
cs.Iflags |= CFadd;
1343+
cs.IFL1 = fl;
1344+
cdb.gen(&cs);
1345+
1346+
if (e.Voffset)
1347+
cdb.gen1(INSTR.addsub_imm(1,0,0,0,cast(uint)e.Voffset,reg,reg)); // ADD reg,reg,#Voffset
13421348
}
1343-
//cs.Iflags = CFoff; /* want offset only */
1344-
cs.IFL1 = fl;
1345-
cdb.gen(&cs);
13461349
break;
13471350

13481351
case FL.reg:
@@ -1372,9 +1375,16 @@ static if (0)
13721375
}
13731376
else
13741377
{
1375-
loadea(cdb,e,cs,LEA,reg,0,0,0); // LEA reg,EA
1376-
if (I64)
1377-
code_orrex(cdb.last(), REX_W);
1378+
uint sh = 0;
1379+
uint base = 0;
1380+
cs.Iop = INSTR.addsub_imm(1,0,0,sh,base,cgstate.BP,reg); // ADD reg,BP,base
1381+
cs.IFL1 = fl;
1382+
cs.IEV1.Vsym = e.Vsym;
1383+
cs.IEV1.Voffset = 0;
1384+
cdb.gen(&cs);
1385+
cdb.gen1(INSTR.addsub_imm(1,0,0,sh,cast(uint)e.Voffset,reg,reg)); // ADD reg,reg,Voffset
1386+
// TODO AArch64 common subexpressions?
1387+
//loadea(cdb,e,cs,LEA,reg,0,0,0); // LEA reg,EA
13781388
}
13791389
break;
13801390

@@ -1532,7 +1542,7 @@ void cdabs(ref CGstate cg, ref CodeBuilder cdb,elem* e, ref regm_t pretregs)
15321542
void cdpost(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
15331543
{
15341544
//printf("cdpost(pretregs = %s)\n", regm_str(pretregs));
1535-
code cs = void;
1545+
//elem_print(e);
15361546
const op = e.Eoper; // OPxxxx
15371547
if (pretregs == 0) // if nothing to return
15381548
{
@@ -1560,10 +1570,11 @@ void cdpost(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
15601570
}
15611571

15621572
assert(e2.Eoper == OPconst);
1563-
regm_t possregs = cgstate.allregs;
1573+
regm_t possregs = cg.allregs;
1574+
code cs;
15641575
getlvalue(cdb,cs,e.E1,0);
15651576
freenode(e.E1);
1566-
if (cs.reg && pretregs == mPSW)
1577+
if (cs.reg != NOREG && pretregs == mPSW)
15671578
{
15681579
gentstreg(cdb,cs.reg,sz == 8); // CMP cs.reg,#0
15691580

@@ -1579,7 +1590,11 @@ void cdpost(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
15791590
}
15801591
else if (sz <= REGSIZE)
15811592
{
1582-
regm_t idxregs = mask(cs.base) | mask(cs.index); // mask of index regs used
1593+
regm_t idxregs; // mask of index regs used
1594+
if (cs.base != NOREG)
1595+
idxregs |= mask(cs.base);
1596+
if (cs.index != NOREG)
1597+
idxregs |= mask(cs.index);
15831598
regm_t retregs = possregs & ~idxregs & pretregs;
15841599
if (retregs == 0)
15851600
retregs = possregs & ~idxregs;
@@ -1588,7 +1603,7 @@ void cdpost(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
15881603

15891604
loadFromEA(cs,reg,sz == 8 ? 8 : 4,sz);
15901605

1591-
cdb.gen(&cs); // MOV reg,EA
1606+
cdb.gen(&cs); // LDR reg,EA
15921607

15931608
if (pretregs & mPSW)
15941609
{
@@ -1601,11 +1616,14 @@ void cdpost(ref CGstate cg, ref CodeBuilder cdb,elem* e,ref regm_t pretregs)
16011616

16021617
const n = e2.Vint;
16031618
uint opx = OPpostinc ? 0 : 1;
1604-
uint ins = INSTR.addsub_imm(sz == 8,opx,1,0,n,cs.reg,cs.reg); // ADD/SUB cs.reg,cs.reg,n);
1619+
uint ins = INSTR.addsub_imm(sz == 8,opx,1,0,n,reg,reg); // ADD/SUB cs.reg,cs.reg,n);
16051620
cdb.gen1(ins);
16061621

16071622
storeToEA(cs,reg,sz);
1608-
cdb.gen(&cs); // MOV EA,reg
1623+
cdb.gen(&cs); // STR reg,EA
1624+
1625+
opx ^= 1;
1626+
cdb.gen1(INSTR.addsub_imm(sz == 8,opx,1,0,n,reg,reg)); // SUB/ADD cs.reg,cs.reg,n);
16091627

16101628
freenode(e2);
16111629
fixresult(cdb,e,retregs,pretregs);

‎compiler/src/dmd/backend/arm/cod3.d

+15-5
Original file line numberDiff line numberDiff line change
@@ -1297,7 +1297,7 @@ void assignaddrc(code* c)
12971297
uint ins = c.Iop;
12981298
if (0 && c.IFL1 != FL.unde)
12991299
{
1300-
printf("FL: %s ", fl_str(c.IFL1));
1300+
printf("FL: %-8s ", fl_str(c.IFL1));
13011301
disassemble(ins);
13021302
}
13031303
switch (c.IFL1)
@@ -1380,8 +1380,8 @@ void assignaddrc(code* c)
13801380
}
13811381
static if (0)
13821382
{
1383-
symbol_print(*s);
1384-
printf("c: %p, x%08x\n", c, c.Iop);
1383+
//symbol_print(*s);
1384+
//printf("c: %p, x%08x\n", c, c.Iop);
13851385
printf("s = %s, Soffset = %d, Para.size = %d, BPoff = %d, EBPtoESP = %d, Voffset = %d\n",
13861386
s.Sident.ptr, cast(int)s.Soffset, cast(int)cgstate.Para.size, cast(int)cgstate.BPoff,
13871387
cast(int)cgstate.EBPtoESP, cast(int)c.IEV1.Voffset);
@@ -1428,25 +1428,35 @@ void assignaddrc(code* c)
14281428
L2:
14291429
offset = cast(int)offset; // sign extend
14301430
// Load/store register (unsigned immediate) https://www.scs.stanford.edu/~zyedidia/arm64/encodingindex.html#ldst_pos
1431-
assert(field(ins,29,27) == 7);
14321431
uint opc = field(ins,23,22);
14331432
uint shift = field(ins,31,30); // 0:1 1:2 2:4 3:8 shift for imm12
14341433
uint op24 = field(ins,25,24);
14351434
//printf("offset: %lld localsize: %lld REGSIZE*2: %d\n", offset, localsize, REGSIZE*2);
14361435
if (cgstate.hasframe)
14371436
offset += REGSIZE * 2;
14381437
offset += localsize;
1439-
if (op24 == 1)
1438+
if (field(ins,28,23) == 0x22) // Add/subtract (immediate)
14401439
{
14411440
uint imm12 = field(ins,21,10); // unsigned 12 bits
1441+
//printf("imm12: %d offset: %llx\n", imm12, offset);
1442+
imm12 += offset;
1443+
assert(imm12 < 0x1000);
1444+
ins = setField(ins,21,10,imm12);
1445+
}
1446+
else if (op24 == 1)
1447+
{
1448+
assert(field(ins,29,27) == 7);
1449+
uint imm12 = field(ins,21,10); // unsigned 12 bits
14421450
offset += imm12 << shift; // add in imm
1451+
//printf("shift: %d offset: %llx imm12: %x\n", shift, offset, imm12);
14431452
assert((offset & ((1 << shift) - 1)) == 0); // no misaligned access
14441453
imm12 = cast(uint)(offset >> shift);
14451454
assert(imm12 < 0x1000);
14461455
ins = setField(ins,21,10,imm12);
14471456
}
14481457
else if (op24 == 0)
14491458
{
1459+
assert(field(ins,29,27) == 7);
14501460
if (opc == 2 && shift == 0)
14511461
shift = 4;
14521462
uint imm9 = field(ins,20,12); // signed 9 bits

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