Caches, MMU and PU

Introduction

Not strictly a GP2X feature, but nevertheless Orcus includes some utility functions to help using the CPU caches, MMU (ARM920T only) and PU (ARM940T only).

CPU	Data cache	Instruction cache	Memory unit
ARM920T	16K	16K	MMU
ARM940T	4K	4K	PU

This page is not intended to be a complete guide, to understand how the caches, MMU and PU work, and how they interact with one another, you should read the official ARM documentation:

• ARM920T
• ARM940T

Take a look at the cachemmu and secondcpu examples.

Caches

The ARM CPUs have two caches, an instruction cache and a data cache. In order to use the data cache, the MMU must be turned on. Most users will want both of these caches enabled, on both CPUs for improved performance.

MMU

The MMU (Memory Management Unit) present on the ARM920T allows one to control caching, access permissions, and virtual memory (remapping pages of physical memory into a virtual address space).

On the ARM920T, most users should just call the helper function included in Orcus after calling gp2xInit:

mmuCachesInitOn();

This creates a simple L1 table for the MMU consisting of 1MB sections with caching and buffering enabled for the first 64M (RAM), with no access controls, as well as enabling the instruction and data caching.

PU

The PU (Protection Unit) on the ARM940T is a cut down version of the MMU which doesn't have virtual memory features. One can define 8 memory regions, controlling caching and access permissions for each.

There is an equivalent helper function to enable a simple setup (first 64M RAM no access controls, instruction and data cache enabled, rest of the 4G address space not cached.

puCachesInitOn()

Note that unlike the ARM920, the instruction cache won't have any effect on the ARM940 unless the PU is enabled and the region is marked as cachable, so it is highly recommended you always enable the PU on the ARM940. If you try to access a memory address not covered by an enabled region, you will get a data abort exception.