Update DMA transfer functions to update coverage tables, and disable HLE audio when performing coverage analysis

Author: kode54

main/main.c

@@ -184,6 +184,7 @@ m64p_error main_start(usf_state_t * state)
         state->g_delay_ai = 1;
         state->g_delay_pi = 1;
         state->g_delay_dp = 1;
+        state->enable_hle_audio = 0;
     }
 
     return M64ERR_SUCCESS;

rsp/rsp_core.c

@@ -23,6 +23,8 @@
 
 #include "usf/usf_internal.h"
 
+#include "usf/barray.h"
+
 #include "rsp_lle/rsp_lle.h"
 
 #include "rsp_core.h"
@@ -53,13 +55,26 @@ void dma_sp_write(struct rsp_core* sp)
     unsigned char *spmem = (unsigned char*)sp->mem + (sp->regs[SP_MEM_ADDR_REG] & 0x1000);
     unsigned char *dram = (unsigned char*)sp->ri->rdram.dram;
 
-    for(j=0; j<count; j++) {
-        for(i=0; i<length; i++) {
-            spmem[memaddr^S8] = dram[dramaddr^S8];
-            memaddr++;
-            dramaddr++;
+    if (sp->r4300->state->enable_trimming_mode) {
+        for(j=0; j<count; j++) {
+            for(i=0; i<length; i++) {
+                spmem[memaddr^S8] = dram[dramaddr^S8];
+                if (!bit_array_test(sp->r4300->state->barray_ram_written_first, dramaddr / 4))
+                    bit_array_set(sp->r4300->state->barray_ram_read, dramaddr / 4);
+                memaddr++;
+                dramaddr++;
+            }
+            dramaddr+=skip;
+        }
+    } else {
+        for(j=0; j<count; j++) {
+            for(i=0; i<length; i++) {
+                spmem[memaddr^S8] = dram[dramaddr^S8];
+                memaddr++;
+                dramaddr++;
+            }
+            dramaddr+=skip;
         }
-        dramaddr+=skip;
     }
 }
 
@@ -79,13 +94,26 @@ void dma_sp_read(struct rsp_core* sp)
     unsigned char *spmem = (unsigned char*)sp->mem + (sp->regs[SP_MEM_ADDR_REG] & 0x1000);
     unsigned char *dram = (unsigned char*)sp->ri->rdram.dram;
 
-    for(j=0; j<count; j++) {
-        for(i=0; i<length; i++) {
-            dram[dramaddr^S8] = spmem[memaddr^S8];
-            memaddr++;
-            dramaddr++;
+    if (sp->r4300->state->enable_trimming_mode) {
+        for(j=0; j<count; j++) {
+            for(i=0; i<length; i++) {
+                dram[dramaddr^S8] = spmem[memaddr^S8];
+                if (!bit_array_test(sp->r4300->state->barray_ram_read, dramaddr / 4))
+                    bit_array_set(sp->r4300->state->barray_ram_written_first, dramaddr / 4);
+                memaddr++;
+                dramaddr++;
+            }
+            dramaddr+=skip;
+        }
+    } else {
+        for(j=0; j<count; j++) {
+            for(i=0; i<length; i++) {
+                dram[dramaddr^S8] = spmem[memaddr^S8];
+                memaddr++;
+                dramaddr++;
+            }
+            dramaddr+=skip;
         }
-        dramaddr+=skip;
     }
 }
 

si/si_controller.c

@@ -23,6 +23,8 @@
 
 #include "usf/usf_internal.h"
 
+#include "usf/barray.h"
+
 #include "si_controller.h"
 
 #include "api/m64p_types.h"
@@ -52,6 +54,16 @@ static void dma_si_write(struct si_controller* si)
     {
         *((uint32_t*)(&si->pif.ram[i])) = sl(si->ri->rdram.dram[(si->regs[SI_DRAM_ADDR_REG]+i)/4]);
     }
+    
+    if (si->r4300->state->enable_trimming_mode)
+    {
+        for (i = 0; i < PIF_RAM_SIZE; i += 4)
+        {
+            unsigned int ram_address = si->regs[SI_DRAM_ADDR_REG] + i;
+            if (!bit_array_test(si->r4300->state->barray_ram_written_first, ram_address / 4))
+                bit_array_set(si->r4300->state->barray_ram_read, ram_address / 4);
+        }
+    }
 
     update_pif_write(si);
     update_count(si->r4300->state);
@@ -81,6 +93,16 @@ static void dma_si_read(struct si_controller* si)
         si->ri->rdram.dram[(si->regs[SI_DRAM_ADDR_REG]+i)/4] = sl(*(uint32_t*)(&si->pif.ram[i]));
     }
 
+    if (si->r4300->state->enable_trimming_mode)
+    {
+        for (i = 0; i < PIF_RAM_SIZE; i += 4)
+        {
+            unsigned int ram_address = si->regs[SI_DRAM_ADDR_REG] + i;
+            if (!bit_array_test(si->r4300->state->barray_ram_read, ram_address / 4))
+                bit_array_set(si->r4300->state->barray_ram_written_first, ram_address / 4);
+        }
+    }
+
     update_count(si->r4300->state);
 
     if (si->r4300->state->g_delay_si) {