More Axoloti/STM32F427xG tweaks.

Author: deadsy

README.md

@@ -19,6 +19,7 @@ Python Based ARM CoreSight Debug and Trace Tools
 
     $ ./pycs -l
     supported targets:
+      axoloti       : Axoloti Synth Board (STM32F427xx)                          
       efm32lg       : EFM32 Leopard Gecko Starter Kit (EFM32LG990F256)
       frdm_k64f     : FRDM-K64F Kinetis Development Board (MK64FN1M0VLL12)
       mb1035b       : STM32F3 Discovery Board (STM32F303xC)
@@ -54,6 +55,7 @@ It has an interactive CLI.
  * display peripheral registers
  * halt/go the cpu
  * program flash
+ * Segger RTT client
  * measure counter frequencies
  * etc. etc.
 

cortexm.py

@@ -117,7 +117,7 @@ def __init__(self, target, ui, dbgio, device):
     self.menu = (
       ('cpuid', self.cmd_cpuid),
       ('rate', self.cmd_systick_rate),
-      ('test', self.cmd_test),
+      #('test', self.cmd_test),
     )
 
   def cmd_test(self, ui, args):

target/axoloti.py

@@ -29,7 +29,7 @@
 
 # -----------------------------------------------------------------------------
 
-soc_name = 'STM32F427xx'
+soc_name = 'STM32F427xG'
 prompt = 'axoloti'
 
 # -----------------------------------------------------------------------------
@@ -171,6 +171,8 @@ def __init__(self, ui, dbgio):
     self.ui = ui
     self.dbgio = dbgio
     self.device = vendor.get_device(self.ui, soc_name)
+    # add the 8MiB SDRAM
+    self.device.insert(soc.make_peripheral('sdram', 0xc0000000, 8 << 20, None, 'external sdram'))
     self.dbgio.connect(self.device.cpu_info.name, 'swd')
     self.cpu = cortexm.cortexm(self, ui, self.dbgio, self.device)
     self.device.bind_cpu(self.cpu)
@@ -182,16 +184,13 @@ def __init__(self, ui, dbgio):
     # setup the rtt client
     ram = self.device.sram
     self.rtt = rtt.rtt(self.cpu, mem.region('ram', ram.address, ram.size))
-    # setup the gdb server
-    self.gdb = gdb.gdb(self.cpu)
 
     self.menu_root = (
       ('cpu', self.cpu.menu, 'cpu functions'),
       ('da', self.cpu.cmd_disassemble, cortexm.help_disassemble),
       ('debugger', self.dbgio.menu, 'debugger functions'),
       ('exit', self.cmd_exit),
       ('flash', self.flash.menu, 'flash functions'),
-      ('gdb', self.gdb.run),
       ('go', self.cpu.cmd_go),
       ('gpio', self.gpio.menu, 'gpio functions'),
       ('halt', self.cpu.cmd_halt),

vendor/st/flash.py

@@ -64,8 +64,9 @@ def __str__(self):
   ('flash_option', (16,)),
 )
 
-# STM32F42xxx 2MiB dual bank
-STM32F42xxx_flash = (
+# STM32F42xxx
+
+STM32F429xI_flash = (
   ('flash_main', (16<<10,16<<10,16<<10,16<<10,64<<10,128<<10,128<<10,128<<10,128<<10,128<<10,128<<10,128<<10,
                   16<<10,16<<10,16<<10,16<<10,64<<10,128<<10,128<<10,128<<10,128<<10,128<<10,128<<10,128<<10),
                  (meta(0,1),meta(1,1),meta(2,1),meta(3,1),meta(4,1),meta(5,1),meta(6,1),meta(7,1),meta(8,1),meta(9,1),meta(10,1),meta(11,1),
@@ -76,6 +77,15 @@ def __str__(self):
   ('flash_opt_bank2', (16,),(meta(None,2),)),
 )
 
+STM32F427xG_flash = (
+  ('flash_main', (16<<10,16<<10,16<<10,16<<10,64<<10,128<<10,128<<10,128<<10,128<<10,128<<10,128<<10,128<<10),
+                 (meta(0,1),meta(1,1),meta(2,1),meta(3,1),meta(4,1),meta(5,1),meta(6,1),meta(7,1),meta(8,1),meta(9,1),meta(10,1),meta(11,1))),
+  ('flash_system', (30<<10,) * 1),
+  ('flash_otp', (528,)),
+  ('flash_opt_bank1', (16,),(meta(None,1),)),
+  ('flash_opt_bank2', (16,),(meta(None,2),)),
+)
+
 #STM32F303xD/E: Up to 512KiB
 #STM32F303x6/8, STM32F328x8: up to 64 KiB
 
@@ -103,8 +113,8 @@ def __str__(self):
 flash_map = {
   'STM32F303xC': STM32F303xC_flash,
   'STM32F407xx': STM32F40x_flash,
-  'STM32F427xx': STM32F42xxx_flash,
-  'STM32F429xI': STM32F42xxx_flash,
+  'STM32F427xG': STM32F427xG_flash,
+  'STM32F429xI': STM32F429xI_flash,
   'STM32L432KC': STM32L432KC_flash,
   'STM32F091xC': STM32F091xC_flash,
 }

vendor/st/gpio.py

@@ -20,7 +20,7 @@
   'STM32F303xC': (('A','B','C','D','E','F'), 'AHBENR', 17),
   'STM32L432KC': (('A','B','C','D','E','H'), 'AHB2ENR', 0),
   'STM32F407xx': (('A','B','C','D','E','F','G','H','I'), 'AHB1ENR', 0),
-  'STM32F427xx': (('A','B','C','D','E','F','G','H','I'), 'AHB1ENR', 0),
+  'STM32F427xG': (('A','B','C','D','E','F','G','H','I'), 'AHB1ENR', 0),
   'STM32F429xI': (('A','B','C','D','E','F','G','H','I','J','K'), 'AHB1ENR', 0),
   'STM32F091xC': (('A','B','C','D','E','F'), 'AHBENR', 17),
 }

vendor/st/st.py

@@ -491,8 +491,6 @@ def STM32F407xx_fixup(d):
 #-----------------------------------------------------------------------------
 
 def STM32F427xx_fixup(d):
-  # TODO - review and modify
-  d.soc_name = 'STM32F427xx'
   d.cpu_info.nvicPrioBits = 4
   d.cpu_info.deviceNumInterrupts = 106
   # remove some core peripherals - we'll replace them in the cpu fixup
@@ -504,14 +502,11 @@ def STM32F427xx_fixup(d):
   f.enumvals = soc.make_enumvals(f, _dev_id_enumset)
   # more decode for the GPIO registers
   gpio_decodes(d, ('A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'), _STM32F427xx_altfunc)
-  # additional interrupts
-  d.insert(soc.make_interrupt('DMA2D_IRQn', 90, 'DMA2D global Interrupt'))
   # sram
   d.insert(soc.make_peripheral('sram', 0x20000000, 256 << 10, None, 'sram'))
   d.insert(soc.make_peripheral('ccm_sram', 0x10000000, 64 << 10, None, 'core coupled memory sram'))
   d.insert(soc.make_peripheral('BKPSRAM', 0x40024000, 4 << 10, None, 'backup sram'))
   # flash (rm0090 3.4 table 6))
-  d.insert(soc.make_peripheral('flash_main', 0x08000000, 2 << 20, None, 'flash main memory'))
   d.insert(soc.make_peripheral('flash_otp', 0x1fff7800, 528, None, 'flash otp memory'))
   d.insert(soc.make_peripheral('flash_system', 0x1fff0000, 30 << 10, None, 'flash system memory'))
   d.insert(soc.make_peripheral('flash_opt_bank1', 0x1fffc000, 16, None, 'flash option memory'))
@@ -524,10 +519,15 @@ def STM32F427xx_fixup(d):
   # ram buffer for flash writing
   d.rambuf = mem.region('rambuf', 0x20000000 + 512, 32 << 10)
 
+def STM32F427xG_fixup(d):
+  d.soc_name = 'STM32F427xG'
+  # 1 MiB of flash for G devices
+  d.insert(soc.make_peripheral('flash_main', 0x08000000, 1 << 20, None, 'flash main memory'))
+
 s = soc_info()
-s.name = 'STM32F427xx'
+s.name = 'STM32F427xG'
 s.svd = 'STM32F427x'
-s.fixups = (STM32F427xx_fixup, cmregs.cm4_fixup)
+s.fixups = (STM32F427xx_fixup, STM32F427xG_fixup, cmregs.cm4_fixup)
 soc_db[s.name] = s
 
 #-----------------------------------------------------------------------------