From a6bebace253371397d40c0479df8d298695469ad Mon Sep 17 00:00:00 2001 From: umarcor Date: Thu, 21 Oct 2021 18:38:16 +0200 Subject: [PATCH] ui: split 'add_builtins' into 'add_vhdl_builtins' and 'add_verilog_builtins'; remove vunit.verilog (#559) --- examples/verilog/uart/run.py | 4 +++- examples/verilog/user_guide/run.py | 4 +++- examples/verilog/verilog_ams/run.py | 4 +++- tests/acceptance/artificial/verilog/run.py | 5 ++++- vunit/ui/__init__.py | 12 ++++++++--- vunit/verilog.py | 23 ---------------------- vunit/verilog/check/run.py | 4 +++- 7 files changed, 25 insertions(+), 31 deletions(-) delete mode 100644 vunit/verilog.py diff --git a/examples/verilog/uart/run.py b/examples/verilog/uart/run.py index edf6315ba4..a38527a6a6 100644 --- a/examples/verilog/uart/run.py +++ b/examples/verilog/uart/run.py @@ -15,11 +15,13 @@ """ from pathlib import Path -from vunit.verilog import VUnit +from vunit import VUnit SRC_PATH = Path(__file__).parent / "src" VU = VUnit.from_argv() +VU.add_verilog_builtins() + VU.add_library("uart_lib").add_source_files(SRC_PATH / "*.sv") VU.add_library("tb_uart_lib").add_source_files(SRC_PATH / "test" / "*.sv") diff --git a/examples/verilog/user_guide/run.py b/examples/verilog/user_guide/run.py index c4b00a71a4..afc4ec309a 100644 --- a/examples/verilog/user_guide/run.py +++ b/examples/verilog/user_guide/run.py @@ -15,11 +15,13 @@ """ from pathlib import Path -from vunit.verilog import VUnit +from vunit import VUnit ROOT = Path(__file__).parent VU = VUnit.from_argv() +VU.add_verilog_builtins() + VU.add_library("lib").add_source_files(ROOT / "*.sv") VU.main() diff --git a/examples/verilog/verilog_ams/run.py b/examples/verilog/verilog_ams/run.py index 3be296bae9..f018af76c1 100644 --- a/examples/verilog/verilog_ams/run.py +++ b/examples/verilog/verilog_ams/run.py @@ -7,11 +7,13 @@ # Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com from pathlib import Path -from vunit.verilog import VUnit +from vunit import VUnit ROOT = Path(__file__).parent VU = VUnit.from_argv() +VU.add_verilog_builtins() + LIB = VU.add_library("lib") LIB.add_source_files(ROOT / "*.sv") LIB.add_source_files(ROOT / "*.vams").set_compile_option("modelsim.vlog_flags", ["-ams"]) diff --git a/tests/acceptance/artificial/verilog/run.py b/tests/acceptance/artificial/verilog/run.py index 65ffeac18c..7089049413 100644 --- a/tests/acceptance/artificial/verilog/run.py +++ b/tests/acceptance/artificial/verilog/run.py @@ -5,11 +5,14 @@ # Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com from pathlib import Path -from vunit.verilog import VUnit +from vunit import VUnit + ROOT = Path(__file__).parent VU = VUnit.from_argv() +VU.add_verilog_builtins() + LIB = VU.add_library("lib") LIB.add_source_files(ROOT / "*.sv", defines={"DEFINE_FROM_RUN_PY": ""}) diff --git a/vunit/ui/__init__.py b/vunit/ui/__init__.py index 80ed8e1be6..16e31b5fbe 100644 --- a/vunit/ui/__init__.py +++ b/vunit/ui/__init__.py @@ -157,7 +157,7 @@ def test_filter(name, attribute_names): self._builtins = Builtins(self, self._vhdl_standard, simulator_class) if compile_builtins: - self.add_builtins() + self.add_vhdl_builtins() def _create_database(self): """ @@ -925,9 +925,15 @@ def _run_test(self, test_cases, report): ) runner.run(test_cases) - def add_builtins(self, external=None): + def add_verilog_builtins(self): """ - Add vunit VHDL builtin libraries + Add VUnit Verilog builtin libraries + """ + self._builtins.add_verilog_builtins() + + def add_vhdl_builtins(self, external=None): + """ + Add VUnit VHDL builtin libraries :param external: struct to provide bridges for the external VHDL API. { diff --git a/vunit/verilog.py b/vunit/verilog.py deleted file mode 100644 index 4a5bd88fd8..0000000000 --- a/vunit/verilog.py +++ /dev/null @@ -1,23 +0,0 @@ -# This Source Code Form is subject to the terms of the Mozilla Public -# License, v. 2.0. If a copy of the MPL was not distributed with this file, -# You can obtain one at http://mozilla.org/MPL/2.0/. -# -# Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com - -""" -The main public Python interface of VUnit-Verilog. -""" - -from vunit.ui import VUnit as VUnitVHDL - - -class VUnit(VUnitVHDL): - """ - VUnit Verilog interface - """ - - def add_builtins(self, external=None): # pylint: disable=arguments-differ - """ - Add vunit Verilog builtin libraries - """ - self._builtins.add_verilog_builtins() diff --git a/vunit/verilog/check/run.py b/vunit/verilog/check/run.py index f70f1fa11f..f328b0ec49 100644 --- a/vunit/verilog/check/run.py +++ b/vunit/verilog/check/run.py @@ -5,12 +5,14 @@ # Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com from pathlib import Path -from vunit.verilog import VUnit +from vunit import VUnit ROOT = Path(__file__).parent VU = VUnit.from_argv() +VU.add_verilog_builtins() + VU.add_library("lib").add_source_files(ROOT / "test" / "*.sv") VU.set_sim_option("modelsim.vsim_flags.gui", ["-novopt"])