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CVC: debug power files referencing undefined power #230

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d-m-bailey opened this issue May 12, 2021 · 0 comments
Open

CVC: debug power files referencing undefined power #230

d-m-bailey opened this issue May 12, 2021 · 0 comments

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@d-m-bailey
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When creating debug power files, the power definitions from subcircuits may be used. If the power reference from the subcircuit does not exist in the top cell of the debug hierarchy, the power file will be unusable.

The power definition should be created with the corresponding power name from the top level of the debug hierarchy.

Ex: *(vgen)/vpl=vp -> *(vgen)/vpl=VDD
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@d-m-bailey