From 56d46c24a34900b859028d321e4d29e892df9785 Mon Sep 17 00:00:00 2001 From: CyrIng Date: Wed, 4 Dec 2024 01:47:17 +0100 Subject: [PATCH] [AArch64] Display, export Floating-point Control Register `FPCR` --- aarch64/corefreq-api.h | 1 + aarch64/corefreq-cli-json.c | 4 ++ aarch64/corefreq-cli-rsc-en.h | 10 +++++ aarch64/corefreq-cli-rsc-fr.h | 7 ++++ aarch64/corefreq-cli-rsc.c | 7 ++++ aarch64/corefreq-cli-rsc.h | 7 ++++ aarch64/corefreq-cli.c | 73 +++++++++++++++++++---------------- aarch64/corefreq.h | 1 + aarch64/corefreqd.c | 3 ++ aarch64/corefreqk.c | 2 + aarch64/coretypes.h | 6 +++ 11 files changed, 87 insertions(+), 34 deletions(-) diff --git a/aarch64/corefreq-api.h b/aarch64/corefreq-api.h index e2153525..4fe2ede8 100644 --- a/aarch64/corefreq-api.h +++ b/aarch64/corefreq-api.h @@ -205,6 +205,7 @@ typedef struct Bit64 SCTLR2 __attribute__ ((aligned (8))); Bit64 EL __attribute__ ((aligned (8))); Bit64 FPSR __attribute__ ((aligned (8))); + Bit64 FPCR __attribute__ ((aligned (8))); Bit64 SVCR __attribute__ ((aligned (8))); Bit64 CPACR __attribute__ ((aligned (8))); } SystemRegister; diff --git a/aarch64/corefreq-cli-json.c b/aarch64/corefreq-cli-json.c index a0f5d04a..a7d2be75 100644 --- a/aarch64/corefreq-cli-json.c +++ b/aarch64/corefreq-cli-json.c @@ -1411,6 +1411,10 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm)) json_key(&s, "FPSR"); json_string(&s, hexStr); + snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.FPCR); + json_key(&s, "FPCR"); + json_string(&s, hexStr); + snprintf(hexStr, 32, "0x%llx", RO(Shm)->Cpu[cpu].SystemRegister.SVCR); json_key(&s, "SVCR"); json_string(&s, hexStr); diff --git a/aarch64/corefreq-cli-rsc-en.h b/aarch64/corefreq-cli-rsc-en.h index e738f6b1..7c507f57 100644 --- a/aarch64/corefreq-cli-rsc-en.h +++ b/aarch64/corefreq-cli-rsc-en.h @@ -828,6 +828,13 @@ #define RSC_SYS_REG_FPSR_DZC_CODE_EN " Divide by Zero Cumulative " #define RSC_SYS_REG_FPSR_IOC_CODE_EN " Invalid Operation Cumulative " +#define RSC_SYS_REG_FPCR_CODE_EN " Floating-point Control Register " +#define RSC_SYS_REG_FPCR_AHP_CODE_EN " Alternative Half-Precision " +#define RSC_SYS_REG_FPCR_DN_CODE_EN " Default NaN " +#define RSC_SYS_REG_FPCR_FZ_CODE_EN " Flush-to-Zero mode " +#define RSC_SYS_REG_FPCR_RM_CODE_EN " Rounding Mode " +#define RSC_SYS_REG_FPCR_FZH_CODE_EN " Flush-to-Zero on Half-precision " + #define RSC_SYS_REG_EL_CODE_EN " Exception Level " #define RSC_SYS_REG_EL_EXEC_CODE_EN " Executes in AArch64 or AArch32 " #define RSC_SYS_REG_EL_SEC_CODE_EN " Secure Exception Level " @@ -2076,6 +2083,9 @@ #define RSC_SYS_REG_HDR_FPSR_CODE \ "FPSR\0 N \0 Z \0 C \0 V \0 QC \0 IDC\0 IXC\0 UFC\0 OFC\0 DZC\0 IOC" +#define RSC_SYS_REG_HDR_FPCR_CODE \ + "FPCR\0 AHP\0 DN \0 FZ \0 RM \0 FZH" + #define RSC_SYS_REG_HDR11_EL_CODE \ " EL \0 \0"" Lev\0el0 \0 \0 Lev\0el1 \0 \0" \ " L\0evel\0""2 \0 \0 Lev\0el3 " diff --git a/aarch64/corefreq-cli-rsc-fr.h b/aarch64/corefreq-cli-rsc-fr.h index f098343d..be787f78 100644 --- a/aarch64/corefreq-cli-rsc-fr.h +++ b/aarch64/corefreq-cli-rsc-fr.h @@ -520,6 +520,13 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_SYS_REG_FPSR_DZC_CODE_FR RSC_SYS_REG_FPSR_DZC_CODE_EN #define RSC_SYS_REG_FPSR_IOC_CODE_FR RSC_SYS_REG_FPSR_IOC_CODE_EN +#define RSC_SYS_REG_FPCR_CODE_FR RSC_SYS_REG_FPCR_CODE_EN +#define RSC_SYS_REG_FPCR_AHP_CODE_FR RSC_SYS_REG_FPCR_AHP_CODE_EN +#define RSC_SYS_REG_FPCR_DN_CODE_FR RSC_SYS_REG_FPCR_DN_CODE_EN +#define RSC_SYS_REG_FPCR_FZ_CODE_FR RSC_SYS_REG_FPCR_FZ_CODE_EN +#define RSC_SYS_REG_FPCR_RM_CODE_FR RSC_SYS_REG_FPCR_RM_CODE_EN +#define RSC_SYS_REG_FPCR_FZH_CODE_FR RSC_SYS_REG_FPCR_FZH_CODE_EN + #define RSC_SYS_REG_EL_CODE_FR RSC_SYS_REG_EL_CODE_EN #define RSC_SYS_REG_EL_EXEC_CODE_FR RSC_SYS_REG_EL_EXEC_CODE_EN #define RSC_SYS_REG_EL_SEC_CODE_FR RSC_SYS_REG_EL_SEC_CODE_EN diff --git a/aarch64/corefreq-cli-rsc.c b/aarch64/corefreq-cli-rsc.c index 5c3dddd0..9ccbabb1 100644 --- a/aarch64/corefreq-cli-rsc.c +++ b/aarch64/corefreq-cli-rsc.c @@ -728,6 +728,13 @@ RESOURCE_ST Resource[] = { LDT(RSC_SYS_REG_FPSR_OFC), LDT(RSC_SYS_REG_FPSR_DZC), LDT(RSC_SYS_REG_FPSR_IOC), + LDQ(RSC_SYS_REG_HDR_FPCR), + LDT(RSC_SYS_REG_FPCR), + LDT(RSC_SYS_REG_FPCR_AHP), + LDT(RSC_SYS_REG_FPCR_DN), + LDT(RSC_SYS_REG_FPCR_FZ), + LDT(RSC_SYS_REG_FPCR_RM), + LDT(RSC_SYS_REG_FPCR_FZH), LDQ(RSC_SYS_REG_HDR11_EL), LDQ(RSC_SYS_REG_HDR12_EL), LDT(RSC_SYS_REG_EL), diff --git a/aarch64/corefreq-cli-rsc.h b/aarch64/corefreq-cli-rsc.h index 010641e1..496cbad4 100644 --- a/aarch64/corefreq-cli-rsc.h +++ b/aarch64/corefreq-cli-rsc.h @@ -551,6 +551,13 @@ enum { RSC_SYS_REG_FPSR_OFC, RSC_SYS_REG_FPSR_DZC, RSC_SYS_REG_FPSR_IOC, + RSC_SYS_REG_HDR_FPCR, + RSC_SYS_REG_FPCR, + RSC_SYS_REG_FPCR_AHP, + RSC_SYS_REG_FPCR_DN, + RSC_SYS_REG_FPCR_FZ, + RSC_SYS_REG_FPCR_RM, + RSC_SYS_REG_FPCR_FZH, RSC_SYS_REG_HDR11_EL, RSC_SYS_REG_HDR12_EL, RSC_SYS_REG_EL, diff --git a/aarch64/corefreq-cli.c b/aarch64/corefreq-cli.c index 9a3bab5d..97dc3e88 100644 --- a/aarch64/corefreq-cli.c +++ b/aarch64/corefreq-cli.c @@ -453,7 +453,7 @@ REASON_CODE SystemRegisters( Window *win, }; enum AUTOMAT { DO_END, DO_SPC, DO_CPU, DO_FLAG, DO_HCR, - DO_SCTLR, DO_SCTLR2, DO_EL, DO_FPSR, DO_ACR + DO_SCTLR, DO_SCTLR2, DO_EL, DO_FPSR, DO_FPCR, DO_ACR }; const struct SR_ST { struct SR_HDR { @@ -1064,43 +1064,43 @@ REASON_CODE SystemRegisters( Window *win, }, { .header = (struct SR_HDR[]) { - [ 0] = {&RSC(SYS_REG_HDR_CPACR).CODE()[ 0],RSC(SYS_REG_CPACR).CODE()}, - [ 1] = {&RSC(SYS_REG_HDR_CPACR).CODE()[ 5],RSC(SYS_REG_ACR_TCP).CODE()}, - [ 2] = {&RSC(SYS_REG_HDR_CPACR).CODE()[10],RSC(SYS_REG_ACR_TAM).CODE()}, - [ 3] = {&RSC(SYS_REG_HDR_CPACR).CODE()[15],RSC(SYS_REG_ACR_POE).CODE()}, - [ 4] = {&RSC(SYS_REG_HDR_CPACR).CODE()[20],RSC(SYS_REG_ACR_TTA).CODE()}, - [ 5] = {&RSC(SYS_REG_HDR_CPACR).CODE()[25],RSC(SYS_REG_ACR_SME).CODE()}, - [ 6] = {&RSC(SYS_REG_HDR_CPACR).CODE()[30],RSC(SYS_REG_ACR_FP).CODE()}, - [ 7] = {&RSC(SYS_REG_HDR_CPACR).CODE()[35],RSC(SYS_REG_ACR_ZEN).CODE()}, - [ 8] = {&RSC(SYS_REG_HDR_CPACR).CODE()[40],RSC(SYS_REG_ACR_R8).CODE()}, - [ 9] = {&RSC(SYS_REG_HDR_CPACR).CODE()[45],RSC(SYS_REG_ACR_R0).CODE()}, - [10] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, - [11] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, - [12] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, - [13] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, - [14] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, - [15] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, - [16] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [ 0] = {&RSC(SYS_REG_HDR_FPCR).CODE()[ 0],RSC(SYS_REG_FPCR).CODE()}, + [ 1] = {&RSC(SYS_REG_HDR_FPCR).CODE()[ 5],RSC(SYS_REG_FPCR_AHP).CODE()}, + [ 2] = {&RSC(SYS_REG_HDR_FPCR).CODE()[10],RSC(SYS_REG_FPCR_DN).CODE()}, + [ 3] = {&RSC(SYS_REG_HDR_FPCR).CODE()[15],RSC(SYS_REG_FPCR_FZ).CODE()}, + [ 4] = {&RSC(SYS_REG_HDR_FPCR).CODE()[20],RSC(SYS_REG_FPCR_RM).CODE()}, + [ 5] = {&RSC(SYS_REG_HDR_FPCR).CODE()[25],RSC(SYS_REG_FPCR_FZH).CODE()}, + [ 6] = {RSC(SYS_REGS_SPACE).CODE(), NULL}, + [ 7] = {&RSC(SYS_REG_HDR_CPACR).CODE()[ 0],RSC(SYS_REG_CPACR).CODE()}, + [ 8] = {&RSC(SYS_REG_HDR_CPACR).CODE()[ 5],RSC(SYS_REG_ACR_TCP).CODE()}, + [ 9] = {&RSC(SYS_REG_HDR_CPACR).CODE()[10],RSC(SYS_REG_ACR_TAM).CODE()}, + [10] = {&RSC(SYS_REG_HDR_CPACR).CODE()[15],RSC(SYS_REG_ACR_POE).CODE()}, + [11] = {&RSC(SYS_REG_HDR_CPACR).CODE()[20],RSC(SYS_REG_ACR_TTA).CODE()}, + [12] = {&RSC(SYS_REG_HDR_CPACR).CODE()[25],RSC(SYS_REG_ACR_SME).CODE()}, + [13] = {&RSC(SYS_REG_HDR_CPACR).CODE()[30],RSC(SYS_REG_ACR_FP).CODE()}, + [14] = {&RSC(SYS_REG_HDR_CPACR).CODE()[35],RSC(SYS_REG_ACR_ZEN).CODE()}, + [15] = {&RSC(SYS_REG_HDR_CPACR).CODE()[40],RSC(SYS_REG_ACR_R8).CODE()}, + [16] = {&RSC(SYS_REG_HDR_CPACR).CODE()[45],RSC(SYS_REG_ACR_R0).CODE()}, {NULL, NULL} }, .flag = (struct SR_BIT[]) { [ 0] = {DO_CPU , 1 , UNDEF_CR , 0 }, - [ 1] = {DO_ACR , 1 , ACR_TCPAC , 1 }, - [ 2] = {DO_ACR , 1 , ACR_TAM , 1 }, - [ 3] = {DO_ACR , 1 , ACR_E0POE , 1 }, - [ 4] = {DO_ACR , 1 , ACR_TTA , 1 }, - [ 5] = {DO_ACR , 1 , ACR_SMEN , 2 }, - [ 6] = {DO_ACR , 1 , ACR_FPEN , 2 }, - [ 7] = {DO_ACR , 1 , ACR_ZEN , 2 }, - [ 8] = {DO_ACR , 1 , ACR_RES8 , 8 }, - [ 9] = {DO_ACR , 1 , ACR_RES0 , 8 }, - [10] = {DO_SPC , 1 , UNDEF_CR , 0 }, - [11] = {DO_SPC , 1 , UNDEF_CR , 0 }, - [12] = {DO_SPC , 1 , UNDEF_CR , 0 }, - [13] = {DO_SPC , 1 , UNDEF_CR , 0 }, - [14] = {DO_SPC , 1 , UNDEF_CR , 0 }, - [15] = {DO_SPC , 1 , UNDEF_CR , 0 }, - [16] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [ 1] = {DO_FPCR, 1 , FPCR_AHP , 1 }, + [ 2] = {DO_FPCR, 1 , FPCR_DN , 1 }, + [ 3] = {DO_FPCR, 1 , FPCR_FZ , 1 }, + [ 4] = {DO_FPCR, 1 , FPCR_RM , 2 }, + [ 5] = {DO_FPCR, 1 , FPCR_FZH , 1 }, + [ 6] = {DO_SPC , 1 , UNDEF_CR , 0 }, + [ 7] = {DO_CPU , 1 , UNDEF_CR , 0 }, + [ 8] = {DO_ACR , 1 , ACR_TCPAC , 1 }, + [ 9] = {DO_ACR , 1 , ACR_TAM , 1 }, + [10] = {DO_ACR , 1 , ACR_E0POE , 1 }, + [11] = {DO_ACR , 1 , ACR_TTA , 1 }, + [12] = {DO_ACR , 1 , ACR_SMEN , 2 }, + [13] = {DO_ACR , 1 , ACR_FPEN , 2 }, + [14] = {DO_ACR , 1 , ACR_ZEN , 2 }, + [15] = {DO_ACR , 1 , ACR_RES8 , 8 }, + [16] = {DO_ACR , 1 , ACR_RES0 , 8 }, {DO_END , 1 , UNDEF_CR , 0 } } } @@ -1177,6 +1177,11 @@ REASON_CODE SystemRegisters( Window *win, BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.FPSR, pFlag->pos, pFlag->len)); break; + case DO_FPCR: + PRT(REG, attrib[2], "%3llx ", + BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.FPCR, + pFlag->pos, pFlag->len)); + break; case DO_ACR: PRT(REG, attrib[2], "%3llx ", BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.CPACR, diff --git a/aarch64/corefreq.h b/aarch64/corefreq.h index cf833451..42ff217b 100644 --- a/aarch64/corefreq.h +++ b/aarch64/corefreq.h @@ -192,6 +192,7 @@ typedef struct Bit64 SCTLR2 __attribute__ ((aligned (8))); Bit64 EL __attribute__ ((aligned (8))); Bit64 FPSR __attribute__ ((aligned (8))); + Bit64 FPCR __attribute__ ((aligned (8))); Bit64 SVCR __attribute__ ((aligned (8))); Bit64 CPACR __attribute__ ((aligned (8))); } SystemRegister; diff --git a/aarch64/corefreqd.c b/aarch64/corefreqd.c index 6074e146..ffdd5687 100644 --- a/aarch64/corefreqd.c +++ b/aarch64/corefreqd.c @@ -875,6 +875,9 @@ void SystemRegisters( RO(SHM_STRUCT) *RO(Shm), RO(CORE) **RO(Core), RO(Shm)->Cpu[cpu].SystemRegister.FPSR = \ RO(Core, AT(cpu))->SystemRegister.FPSR; + RO(Shm)->Cpu[cpu].SystemRegister.FPCR = \ + RO(Core, AT(cpu))->SystemRegister.FPCR; + RO(Shm)->Cpu[cpu].SystemRegister.SVCR = \ RO(Core, AT(cpu))->SystemRegister.SVCR; diff --git a/aarch64/corefreqk.c b/aarch64/corefreqk.c index b48f8cc1..f7422458 100644 --- a/aarch64/corefreqk.c +++ b/aarch64/corefreqk.c @@ -2453,6 +2453,7 @@ static void SystemRegisters(CORE_RO *Core) "mrs %[sctlr], sctlr_el1" "\n\t" "mrs %[mmfr1], id_aa64mmfr1_el1""\n\t" "mrs %[pfr0] , id_aa64pfr0_el1""\n\t" + "mrs %[fpcr] , fpcr" "\n\t" "mrs %[fpsr] , fpsr" "\n\t" "cmp xzr , xzr, lsl #0" "\n\t" "mrs x14 , nzcv" "\n\t" @@ -2467,6 +2468,7 @@ static void SystemRegisters(CORE_RO *Core) : [sctlr] "=r" (Core->SystemRegister.SCTLR), [mmfr1] "=r" (mmfr1), [pfr0] "=r" (pfr0), + [fpcr] "=r" (Core->SystemRegister.FPCR), [fpsr] "=r" (Core->SystemRegister.FPSR), [flags] "=r" (Core->SystemRegister.FLAGS) : diff --git a/aarch64/coretypes.h b/aarch64/coretypes.h index 8011ba70..d50b597d 100644 --- a/aarch64/coretypes.h +++ b/aarch64/coretypes.h @@ -289,6 +289,12 @@ enum SYS_REG { FPSR_DZC = 1, FPSR_IOC = 0, + FPCR_AHP = 26, + FPCR_DN = 25, + FPCR_FZ = 24, + FPCR_RM = 22, /* [23:22] */ + FPCR_FZH = 19, + ACR_TCPAC = 31, ACR_TAM = 30, ACR_E0POE = 29,