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Commit 421d5c5

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author
Jingqing3948
committed
implement flw, fsw, fadd.s, fsub.s
1 parent 432daf6 commit 421d5c5

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6 files changed

+51
-4
lines changed

6 files changed

+51
-4
lines changed

‎src/machine/core.cpp

+9-2
Original file line numberDiff line numberDiff line change
@@ -366,7 +366,9 @@ DecodeState Core::decode(const FetchInterstage &dt) {
366366
.ff_rs = FORWARD_NONE,
367367
.ff_rt = FORWARD_NONE,
368368
.alu_component = (flags & IMF_AMO) ? AluComponent::PASS :
369-
(flags & IMF_MUL) ? AluComponent::MUL : AluComponent::ALU,
369+
(flags & IMF_MUL) ? AluComponent::MUL :
370+
// AluComponent::ALU,
371+
(flags & (IMF_ALU_REQ_RD_F | IMF_ALU_REQ_RS_F | IMF_ALU_REQ_RT_F)) == (IMF_ALU_REQ_RD_F | IMF_ALU_REQ_RS_F | IMF_ALU_REQ_RT_F) ? AluComponent::FALU : AluComponent::ALU,
370372
.aluop = alu_op,
371373
.memctl = mem_ctl,
372374
.num_rs = num_rs,
@@ -376,8 +378,10 @@ DecodeState Core::decode(const FetchInterstage &dt) {
376378
.memwrite = bool(flags & IMF_MEMWRITE),
377379
.alusrc = bool(flags & IMF_ALUSRC),
378380
.regwrite = regwrite,
381+
.regwrite_fp = bool(flags & IMF_ALU_REQ_RD_F),
379382
.alu_req_rs = bool(flags & IMF_ALU_REQ_RS),
380383
.alu_req_rt = bool(flags & IMF_ALU_REQ_RT),
384+
.alu_fp = bool(flags & (IMF_ALU_REQ_RD_F | IMF_ALU_REQ_RS_F | IMF_ALU_REQ_RT_F)), // maybe not correct
381385
.branch_bxx = bool(flags & IMF_BRANCH),
382386
.branch_jal = bool(flags & IMF_JUMP),
383387
.branch_val = bool(flags & IMF_BJ_NOT),
@@ -451,6 +455,8 @@ ExecuteState Core::execute(const DecodeInterstage &dt) {
451455
.memread = dt.memread,
452456
.memwrite = dt.memwrite,
453457
.regwrite = dt.regwrite,
458+
.regwrite_fp = dt.regwrite_fp,
459+
.alu_fp = dt.alu_fp,
454460
.is_valid = dt.is_valid,
455461
.branch_bxx = dt.branch_bxx,
456462
.branch_jal = dt.branch_jal,
@@ -546,13 +552,14 @@ MemoryState Core::memory(const ExecuteInterstage &dt) {
546552
.num_rd = dt.num_rd,
547553
.memtoreg = memread,
548554
.regwrite = regwrite,
555+
.regwrite_fp = dt.regwrite_fp,
549556
.is_valid = dt.is_valid,
550557
.csr_written = csr_written,
551558
} };
552559
}
553560

554561
WritebackState Core::writeback(const MemoryInterstage &dt) {
555-
if (dt.regwrite) { regs->write_gp(dt.num_rd, dt.towrite_val); }
562+
if (dt.regwrite) { (dt.regwrite_fp) ? regs->write_fp(dt.num_rd, dt.towrite_val) : regs->write_gp(dt.num_rd, dt.towrite_val); }
556563

557564
return WritebackState { WritebackInternalState {
558565
.inst = (dt.excause == EXCAUSE_NONE)? dt.inst: Instruction::NOP,

‎src/machine/execute/alu.cpp

+14
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,9 @@ RegisterValue alu_combined_operate(
1717
: alu64_operate(op.alu_op, modified, a, b);
1818
case AluComponent::MUL:
1919
return (w_operation) ? mul32_operate(op.mul_op, a, b) : mul64_operate(op.mul_op, a, b);
20+
case AluComponent::FALU:
21+
// return (w_operation) ? alu32f_operate(op.alu_op, modified, a, b) : alu64f_operate(op.alu_op, modified, a, b);
22+
return alu32f_operate(op.alu_op, modified, a, b);
2023
case AluComponent::PASS:
2124
return a;
2225
default: qDebug("ERROR, unknown alu component: %hhx", uint8_t(component)); return 0;
@@ -74,6 +77,17 @@ int32_t alu32_operate(AluOp op, bool modified, RegisterValue a, RegisterValue b)
7477
}
7578
}
7679

80+
int32_t alu32f_operate(AluOp op, bool modified, RegisterValue a, RegisterValue b) {
81+
return alu32_operate(op, modified, a, b);
82+
// switch (op) {
83+
// case AluOp::ADD: {
84+
// float result = (a.as_f32()) + ((modified) ? - (b.as_f32()) : (b.as_f32()));
85+
// return *reinterpret_cast<int32_t*>(&result);
86+
// }
87+
// default: qDebug("ERROR, unknown alu operation: %hhx", uint8_t(op)); return 0;
88+
// }
89+
}
90+
7791
int64_t mul64_operate(MulOp op, RegisterValue a, RegisterValue b) {
7892
switch (op) {
7993
case MulOp::MUL: return a.as_u64() * b.as_u64();

‎src/machine/execute/alu.h

+17
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ namespace machine {
1515
enum class AluComponent {
1616
ALU, //> RV32/64I
1717
MUL, //> RV32/64M
18+
FALU, //> RV32/64F
1819
PASS, //> Pass operand A without change (used for AMO)
1920
};
2021

@@ -74,6 +75,22 @@ union AluCombinedOp {
7475
*/
7576
[[gnu::const]] int32_t alu32_operate(AluOp op, bool modified, RegisterValue a, RegisterValue b);
7677

78+
/**
79+
* RV32F for OP and OP-IMM instructions and RV64F OP-32 and OP-IMM-32
80+
*
81+
* ALU conforming to Base Integer Instruction Set, Version 2.0.
82+
*
83+
* @param op operation specifier (funct3 in instruction)
84+
* @param modified modifies behavior of ADD (to SUB) and SRL (to SRA)
85+
* encoded by bit 30 if applicable
86+
* @param a operand 1
87+
* @param b operand 2
88+
* @return result of specified ALU operation (always, no traps)
89+
* integer type is returned to ensure correct signe extension
90+
* to arbitrary implementation of RegisterValue
91+
*/
92+
[[gnu::const]] int32_t alu32f_operate(AluOp op, bool modified, RegisterValue a, RegisterValue b);
93+
7794
/**
7895
* RV64 "M" for OP instructions
7996
*

‎src/machine/machineconfig.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ enum ConfigPresets {
2727
};
2828

2929
constexpr ConfigIsaWord config_isa_word_default = ConfigIsaWord::byChar('E') | ConfigIsaWord::byChar('I') |
30-
ConfigIsaWord::byChar('A') |ConfigIsaWord::byChar('M');
30+
ConfigIsaWord::byChar('A') | ConfigIsaWord::byChar('M') | ConfigIsaWord::byChar('F');
3131

3232
constexpr ConfigIsaWord config_isa_word_fixed = ConfigIsaWord::byChar('E') | ConfigIsaWord::byChar('I');
3333

‎src/machine/pipeline.h

+5
Original file line numberDiff line numberDiff line change
@@ -102,8 +102,10 @@ struct DecodeInterstage {
102102
bool memwrite = false; // If memory should write input
103103
bool alusrc = false; // If second value to alu is immediate value (rt used otherwise)
104104
bool regwrite = false; // If output should be written back to register
105+
bool regwrite_fp = false; // If output should be written back to floating point register
105106
bool alu_req_rs = false; // requires rs value for ALU
106107
bool alu_req_rt = false; // requires rt value for ALU or SW
108+
bool alu_fp = false; // ALU operation is floating point
107109
bool branch_bxx = false; // branch instruction
108110
bool branch_jal = false; // jump
109111
bool branch_val = false; // negate branch condition
@@ -170,6 +172,8 @@ struct ExecuteInterstage {
170172
bool memread = false;
171173
bool memwrite = false;
172174
bool regwrite = false;
175+
bool regwrite_fp = false;
176+
bool alu_fp = false;
173177
bool is_valid = false;
174178
bool branch_bxx = false;
175179
bool branch_jal = false;
@@ -243,6 +247,7 @@ struct MemoryInterstage {
243247
RegisterId num_rd = 0;
244248
bool memtoreg = false;
245249
bool regwrite = false;
250+
bool regwrite_fp = false;
246251
bool is_valid = false;
247252
bool csr_written = false;
248253

‎src/machine/register_value.h

+5-1
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,9 @@ class RegisterValue {
7979

8080
[[nodiscard]] constexpr inline int32_t as_i32() const { return (int32_t)data; };
8181

82-
[[nodiscard]] constexpr inline uint32_t as_u32() const { return (uint32_t)data; };
82+
[[nodiscard]] constexpr inline uint32_t as_u32() const { return (uint32_t)data; };
83+
84+
[[nodiscard]] constexpr inline float as_f32() const { union { uint32_t u; float f; } u = {(size_t)data}; return u.f; };
8385

8486
[[nodiscard]] constexpr inline int64_t as_i64() const { return (int64_t)data; };
8587

@@ -97,6 +99,8 @@ class RegisterValue {
9799

98100
constexpr explicit operator uint32_t() const { return as_u32(); };
99101

102+
constexpr explicit operator float() const { return as_f32(); };
103+
100104
constexpr explicit operator int64_t() const { return as_i64(); };
101105

102106
constexpr explicit operator uint64_t() const { return as_u64(); };

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