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FinalDisplay.syr
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FinalDisplay.syr
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Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.25 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.25 secs
--> Reading design: FinalDisplay.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "FinalDisplay.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "FinalDisplay"
Output Format : NGC
Target Device : CoolRunner2 CPLDs
---- Source Options
Top Module Name : FinalDisplay
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : Yes
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : Yes
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Verilog 2001 : YES
---- Other Options
Clock Enable : YES
wysiwyg : NO
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/puber/Desktop/FinalDisplay/FinalDisplay.vhd" in Library work.
Entity <finaldisplay> compiled.
Entity <finaldisplay> (Architecture <behavioral>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <FinalDisplay> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <FinalDisplay> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/Users/puber/Desktop/FinalDisplay/FinalDisplay.vhd" line 161: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<SEC1>, <SEC2>, <MIN1>, <MIN2>
WARNING:Xst:819 - "C:/Users/puber/Desktop/FinalDisplay/FinalDisplay.vhd" line 210: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<set>, <set_min>, <MIN1>, <MIN2>, <set_hour>, <hour24>, <hour1>, <hour2>, <dot>, <set_day>, <month>, <day1>, <day2>, <set_month>, <RESET>
Entity <FinalDisplay> analyzed. Unit <FinalDisplay> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <FinalDisplay>.
Related source file is "C:/Users/puber/Desktop/FinalDisplay/FinalDisplay.vhd".
WARNING:Xst:653 - Signal <hour24<0>> is used but never assigned. This sourceless signal will be automatically connected to value 0.
INFO:Xst:1608 - Relative priorities of control signals on register <hour2> differ from those commonly found in the selected device family. This will result in additional logic around the register.
Found 16x7-bit ROM for signal <DISPLAY>.
Found 8-bit adder for signal <$add0000> created at line 294.
Found 1-of-4 decoder for signal <AN>.
Found 26-bit up counter for signal <CLK_COUNTER>.
Found 2-bit up counter for signal <COUNTER>.
Found 26-bit comparator greatequal for signal <COUNTER$cmp_ge0000> created at line 131.
Found 4-bit register for signal <day1>.
Found 4-bit adder for signal <day1$addsub0000> created at line 309.
Found 4-bit comparator equal for signal <day1$cmp_eq0000> created at line 290.
Found 4-bit comparator equal for signal <day1$cmp_eq0001> created at line 290.
Found 4-bit register for signal <day2>.
Found 4-bit comparator not equal for signal <day2$cmp_ne0001> created at line 386.
Found 4-bit comparator not equal for signal <day2$cmp_ne0002> created at line 386.
Found 4-bit adder for signal <day2$share0000>.
Found 1-bit register for signal <dot<0>>.
Found 4-bit register for signal <hour1>.
Found 4-bit register for signal <hour2>.
Found 4-bit comparator lessequal for signal <hour2$cmp_le0000> created at line 475.
Found 4-bit adder for signal <hour2$share0000>.
Found 4-bit register for signal <maxday1>.
Found 4-bit register for signal <maxday2>.
Found 4-bit up counter for signal <MIN1>.
Found 4-bit adder for signal <MIN1$addsub0000> created at line 451.
Found 4-bit register for signal <MIN2>.
Found 4-bit adder for signal <MIN2$addsub0000> created at line 419.
Found 8-bit register for signal <month>.
Found 4-bit adder for signal <mux0000$add0000> created at line 468.
Found 4-bit comparator greater for signal <mux0000$cmp_gt0000> created at line 463.
Found 4-bit comparator greater for signal <mux0000$cmp_gt0001> created at line 463.
Found 4-bit comparator greater for signal <mux0000$cmp_gt0002> created at line 475.
Found 4-bit comparator greater for signal <mux0000$cmp_gt0003> created at line 482.
Found 8-bit comparator less for signal <mux0002$cmp_lt0000> created at line 562.
Found 4-bit 4-to-1 multiplexer for signal <NUMBER>.
Found 4-bit up counter for signal <SEC1>.
Found 4-bit up counter for signal <SEC2>.
Summary:
inferred 1 ROM(s).
inferred 5 Counter(s).
inferred 12 D-type flip-flop(s).
inferred 7 Adder/Subtractor(s).
inferred 11 Comparator(s).
inferred 1 Decoder(s).
Unit <FinalDisplay> synthesized.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
=========================================================================
HDL Synthesis Report
Macro Statistics
# ROMs : 1
16x7-bit ROM : 1
# Adders/Subtractors : 7
4-bit adder : 6
8-bit adder : 1
# Counters : 5
2-bit up counter : 1
26-bit up counter : 1
4-bit up counter : 3
# Registers : 19
1-bit register : 13
4-bit register : 6
# Comparators : 11
26-bit comparator greatequal : 1
4-bit comparator equal : 2
4-bit comparator greater : 4
4-bit comparator lessequal : 1
4-bit comparator not equal : 2
8-bit comparator less : 1
# Multiplexers : 1
4-bit 4-to-1 multiplexer : 1
# Decoders : 1
1-of-4 decoder : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# ROMs : 1
16x7-bit ROM : 1
# Adders/Subtractors : 7
4-bit adder : 6
8-bit adder : 1
# Counters : 5
2-bit up counter : 1
26-bit up counter : 1
4-bit up counter : 3
# Registers : 12
Flip-Flops : 12
# Comparators : 2
4-bit comparator equal : 2
# Multiplexers : 1
4-bit 4-to-1 multiplexer : 1
# Decoders : 1
1-of-4 decoder : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:2677 - Node <month_0> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <month_1> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <month_2> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <month_3> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <month_4> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <month_5> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <month_6> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <month_7> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <maxday1_0> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <maxday1_1> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <maxday1_2> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <maxday1_3> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <maxday2_0> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <maxday2_1> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <maxday2_2> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <maxday2_3> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <dot_0> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <hour2_1> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <hour2_2> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <hour2_3> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <day2_0> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <day2_1> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <day2_2> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <day2_3> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <hour2_0> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <hour1_0> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <hour1_1> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <hour1_2> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <hour1_3> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <day1_0> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <day1_1> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <day1_2> of sequential type is unconnected in block <FinalDisplay>.
WARNING:Xst:2677 - Node <day1_3> of sequential type is unconnected in block <FinalDisplay>.
Optimizing unit <FinalDisplay> ...
implementation constraint: INIT=r : SEC2_0
implementation constraint: INIT=r : SEC1_0
implementation constraint: INIT=r : MIN1_2
implementation constraint: INIT=r : MIN2_3
implementation constraint: INIT=r : MIN2_2
implementation constraint: INIT=r : MIN2_1
implementation constraint: INIT=r : MIN2_0
implementation constraint: INIT=r : SEC2_2
implementation constraint: INIT=r : CLK_COUNTER_23
implementation constraint: INIT=r : CLK_COUNTER_24
implementation constraint: INIT=r : COUNTER_1
implementation constraint: INIT=r : COUNTER_0
implementation constraint: INIT=r : CLK_COUNTER_19
implementation constraint: INIT=r : CLK_COUNTER_20
implementation constraint: INIT=r : CLK_COUNTER_21
implementation constraint: INIT=r : CLK_COUNTER_22
implementation constraint: INIT=r : SEC2_1
implementation constraint: INIT=r : MIN1_0
implementation constraint: INIT=r : MIN1_3
implementation constraint: INIT=r : SEC2_3
implementation constraint: INIT=r : CLK_COUNTER_25
implementation constraint: INIT=r : CLK_COUNTER_16
implementation constraint: INIT=r : CLK_COUNTER_17
implementation constraint: INIT=r : CLK_COUNTER_18
implementation constraint: INIT=r : CLK_COUNTER_13
implementation constraint: INIT=r : CLK_COUNTER_14
implementation constraint: INIT=r : CLK_COUNTER_15
implementation constraint: INIT=r : CLK_COUNTER_10
implementation constraint: INIT=r : CLK_COUNTER_11
implementation constraint: INIT=r : CLK_COUNTER_12
implementation constraint: INIT=r : CLK_COUNTER_7
implementation constraint: INIT=r : CLK_COUNTER_8
implementation constraint: INIT=r : CLK_COUNTER_9
implementation constraint: INIT=r : CLK_COUNTER_0
implementation constraint: INIT=r : CLK_COUNTER_1
implementation constraint: INIT=r : CLK_COUNTER_2
implementation constraint: INIT=r : CLK_COUNTER_3
implementation constraint: INIT=r : CLK_COUNTER_4
implementation constraint: INIT=r : CLK_COUNTER_5
implementation constraint: INIT=r : CLK_COUNTER_6
implementation constraint: INIT=r : SEC1_3
implementation constraint: INIT=r : SEC1_2
implementation constraint: INIT=r : SEC1_1
implementation constraint: INIT=r : MIN1_1
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : FinalDisplay.ngr
Top Level Output File Name : FinalDisplay
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : Yes
Target Technology : CoolRunner2 CPLDs
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 20
Cell Usage :
# BELS : 385
# AND2 : 169
# AND3 : 3
# AND4 : 6
# GND : 1
# INV : 114
# OR2 : 50
# OR3 : 1
# OR4 : 1
# OR8 : 1
# XOR2 : 39
# FlipFlops/Latches : 44
# FD : 26
# FDC : 4
# FDCE : 6
# FDCPE : 8
# IO Buffers : 17
# IBUF : 5
# OBUF : 12
=========================================================================
Total REAL time to Xst completion: 12.00 secs
Total CPU time to Xst completion: 12.19 secs
-->
Total memory usage is 4572788 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 36 ( 0 filtered)
Number of infos : 2 ( 0 filtered)