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FinalDisplay.rpt
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FinalDisplay.rpt
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cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: FinalDisplay Date: 4-19-2021, 6:48PM
Device Used: XC2C256-7-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
81 /256 ( 32%) 213 /896 ( 24%) 189 /640 ( 30%) 44 /256 ( 17%) 17 /118 ( 14%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO CTC CTR CTS CTE
Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1 16/16* 3/40 4/56 0/ 6 0/1 0/1 0/1 0/1
FB2 16/16* 31/40 36/56 0/ 8 0/1 0/1 0/1 0/1
FB3 16/16* 35/40 55/56 0/ 6 1/1* 1/1* 1/1* 0/1
FB4 16/16* 31/40 36/56 0/ 8 1/1* 1/1* 1/1* 0/1
FB5 3/16 21/40 10/56 0/ 5 1/1* 1/1* 1/1* 0/1
FB6 2/16 21/40 10/56 0/ 8 1/1* 1/1* 1/1* 0/1
FB7 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1
FB8 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1
FB9 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1
FB10 0/16 0/40 0/56 0/ 9 0/1 0/1 0/1 0/1
FB11 4/16 2/40 4/56 4/ 8 0/1 0/1 0/1 0/1
FB12 0/16 0/40 0/56 0/ 6 0/1 0/1 0/1 0/1
FB13 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1
FB14 2/16 20/40 10/56 2/ 8 0/1 0/1 0/1 0/1
FB15 0/16 0/40 0/56 0/ 7 0/1 0/1 0/1 0/1
FB16 6/16 25/40 48/56 6/ 7 0/1 0/1 0/1 0/1
----- ------- ------- ----- --- --- --- ---
Total 81/256 189/640 213/896 12/118 4/16 4/16 4/16 0/16
CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable
* - Resource is exhausted
** Global Control Resources **
GCK GSR GTS DGE
Used/Tot Used/Tot Used/Tot Used/Tot
1/3 0/1 0/4 0/1
Signal 'CLK' mapped onto global clock net GCK2.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 4 4 | I/O : 14 108
Output : 12 12 | GCK/IO : 2 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 1 1 | GSR/IO : 1 1
GTS : 0 0 | CDR/IO : 0 1
GSR : 0 0 | DGE/IO : 0 1
---- ----
Total 17 17
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'FinalDisplay.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK' based upon the LOC
constraint 'P38'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
WARNING:Cpld - Unable to map all desired signals into function block, FB16.
Buffering output signal C_B to allow all signals assigned to this function
block to be placed.
************************* Summary of Mapped Logic ************************
** 12 Outputs **
Signal Total Total Bank Loc Pin Pin Pin I/O I/O Slew Reg Reg Init
Name Pts Inps No. Type Use STD Style Rate Use State
AN4 1 2 2 FB11_13 126 I/O O LVCMOS18 FAST
AN3 1 2 2 FB11_14 128 I/O O LVCMOS18 FAST
AN2 1 2 2 FB11_15 129 I/O O LVCMOS18 FAST
AN1 1 2 2 FB11_16 130 I/O O LVCMOS18 FAST
LD0 1 1 1 FB14_4 69 I/O O LVCMOS18 FAST
C_G 9 19 1 FB14_16 61 I/O O LVCMOS18 FAST
C_C 12 18 1 FB16_5 60 I/O O LVCMOS18 FAST
C_D 14 24 1 FB16_11 58 I/O O LVCMOS18 FAST
C_E 8 18 1 FB16_12 57 I/O O LVCMOS18 FAST
C_A 13 20 1 FB16_13 56 I/O O LVCMOS18 FAST
C_F 9 20 1 FB16_15 54 I/O O LVCMOS18 FAST
C_B 1 1 1 FB16_16 53 I/O O LVCMOS18 FAST
** 69 Buried Nodes **
Signal Total Total Loc Reg Reg Init
Name Pts Inps Use State
CLK_COUNTER<22> 0 0 FB1_1 DFF RESET
CLK_COUNTER<21> 0 0 FB1_2 DFF RESET
CLK_COUNTER<1> 2 3 FB1_3 DFF RESET
CLK_COUNTER<0> 1 2 FB1_4 DFF RESET
CLK_COUNTER<20> 0 0 FB1_5 DFF RESET
COUNTER<0> 1 1 FB1_6 TFF RESET
CLK_COUNTER<19> 0 0 FB1_7 DFF RESET
CLK_COUNTER<18> 0 0 FB1_8 DFF RESET
CLK_COUNTER<17> 0 0 FB1_9 DFF RESET
CLK_COUNTER<16> 0 0 FB1_10 DFF RESET
CLK_COUNTER<15> 0 0 FB1_11 DFF RESET
CLK_COUNTER<25> 0 0 FB1_12 DFF RESET
CLK_COUNTER<24> 0 0 FB1_13 DFF RESET
CLK_COUNTER<23> 0 0 FB1_14 DFF RESET
CLK_COUNTER<14> 0 0 FB1_15 DFF RESET
CLK_COUNTER<13> 0 0 FB1_16 DFF RESET
N_PZ_378 1 3 FB2_1
CLK_COUNTER<11> 6 21 FB2_2 DFF RESET
CLK_COUNTER<2> 2 5 FB2_3 DFF RESET
N_PZ_344 1 3 FB2_4
CLK_COUNTER<8> 2 3 FB2_5 DFF RESET
CLK_COUNTER<7> 2 5 FB2_6 DFF RESET
CLK_COUNTER<6> 2 3 FB2_7 DFF RESET
N_PZ_374 1 4 FB2_8
CLK_COUNTER<5> 2 6 FB2_9 DFF RESET
CLK_COUNTER<4> 2 4 FB2_10 TFF RESET
CLK_COUNTER<3> 2 3 FB2_11 DFF RESET
CLK_COUNTER<9> 2 4 FB2_12 TFF RESET
CLK_COUNTER<12> 2 7 FB2_13 DFF RESET
CLK_COUNTER<10> 2 18 FB2_14 TFF RESET
N_PZ_342 6 20 FB2_15
COUNTER<1> 1 2 FB2_16 TFF RESET
MIN1_1__or0000 3 7 FB3_1
MIN2_2_or0000 3 8 FB3_2
MIN2_3_or0000 4 9 FB3_3
SEC1<3> 4 6 FB3_4 TFF RESET
MIN1_2__or0000 3 8 FB3_5
SEC2<0> 3 6 FB3_6 TFF RESET
SEC2<3> 3 9 FB3_7 TFF RESET
SEC2<1> 5 10 FB3_8 TFF RESET
Signal Total Total Loc Reg Reg Init
Name Pts Inps Use State
SEC2<2> 4 10 FB3_9 TFF RESET
N_PZ_362 3 9 FB3_10
N_PZ_303 4 14 FB3_11
C_B_BUFR 11 17 FB3_12
MIN1<2> 7 19 FB3_13 TFF RESET
MIN1_0__or0000 3 8 FB3_14
MIN1<3> 6 22 FB3_15 TFF RESET
SEC1<1> 4 6 FB3_16 TFF RESET
MIN1_cmp_eq0000 1 4 FB4_1
MIN1_addsub0000<2> 2 3 FB4_2
N_PZ_292 2 2 FB4_3
N_PZ_294 3 4 FB4_4
MIN2_mux0000<2> 3 4 FB4_5
N_PZ_293 2 4 FB4_6
N_PZ_488 1 2 FB4_7
N_PZ_325 1 2 FB4_8
SEC1<2> 3 4 FB4_9 TFF RESET
MIN1_3__or0000 3 7 FB4_10
MIN2_1_or0000 2 5 FB4_11
MIN2_addsub0000<2> 2 3 FB4_12
MIN2_0_or0000 2 5 FB4_13
SEC1<0> 2 2 FB4_14 TFF RESET
MIN2<1> 5 17 FB4_15 TFF RESET
MIN1<1> 7 19 FB4_16 TFF RESET
MIN2<2> 5 16 FB5_13 TFF RESET
MIN2<0> 4 15 FB5_15 TFF RESET
MIN1_addsub0000<3> 2 3 FB5_16
MIN1<0> 6 18 FB6_10 TFF RESET
MIN2<3> 5 16 FB6_11 TFF RESET
** 5 Inputs **
Signal Bank Loc Pin Pin Pin I/O I/O
Name No. Type Use STD Style
RESET 2 FB1_3 143 GSR/I/O I LVCMOS18 KPR
clk2 2 FB2_15 10 I/O I LVCMOS18 KPR
set 1 FB5_2 33 I/O I LVCMOS18 KPR
set_min 1 FB5_4 32 GCK/I/O I LVCMOS18 KPR
CLK 1 FB6_4 38 GCK/I/O GCK LVCMOS18 KPR
Legend:
Pin No. - ~ - User Assigned
I/O Style - OD - OpenDrain
- PU - Pullup
- KPR - Keeper
- S - SchmittTrigger
- DG - DataGate
Reg Use - LATCH - Transparent latch
- DFF - D-flip-flop
- DEFF - D-flip-flop with clock enable
- TFF - T-flip-flop
- TDFF - Dual-edge-triggered T-flip-flop
- DDFF - Dual-edge-triggered flip-flop
- DDEFF - Dual-edge-triggered flip-flop with clock enable
/S (after any above flop/latch type) indicates initial state is Set
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
VRF - Vref
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 3/37
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 4/52
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
CLK_COUNTER<22> 0 FB1_1 (b) (b)
CLK_COUNTER<21> 0 FB1_2 (b) (b)
CLK_COUNTER<1> 2 FB1_3 143 GSR/I/O I
CLK_COUNTER<0> 1 FB1_4 142 I/O (b)
CLK_COUNTER<20> 0 FB1_5 (b) (b)
COUNTER<0> 1 FB1_6 140 I/O (b)
CLK_COUNTER<19> 0 FB1_7 (b) (b)
CLK_COUNTER<18> 0 FB1_8 (b) (b)
CLK_COUNTER<17> 0 FB1_9 (b) (b)
CLK_COUNTER<16> 0 FB1_10 (b) (b)
CLK_COUNTER<15> 0 FB1_11 (b) (b)
CLK_COUNTER<25> 0 FB1_12 139 I/O (b)
CLK_COUNTER<24> 0 FB1_13 138 I/O (b)
CLK_COUNTER<23> 0 FB1_14 137 I/O (b)
CLK_COUNTER<14> 0 FB1_15 (b) (b)
CLK_COUNTER<13> 0 FB1_16 (b) (b)
Signals Used by Logic in Function Block
1: CLK_COUNTER<0> 2: CLK_COUNTER<1> 3: N_PZ_342
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
CLK_COUNTER<22> ........................................ 0
CLK_COUNTER<21> ........................................ 0
CLK_COUNTER<1> XXX..................................... 3
CLK_COUNTER<0> X.X..................................... 2
CLK_COUNTER<20> ........................................ 0
COUNTER<0> ..X..................................... 1
CLK_COUNTER<19> ........................................ 0
CLK_COUNTER<18> ........................................ 0
CLK_COUNTER<17> ........................................ 0
CLK_COUNTER<16> ........................................ 0
CLK_COUNTER<15> ........................................ 0
CLK_COUNTER<25> ........................................ 0
CLK_COUNTER<24> ........................................ 0
CLK_COUNTER<23> ........................................ 0
CLK_COUNTER<14> ........................................ 0
CLK_COUNTER<13> ........................................ 0
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 31/9
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 36/20
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
N_PZ_378 1 FB2_1 2 GTS/I/O (b)
CLK_COUNTER<11> 6 FB2_2 (b) (b)
CLK_COUNTER<2> 2 FB2_3 3 GTS/I/O (b)
N_PZ_344 1 FB2_4 4 I/O (b)
CLK_COUNTER<8> 2 FB2_5 5 GTS/I/O (b)
CLK_COUNTER<7> 2 FB2_6 (b) (b)
CLK_COUNTER<6> 2 FB2_7 (b) (b)
N_PZ_374 1 FB2_8 (b) (b)
CLK_COUNTER<5> 2 FB2_9 (b) (b)
CLK_COUNTER<4> 2 FB2_10 (b) (b)
CLK_COUNTER<3> 2 FB2_11 (b) (b)
CLK_COUNTER<9> 2 FB2_12 6 GTS/I/O (b)
CLK_COUNTER<12> 2 FB2_13 7 I/O (b)
CLK_COUNTER<10> 2 FB2_14 9 I/O (b)
N_PZ_342 6 FB2_15 10 I/O I
COUNTER<1> 1 FB2_16 (b) (b)
Signals Used by Logic in Function Block
1: CLK_COUNTER<0> 12: CLK_COUNTER<1> 22: CLK_COUNTER<5>
2: CLK_COUNTER<10> 13: CLK_COUNTER<20> 23: CLK_COUNTER<6>
3: CLK_COUNTER<11> 14: CLK_COUNTER<21> 24: CLK_COUNTER<7>
4: CLK_COUNTER<12> 15: CLK_COUNTER<22> 25: CLK_COUNTER<8>
5: CLK_COUNTER<13> 16: CLK_COUNTER<23> 26: CLK_COUNTER<9>
6: CLK_COUNTER<14> 17: CLK_COUNTER<24> 27: COUNTER<0>
7: CLK_COUNTER<15> 18: CLK_COUNTER<25> 28: N_PZ_342
8: CLK_COUNTER<16> 19: CLK_COUNTER<2> 29: N_PZ_344
9: CLK_COUNTER<17> 20: CLK_COUNTER<3> 30: N_PZ_374
10: CLK_COUNTER<18> 21: CLK_COUNTER<4> 31: N_PZ_378
11: CLK_COUNTER<19>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
N_PZ_378 X..........X......X..................... 3
CLK_COUNTER<11> .XXXXXXXXXX.XXXXXX....XXXX..X........... 21
CLK_COUNTER<2> X..........X......X........X..X......... 5
N_PZ_344 ......................XX.....X.......... 3
CLK_COUNTER<8> ........................X..XX........... 3
CLK_COUNTER<7> ......................XX...XXX.......... 5
CLK_COUNTER<6> ......................X....X.X.......... 3
N_PZ_374 ...................XXX........X......... 4
CLK_COUNTER<5> ...................XXX.....X.XX......... 6
CLK_COUNTER<4> ...................XX......X..X......... 4
CLK_COUNTER<3> ...................X.......X..X......... 3
CLK_COUNTER<9> ........................XX.XX........... 4
CLK_COUNTER<12> .XXX....................XX.XX........... 7
CLK_COUNTER<10> .X..XXXXXXX.XXXXXX......XX.XX........... 18
N_PZ_342 .XXXXXXXXXX.XXXXXX....XXXX.............. 20
COUNTER<1> ..........................XX............ 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 35/5
Number of function block control terms used/remaining: 3/1
Number of PLA product terms used/remaining: 55/1
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
MIN1_1__or0000 3 FB3_1 136 I/O (b)
MIN2_2_or0000 3 FB3_2 135 I/O (b)
MIN2_3_or0000 4 FB3_3 134 I/O (b)
SEC1<3> 4 FB3_4 (b) (b) +
MIN1_2__or0000 3 FB3_5 133 I/O (b)
SEC2<0> 3 FB3_6 (b) (b) +
SEC2<3> 3 FB3_7 (b) (b) +
SEC2<1> 5 FB3_8 (b) (b) +
SEC2<2> 4 FB3_9 (b) (b) +
N_PZ_362 3 FB3_10 (b) (b)
N_PZ_303 4 FB3_11 (b) (b)
C_B_BUFR 11 FB3_12 (b) (b)
MIN1<2> 7 FB3_13 (b) (b) + +
MIN1_0__or0000 3 FB3_14 132 I/O (b)
MIN1<3> 6 FB3_15 (b) (b) + +
SEC1<1> 4 FB3_16 131 I/O (b) +
Signals Used by Logic in Function Block
1: COUNTER<0> 13: MIN2<1> 25: SEC1<0>
2: COUNTER<1> 14: MIN2<2> 26: SEC1<1>
3: MIN1<0> 15: MIN2<3> 27: SEC1<2>
4: MIN1<1> 16: MIN2_0_or0000 28: SEC1<3>
5: MIN1<2> 17: MIN2_addsub0000<2> 29: SEC2<0>
6: MIN1<3> 18: MIN2_mux0000<2> 30: SEC2<1>
7: MIN1_2__or0000 19: N_PZ_292 31: SEC2<2>
8: MIN1_3__or0000 20: N_PZ_303 32: SEC2<3>
9: MIN1_addsub0000<2> 21: N_PZ_325 33: clk2
10: MIN1_addsub0000<3> 22: N_PZ_362 34: set
11: MIN1_cmp_eq0000 23: N_PZ_488 35: set_min
12: MIN2<0> 24: RESET
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
MIN1_1__or0000 ............X..X.XX....X.........XX..... 7
MIN2_2_or0000 ..........X..X.XXX.....X.........XX..... 8
MIN2_3_or0000 ..........X.XXXXX......X.........XX..... 9
SEC1<3> ......................X.XXXX....X....... 6
MIN1_2__or0000 ........X.X.X..X.X.....X.........XX..... 8
SEC2<0> ......................X.XXXX....X....... 6
SEC2<3> ......................X.XXXXXXX.X....... 9
SEC2<1> ......................X.XXXXXXXXX....... 10
SEC2<2> ......................X.XXXXXXXXX....... 10
N_PZ_362 XX......................XXXX.XXX........ 9
N_PZ_303 XX.XXX......XXX..........XXX.XXX........ 14
C_B_BUFR XX..XX.....XXXX...XX.X..XX.XX.XX........ 17
MIN1<2> ....X.X.X.XXX....X..X...XXXXXXXXXXX..... 19
MIN1_0__or0000 ..X.......X.X..X.X.....X.........XX..... 8
MIN1<3> ..X.XX.XXXXXX....X..X...XXXXXXXXXXX..... 22
SEC1<1> ......................X.XXXX....X....... 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 31/9
Number of function block control terms used/remaining: 3/1
Number of PLA product terms used/remaining: 36/20
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
MIN1_cmp_eq0000 1 FB4_1 11 I/O (b)
MIN1_addsub0000<2> 2 FB4_2 12 I/O (b)
N_PZ_292 2 FB4_3 13 I/O (b)
N_PZ_294 3 FB4_4 14 I/O (b)
MIN2_mux0000<2> 3 FB4_5 15 I/O (b)
N_PZ_293 2 FB4_6 16 I/O (b)
N_PZ_488 1 FB4_7 (b) (b)
N_PZ_325 1 FB4_8 (b) (b)
SEC1<2> 3 FB4_9 (b) (b) +
MIN1_3__or0000 3 FB4_10 (b) (b)
MIN2_1_or0000 2 FB4_11 (b) (b)
MIN2_addsub0000<2> 2 FB4_12 17 I/O (b)
MIN2_0_or0000 2 FB4_13 (b) (b)
SEC1<0> 2 FB4_14 18 I/O (b) +
MIN2<1> 5 FB4_15 (b) (b) + +
MIN1<1> 7 FB4_16 (b) (b) + +
Signals Used by Logic in Function Block
1: MIN1<0> 12: MIN2_0_or0000 22: SEC1<1>
2: MIN1<1> 13: MIN2_1_or0000 23: SEC1<2>
3: MIN1<2> 14: MIN2_addsub0000<2> 24: SEC1<3>
4: MIN1<3> 15: MIN2_mux0000<2> 25: SEC2<0>
5: MIN1_1__or0000 16: N_PZ_292 26: SEC2<1>
6: MIN1_addsub0000<3> 17: N_PZ_293 27: SEC2<2>
7: MIN1_cmp_eq0000 18: N_PZ_325 28: SEC2<3>
8: MIN2<0> 19: N_PZ_488 29: clk2
9: MIN2<1> 20: RESET 30: set
10: MIN2<2> 21: SEC1<0> 31: set_min
11: MIN2<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
MIN1_cmp_eq0000 XXXX.................................... 4
MIN1_addsub0000<2>
XXX..................................... 3
N_PZ_292 XX...................................... 2
N_PZ_294 .........XX..X..X....................... 4
MIN2_mux0000<2> .......XXXX............................. 4
N_PZ_293 .......X.X...XX......................... 4
N_PZ_488 ...................X.........X.......... 2
N_PZ_325 .............................XX......... 2
SEC1<2> ..................X.XX......X........... 4
MIN1_3__or0000 .....X..X..X..X....X.........XX......... 7
MIN2_1_or0000 ......X.......X....X.........XX......... 5
MIN2_addsub0000<2>
.......XXX.............................. 3
MIN2_0_or0000 ......XX...........X.........XX......... 5
SEC1<0> ..................X.........X........... 2
MIN2<1> ......XXX...X.X..X..XXXXXXXXXXX......... 17
MIN1<1> .X..X.XXX.....XX.X..XXXXXXXXXXX......... 19
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 21/19
Number of function block control terms used/remaining: 3/1
Number of PLA product terms used/remaining: 10/46
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB5_1 (b)
(unused) 0 FB5_2 33 I/O I
(unused) 0 FB5_3 (b)
(unused) 0 FB5_4 32 GCK/I/O I
(unused) 0 FB5_5 31 I/O
(unused) 0 FB5_6 30 GCK/I/O
(unused) 0 FB5_7 (b)
(unused) 0 FB5_8 (b)
(unused) 0 FB5_9 (b)
(unused) 0 FB5_10 (b)
(unused) 0 FB5_11 (b)
(unused) 0 FB5_12 (b)
MIN2<2> 5 FB5_13 (b) (b) + +
(unused) 0 FB5_14 28 I/O
MIN2<0> 4 FB5_15 (b) (b) + +
MIN1_addsub0000<3> 2 FB5_16 (b) (b)
Signals Used by Logic in Function Block
1: MIN1<2> 8: MIN2_2_or0000 15: SEC2<0>
2: MIN1<3> 9: N_PZ_293 16: SEC2<1>
3: MIN1_addsub0000<2> 10: N_PZ_325 17: SEC2<2>
4: MIN1_cmp_eq0000 11: SEC1<0> 18: SEC2<3>
5: MIN2<0> 12: SEC1<1> 19: clk2
6: MIN2<2> 13: SEC1<2> 20: set
7: MIN2_0_or0000 14: SEC1<3> 21: set_min
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
MIN2<2> ...X.X.XXXXXXXXXXXXXX................... 16
MIN2<0> ...XX.X..XXXXXXXXXXXX................... 15
MIN1_addsub0000<3>
XXX..................................... 3
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB6 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 21/19
Number of function block control terms used/remaining: 3/1
Number of PLA product terms used/remaining: 10/46
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB6_1 34 I/O
(unused) 0 FB6_2 35 CDR/I/O
(unused) 0 FB6_3 (b)
(unused) 0 FB6_4 38 GCK/I/O GCK
(unused) 0 FB6_5 (b)
(unused) 0 FB6_6 (b)
(unused) 0 FB6_7 (b)
(unused) 0 FB6_8 (b)
(unused) 0 FB6_9 (b)
MIN1<0> 6 FB6_10 (b) (b) + +
MIN2<3> 5 FB6_11 (b) (b) + +
(unused) 0 FB6_12 39 DGE/I/O
(unused) 0 FB6_13 40 I/O
(unused) 0 FB6_14 41 I/O
(unused) 0 FB6_15 42 I/O
(unused) 0 FB6_16 43 I/O
Signals Used by Logic in Function Block
1: MIN1<0> 8: MIN2_3_or0000 15: SEC2<0>
2: MIN1_0__or0000 9: N_PZ_294 16: SEC2<1>
3: MIN1_cmp_eq0000 10: N_PZ_325 17: SEC2<2>
4: MIN2<0> 11: SEC1<0> 18: SEC2<3>
5: MIN2<1> 12: SEC1<1> 19: clk2
6: MIN2<2> 13: SEC1<2> 20: set
7: MIN2<3> 14: SEC1<3> 21: set_min
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
MIN1<0> XXXXXXX...XXXXXXXXXXX................... 18
MIN2<3> ..X...XXXXXXXXXXXXXXX................... 16
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB7_1 (b)
(unused) 0 FB7_2 (b)
(unused) 0 FB7_3 (b)
(unused) 0 FB7_4 (b)
(unused) 0 FB7_5 26 I/O
(unused) 0 FB7_6 25 I/O
(unused) 0 FB7_7 (b)
(unused) 0 FB7_8 (b)
(unused) 0 FB7_9 (b)
(unused) 0 FB7_10 (b)
(unused) 0 FB7_11 24 I/O
(unused) 0 FB7_12 23 I/O
(unused) 0 FB7_13 22 I/O
(unused) 0 FB7_14 21 I/O
(unused) 0 FB7_15 20 I/O
(unused) 0 FB7_16 19 I/O
*********************************** FB8 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB8_1 44 I/O
(unused) 0 FB8_2 45 I/O
(unused) 0 FB8_3 46 I/O
(unused) 0 FB8_4 (b)
(unused) 0 FB8_5 48 I/O
(unused) 0 FB8_6 49 I/O
(unused) 0 FB8_7 (b)
(unused) 0 FB8_8 (b)
(unused) 0 FB8_9 (b)
(unused) 0 FB8_10 (b)
(unused) 0 FB8_11 50 I/O
(unused) 0 FB8_12 51 I/O
(unused) 0 FB8_13 52 I/O
(unused) 0 FB8_14 (b)
(unused) 0 FB8_15 (b)
(unused) 0 FB8_16 (b)
*********************************** FB9 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB9_1 112 I/O
(unused) 0 FB9_2 113 I/O
(unused) 0 FB9_3 (b)
(unused) 0 FB9_4 114 I/O
(unused) 0 FB9_5 (b)
(unused) 0 FB9_6 115 I/O
(unused) 0 FB9_7 (b)
(unused) 0 FB9_8 (b)
(unused) 0 FB9_9 (b)
(unused) 0 FB9_10 (b)
(unused) 0 FB9_11 (b)
(unused) 0 FB9_12 116 I/O
(unused) 0 FB9_13 117 I/O
(unused) 0 FB9_14 118 I/O
(unused) 0 FB9_15 119 I/O
(unused) 0 FB9_16 (b)
*********************************** FB10 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB10_1 111 I/O
(unused) 0 FB10_2 110 I/O
(unused) 0 FB10_3 107 I/O
(unused) 0 FB10_4 106 I/O
(unused) 0 FB10_5 105 I/O
(unused) 0 FB10_6 104 I/O
(unused) 0 FB10_7 (b)
(unused) 0 FB10_8 (b)
(unused) 0 FB10_9 (b)
(unused) 0 FB10_10 (b)
(unused) 0 FB10_11 (b)
(unused) 0 FB10_12 103 I/O
(unused) 0 FB10_13 (b)
(unused) 0 FB10_14 102 I/O
(unused) 0 FB10_15 (b)
(unused) 0 FB10_16 101 I/O
*********************************** FB11 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 2/38
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 4/52
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB11_1 (b)
(unused) 0 FB11_2 (b)
(unused) 0 FB11_3 (b)
(unused) 0 FB11_4 (b)
(unused) 0 FB11_5 120 I/O
(unused) 0 FB11_6 121 I/O
(unused) 0 FB11_7 (b)
(unused) 0 FB11_8 (b)
(unused) 0 FB11_9 (b)
(unused) 0 FB11_10 (b)
(unused) 0 FB11_11 124 I/O
(unused) 0 FB11_12 125 I/O
AN4 1 FB11_13 126 I/O O
AN3 1 FB11_14 128 I/O O
AN2 1 FB11_15 129 I/O O
AN1 1 FB11_16 130 I/O O
Signals Used by Logic in Function Block
1: COUNTER<0> 2: COUNTER<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
AN4 XX...................................... 2
AN3 XX...................................... 2
AN2 XX...................................... 2
AN1 XX...................................... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB12 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB12_1 (b)
(unused) 0 FB12_2 100 I/O
(unused) 0 FB12_3 (b)
(unused) 0 FB12_4 (b)
(unused) 0 FB12_5 (b)
(unused) 0 FB12_6 (b)
(unused) 0 FB12_7 (b)
(unused) 0 FB12_8 (b)
(unused) 0 FB12_9 (b)
(unused) 0 FB12_10 (b)
(unused) 0 FB12_11 98 I/O
(unused) 0 FB12_12 97 I/O
(unused) 0 FB12_13 96 I/O
(unused) 0 FB12_14 95 I/O
(unused) 0 FB12_15 94 I/O
(unused) 0 FB12_16 (b)
*********************************** FB13 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB13_1 75 I/O
(unused) 0 FB13_2 76 I/O
(unused) 0 FB13_3 77 I/O
(unused) 0 FB13_4 (b)
(unused) 0 FB13_5 78 I/O
(unused) 0 FB13_6 79 I/O
(unused) 0 FB13_7 (b)
(unused) 0 FB13_8 (b)
(unused) 0 FB13_9 (b)
(unused) 0 FB13_10 (b)
(unused) 0 FB13_11 (b)
(unused) 0 FB13_12 80 I/O
(unused) 0 FB13_13 81 I/O
(unused) 0 FB13_14 82 I/O
(unused) 0 FB13_15 (b)
(unused) 0 FB13_16 (b)
*********************************** FB14 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 20/20
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 10/46
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB14_1 74 I/O
(unused) 0 FB14_2 71 I/O
(unused) 0 FB14_3 70 I/O
LD0 1 FB14_4 69 I/O O
(unused) 0 FB14_5 (b)
(unused) 0 FB14_6 68 I/O
(unused) 0 FB14_7 (b)
(unused) 0 FB14_8 (b)
(unused) 0 FB14_9 (b)
(unused) 0 FB14_10 (b)
(unused) 0 FB14_11 (b)
(unused) 0 FB14_12 (b)
(unused) 0 FB14_13 66 I/O
(unused) 0 FB14_14 64 I/O
(unused) 0 FB14_15 (b)
C_G 9 FB14_16 61 I/O O
Signals Used by Logic in Function Block
1: COUNTER<0> 8: MIN2<2> 15: SEC1<3>
2: COUNTER<1> 9: MIN2<3> 16: SEC2<0>
3: MIN1<1> 10: MIN2_addsub0000<2> 17: SEC2<1>
4: MIN1<2> 11: N_PZ_303 18: SEC2<2>
5: MIN1<3> 12: N_PZ_362 19: SEC2<3>
6: MIN1_addsub0000<3> 13: SEC1<1> 20: clk2
7: MIN2<1> 14: SEC1<2>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
LD0 ...................X.................... 1
C_G XXXXXXXXXXXXXXXXXXX..................... 19
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB15 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB15_1 (b)
(unused) 0 FB15_2 83 I/O
(unused) 0 FB15_3 (b)
(unused) 0 FB15_4 (b)
(unused) 0 FB15_5 (b)
(unused) 0 FB15_6 (b)
(unused) 0 FB15_7 (b)
(unused) 0 FB15_8 (b)
(unused) 0 FB15_9 (b)
(unused) 0 FB15_10 (b)
(unused) 0 FB15_11 85 I/O
(unused) 0 FB15_12 86 I/O
(unused) 0 FB15_13 87 I/O
(unused) 0 FB15_14 88 I/O
(unused) 0 FB15_15 91 I/O
(unused) 0 FB15_16 92 I/O
*********************************** FB16 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 25/15
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 48/8
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB16_1 (b)
(unused) 0 FB16_2 (b)
(unused) 0 FB16_3 (b)
(unused) 0 FB16_4 (b)
C_C 12 FB16_5 60 I/O O
(unused) 0 FB16_6 59 I/O
(unused) 0 FB16_7 (b)
(unused) 0 FB16_8 (b)
(unused) 0 FB16_9 (b)
(unused) 0 FB16_10 (b)
C_D 14 FB16_11 58 I/O O
C_E 8 FB16_12 57 I/O O
C_A 13 FB16_13 56 I/O O
(unused) 0 FB16_14 (b)
C_F 9 FB16_15 54 I/O O
C_B 1 FB16_16 53 I/O O
Signals Used by Logic in Function Block
1: COUNTER<0> 10: MIN2<0> 18: SEC1<0>
2: COUNTER<1> 11: MIN2<1> 19: SEC1<1>
3: C_B_BUFR 12: MIN2<2> 20: SEC1<2>
4: MIN1<0> 13: MIN2<3> 21: SEC1<3>
5: MIN1<1> 14: MIN2_addsub0000<2> 22: SEC2<0>
6: MIN1<2> 15: N_PZ_292 23: SEC2<1>
7: MIN1<3> 16: N_PZ_303 24: SEC2<2>
8: MIN1_addsub0000<2> 17: N_PZ_362 25: SEC2<3>
9: MIN1_addsub0000<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
C_C XX.XXXX..XXXX....XXXXXXXX............... 18
C_D XX.XXXXXXXXXXXXXXXXXXXXXX............... 24
C_E XX.XXXX..XXXX....XXXXXXXX............... 18
C_A XX.XXXX.XXXXX..X.XXXXXXXX............... 20
C_F XX...XXX.XXXXXXXXXXX.XXXX............... 20
C_B ..X..................................... 1
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
AN1 <= NOT ((COUNTER(0) AND COUNTER(1)));
AN2 <= NOT ((NOT COUNTER(0) AND COUNTER(1)));
AN3 <= NOT ((COUNTER(0) AND NOT COUNTER(1)));
AN4 <= NOT ((NOT COUNTER(0) AND NOT COUNTER(1)));
FDCPE_CLK_COUNTER0: FDCPE port map (CLK_COUNTER(0),CLK_COUNTER_D(0),CLK,'0','0','1');
CLK_COUNTER_D(0) <= (N_PZ_342 AND NOT CLK_COUNTER(0));
FDCPE_CLK_COUNTER1: FDCPE port map (CLK_COUNTER(1),CLK_COUNTER_D(1),CLK,'0','0','1');
CLK_COUNTER_D(1) <= ((N_PZ_342 AND CLK_COUNTER(0) AND NOT CLK_COUNTER(1))
OR (N_PZ_342 AND NOT CLK_COUNTER(0) AND CLK_COUNTER(1)));
FDCPE_CLK_COUNTER2: FDCPE port map (CLK_COUNTER(2),CLK_COUNTER_D(2),CLK,'0','0','1');
CLK_COUNTER_D(2) <= ((N_PZ_342 AND NOT N_PZ_378 AND CLK_COUNTER(2))
OR (N_PZ_342 AND NOT N_PZ_378 AND CLK_COUNTER(0) AND
CLK_COUNTER(1)));
FDCPE_CLK_COUNTER3: FDCPE port map (CLK_COUNTER(3),CLK_COUNTER_D(3),CLK,'0','0','1');
CLK_COUNTER_D(3) <= ((N_PZ_342 AND CLK_COUNTER(3) AND NOT N_PZ_378)
OR (N_PZ_342 AND NOT CLK_COUNTER(3) AND N_PZ_378));
FTCPE_CLK_COUNTER4: FTCPE port map (CLK_COUNTER(4),CLK_COUNTER_T(4),CLK,'0','0','1');
CLK_COUNTER_T(4) <= ((NOT N_PZ_342 AND CLK_COUNTER(4))
OR (N_PZ_342 AND CLK_COUNTER(3) AND N_PZ_378));
FDCPE_CLK_COUNTER5: FDCPE port map (CLK_COUNTER(5),CLK_COUNTER_D(5),CLK,'0','0','1');
CLK_COUNTER_D(5) <= ((N_PZ_342 AND NOT N_PZ_374 AND CLK_COUNTER(5))
OR (N_PZ_342 AND NOT N_PZ_374 AND CLK_COUNTER(3) AND N_PZ_378 AND
CLK_COUNTER(4)));
FDCPE_CLK_COUNTER6: FDCPE port map (CLK_COUNTER(6),CLK_COUNTER_D(6),CLK,'0','0','1');
CLK_COUNTER_D(6) <= ((N_PZ_342 AND CLK_COUNTER(6) AND NOT N_PZ_374)
OR (N_PZ_342 AND NOT CLK_COUNTER(6) AND N_PZ_374));
FDCPE_CLK_COUNTER7: FDCPE port map (CLK_COUNTER(7),CLK_COUNTER_D(7),CLK,'0','0','1');
CLK_COUNTER_D(7) <= ((N_PZ_342 AND NOT N_PZ_344 AND CLK_COUNTER(7))
OR (N_PZ_342 AND NOT N_PZ_344 AND CLK_COUNTER(6) AND N_PZ_374));
FDCPE_CLK_COUNTER8: FDCPE port map (CLK_COUNTER(8),CLK_COUNTER_D(8),CLK,'0','0','1');
CLK_COUNTER_D(8) <= ((N_PZ_342 AND CLK_COUNTER(8) AND NOT N_PZ_344)
OR (N_PZ_342 AND NOT CLK_COUNTER(8) AND N_PZ_344));
FTCPE_CLK_COUNTER9: FTCPE port map (CLK_COUNTER(9),CLK_COUNTER_T(9),CLK,'0','0','1');
CLK_COUNTER_T(9) <= ((NOT N_PZ_342 AND CLK_COUNTER(9))
OR (N_PZ_342 AND CLK_COUNTER(8) AND N_PZ_344));
FTCPE_CLK_COUNTER10: FTCPE port map (CLK_COUNTER(10),CLK_COUNTER_T(10),CLK,'0','0','1');
CLK_COUNTER_T(10) <= ((NOT N_PZ_342 AND CLK_COUNTER(10))
OR (NOT CLK_COUNTER(13) AND NOT CLK_COUNTER(14) AND
NOT CLK_COUNTER(15) AND NOT CLK_COUNTER(16) AND NOT CLK_COUNTER(17) AND
NOT CLK_COUNTER(18) AND NOT CLK_COUNTER(19) AND NOT CLK_COUNTER(20) AND
NOT CLK_COUNTER(21) AND NOT CLK_COUNTER(22) AND NOT CLK_COUNTER(23) AND
NOT CLK_COUNTER(24) AND CLK_COUNTER(8) AND N_PZ_344 AND CLK_COUNTER(9) AND
NOT CLK_COUNTER(25)));
FDCPE_CLK_COUNTER11: FDCPE port map (CLK_COUNTER(11),CLK_COUNTER_D(11),CLK,'0','0','1');
CLK_COUNTER_D(11) <= ((NOT CLK_COUNTER(10) AND NOT CLK_COUNTER(13) AND
NOT CLK_COUNTER(14) AND NOT CLK_COUNTER(15) AND NOT CLK_COUNTER(16) AND
NOT CLK_COUNTER(17) AND NOT CLK_COUNTER(18) AND NOT CLK_COUNTER(19) AND
NOT CLK_COUNTER(20) AND NOT CLK_COUNTER(21) AND NOT CLK_COUNTER(22) AND
NOT CLK_COUNTER(23) AND NOT CLK_COUNTER(24) AND NOT CLK_COUNTER(25) AND
CLK_COUNTER(11))
OR (NOT CLK_COUNTER(13) AND NOT CLK_COUNTER(14) AND
NOT CLK_COUNTER(15) AND NOT CLK_COUNTER(16) AND NOT CLK_COUNTER(17) AND
NOT CLK_COUNTER(18) AND NOT CLK_COUNTER(19) AND NOT CLK_COUNTER(20) AND
NOT CLK_COUNTER(21) AND NOT CLK_COUNTER(22) AND NOT CLK_COUNTER(23) AND
NOT CLK_COUNTER(24) AND NOT CLK_COUNTER(8) AND NOT CLK_COUNTER(25) AND
CLK_COUNTER(11))
OR (NOT CLK_COUNTER(13) AND NOT CLK_COUNTER(14) AND
NOT CLK_COUNTER(15) AND NOT CLK_COUNTER(16) AND NOT CLK_COUNTER(17) AND
NOT CLK_COUNTER(18) AND NOT CLK_COUNTER(19) AND NOT CLK_COUNTER(20) AND
NOT CLK_COUNTER(21) AND NOT CLK_COUNTER(22) AND NOT CLK_COUNTER(23) AND
NOT CLK_COUNTER(24) AND NOT CLK_COUNTER(9) AND NOT CLK_COUNTER(25) AND
CLK_COUNTER(11))
OR (NOT CLK_COUNTER(13) AND NOT CLK_COUNTER(14) AND
NOT CLK_COUNTER(15) AND NOT CLK_COUNTER(16) AND NOT CLK_COUNTER(17) AND
NOT CLK_COUNTER(18) AND NOT CLK_COUNTER(19) AND NOT CLK_COUNTER(20) AND
NOT CLK_COUNTER(21) AND NOT CLK_COUNTER(22) AND NOT CLK_COUNTER(23) AND
NOT CLK_COUNTER(24) AND NOT N_PZ_344 AND NOT CLK_COUNTER(25) AND CLK_COUNTER(11) AND
NOT CLK_COUNTER(12))
OR (NOT CLK_COUNTER(13) AND NOT CLK_COUNTER(14) AND
NOT CLK_COUNTER(15) AND NOT CLK_COUNTER(16) AND NOT CLK_COUNTER(17) AND
NOT CLK_COUNTER(18) AND NOT CLK_COUNTER(19) AND NOT CLK_COUNTER(20) AND
NOT CLK_COUNTER(21) AND NOT CLK_COUNTER(22) AND NOT CLK_COUNTER(23) AND
NOT CLK_COUNTER(24) AND NOT CLK_COUNTER(6) AND NOT CLK_COUNTER(7) AND
NOT CLK_COUNTER(25) AND CLK_COUNTER(11))
OR (CLK_COUNTER(10) AND NOT CLK_COUNTER(13) AND
NOT CLK_COUNTER(14) AND NOT CLK_COUNTER(15) AND NOT CLK_COUNTER(16) AND
NOT CLK_COUNTER(17) AND NOT CLK_COUNTER(18) AND NOT CLK_COUNTER(19) AND
NOT CLK_COUNTER(20) AND NOT CLK_COUNTER(21) AND NOT CLK_COUNTER(22) AND
NOT CLK_COUNTER(23) AND NOT CLK_COUNTER(24) AND CLK_COUNTER(8) AND N_PZ_344 AND
CLK_COUNTER(9) AND NOT CLK_COUNTER(25) AND NOT CLK_COUNTER(11)));
FDCPE_CLK_COUNTER12: FDCPE port map (CLK_COUNTER(12),CLK_COUNTER_D(12),CLK,'0','0','1');
CLK_COUNTER_D(12) <= ((N_PZ_342 AND CLK_COUNTER(12))
OR (N_PZ_342 AND CLK_COUNTER(10) AND CLK_COUNTER(8) AND
N_PZ_344 AND CLK_COUNTER(9) AND CLK_COUNTER(11)));
FDCPE_CLK_COUNTER13: FDCPE port map (CLK_COUNTER(13),'0',CLK,'0','0','1');
FDCPE_CLK_COUNTER14: FDCPE port map (CLK_COUNTER(14),'0',CLK,'0','0','1');
FDCPE_CLK_COUNTER15: FDCPE port map (CLK_COUNTER(15),'0',CLK,'0','0','1');
FDCPE_CLK_COUNTER16: FDCPE port map (CLK_COUNTER(16),'0',CLK,'0','0','1');
FDCPE_CLK_COUNTER17: FDCPE port map (CLK_COUNTER(17),'0',CLK,'0','0','1');
FDCPE_CLK_COUNTER18: FDCPE port map (CLK_COUNTER(18),'0',CLK,'0','0','1');
FDCPE_CLK_COUNTER19: FDCPE port map (CLK_COUNTER(19),'0',CLK,'0','0','1');
FDCPE_CLK_COUNTER20: FDCPE port map (CLK_COUNTER(20),'0',CLK,'0','0','1');
FDCPE_CLK_COUNTER21: FDCPE port map (CLK_COUNTER(21),'0',CLK,'0','0','1');
FDCPE_CLK_COUNTER22: FDCPE port map (CLK_COUNTER(22),'0',CLK,'0','0','1');
FDCPE_CLK_COUNTER23: FDCPE port map (CLK_COUNTER(23),'0',CLK,'0','0','1');
FDCPE_CLK_COUNTER24: FDCPE port map (CLK_COUNTER(24),'0',CLK,'0','0','1');
FDCPE_CLK_COUNTER25: FDCPE port map (CLK_COUNTER(25),'0',CLK,'0','0','1');
FTCPE_COUNTER0: FTCPE port map (COUNTER(0),N_PZ_342,CLK,'0','0','1');
FTCPE_COUNTER1: FTCPE port map (COUNTER(1),COUNTER_T(1),CLK,'0','0','1');
COUNTER_T(1) <= (COUNTER(0) AND NOT N_PZ_342);
C_A <= NOT (((N_PZ_303)
OR (COUNTER(0) AND COUNTER(1) AND MIN2(1) AND NOT MIN2(3))
OR (COUNTER(0) AND NOT COUNTER(1) AND SEC2(1) AND NOT SEC2(3))
OR (NOT COUNTER(0) AND NOT COUNTER(1) AND SEC1(1) AND NOT SEC1(3))
OR (COUNTER(0) AND COUNTER(1) AND MIN2(0) AND MIN2(2) AND
NOT MIN2(3))
OR (COUNTER(0) AND COUNTER(1) AND NOT MIN2(0) AND NOT MIN2(2) AND
NOT MIN2(3))
OR (COUNTER(0) AND NOT COUNTER(1) AND SEC2(0) AND SEC2(2) AND
NOT SEC2(3))
OR (COUNTER(0) AND NOT COUNTER(1) AND NOT SEC2(0) AND NOT SEC2(2) AND
NOT SEC2(3))
OR (NOT COUNTER(0) AND COUNTER(1) AND MIN1(0) AND MIN1(2) AND
NOT MIN1(3))
OR (NOT COUNTER(0) AND COUNTER(1) AND NOT MIN1(0) AND NOT MIN1(2) AND
NOT MIN1(3))
OR (NOT COUNTER(0) AND COUNTER(1) AND MIN1(1) AND NOT MIN1(3) AND
NOT MIN1_addsub0000(3))
OR (NOT COUNTER(0) AND NOT COUNTER(1) AND SEC1(0) AND SEC1(2) AND
NOT SEC1(3))
OR (NOT COUNTER(0) AND NOT COUNTER(1) AND NOT SEC1(0) AND NOT SEC1(2) AND
NOT SEC1(3))));
C_B_BUFR <= NOT (((N_PZ_303)
OR (COUNTER(0) AND NOT SEC2(0) AND N_PZ_362)
OR (COUNTER(0) AND COUNTER(1) AND NOT MIN2(2) AND NOT MIN2(3))
OR (COUNTER(0) AND NOT COUNTER(1) AND NOT SEC2(2) AND NOT SEC2(3))
OR (NOT COUNTER(0) AND COUNTER(1) AND NOT N_PZ_292 AND NOT MIN1(3))
OR (NOT COUNTER(0) AND COUNTER(1) AND NOT MIN1(2) AND NOT MIN1(3))
OR (NOT COUNTER(0) AND NOT COUNTER(1) AND NOT SEC1(3) AND NOT N_PZ_362)
OR (NOT COUNTER(0) AND NOT SEC1(0) AND NOT SEC1(1) AND N_PZ_362)
OR (COUNTER(0) AND COUNTER(1) AND MIN2(1) AND MIN2(0) AND
NOT MIN2(3))
OR (COUNTER(0) AND COUNTER(1) AND NOT MIN2(1) AND NOT MIN2(0) AND
NOT MIN2(3))
OR (COUNTER(0) AND NOT COUNTER(1) AND SEC2(0) AND NOT SEC2(3) AND
NOT N_PZ_362)));
C_B <= C_B_BUFR;
C_C <= NOT (((COUNTER(0) AND COUNTER(1) AND NOT MIN2(1) AND NOT MIN2(2))
OR (COUNTER(0) AND COUNTER(1) AND MIN2(0) AND NOT MIN2(3))
OR (COUNTER(0) AND COUNTER(1) AND MIN2(2) AND NOT MIN2(3))
OR (COUNTER(0) AND NOT COUNTER(1) AND SEC2(0) AND NOT SEC2(3))
OR (COUNTER(0) AND NOT COUNTER(1) AND NOT SEC2(1) AND NOT SEC2(2))
OR (COUNTER(0) AND NOT COUNTER(1) AND SEC2(2) AND NOT SEC2(3))
OR (NOT COUNTER(0) AND COUNTER(1) AND MIN1(0) AND NOT MIN1(3))
OR (NOT COUNTER(0) AND COUNTER(1) AND NOT MIN1(1) AND NOT MIN1(2))
OR (NOT COUNTER(0) AND COUNTER(1) AND MIN1(2) AND NOT MIN1(3))
OR (NOT COUNTER(0) AND NOT COUNTER(1) AND SEC1(0) AND NOT SEC1(3))
OR (NOT COUNTER(0) AND NOT COUNTER(1) AND NOT SEC1(1) AND NOT SEC1(2))
OR (NOT COUNTER(0) AND NOT COUNTER(1) AND SEC1(2) AND NOT SEC1(3))));
C_D <= NOT (((N_PZ_303)
OR (COUNTER(0) AND SEC2(0) AND N_PZ_362)
OR (NOT COUNTER(0) AND SEC1(0) AND N_PZ_362)
OR (NOT COUNTER(0) AND SEC1(1) AND N_PZ_362)
OR (COUNTER(0) AND COUNTER(1) AND MIN2(1) AND NOT MIN2(0) AND
NOT MIN2(3))
OR (COUNTER(0) AND COUNTER(1) AND MIN2(0) AND
MIN2_addsub0000(2) AND NOT MIN2(3))
OR (COUNTER(0) AND COUNTER(1) AND NOT MIN2(0) AND NOT MIN2(2) AND
NOT MIN2(3))
OR (COUNTER(0) AND NOT COUNTER(1) AND NOT SEC2(0) AND NOT SEC2(3) AND
NOT N_PZ_362)
OR (COUNTER(0) AND NOT COUNTER(1) AND SEC2(1) AND NOT SEC2(2) AND
NOT SEC2(3))