Backup 1.txt

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-- Company: LeTourneau University
-- Engineer: 
-- 
-- Create Date:    19:46:40 04/11/2021 
-- Design Name: 
-- Module Name:    FinalDisplay - Behavioral 
-- Project Name: Digital Electronics Clock Display
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FinalDisplay is
    Port ( --SEC_0 : in  STD_LOGIC_VECTOR(3 downto 0);
				
				-- clock signal
				CLK : in STD_LOGIC;
				
				-- 4 digits on board				
				AN1 : out  STD_LOGIC;
				AN2 : out  STD_LOGIC;
				AN3 : out  STD_LOGIC;
				AN4 : out  STD_LOGIC;
	 
				-- 7 outputs for 7 segment display
           C_A : out  STD_LOGIC;
           C_B : out  STD_LOGIC;
           C_C : out  STD_LOGIC;
           C_D : out  STD_LOGIC;
           C_E : out  STD_LOGIC;
           C_F : out  STD_LOGIC;
           C_G : out  STD_LOGIC);
end FinalDisplay;


architecture Behavioral of FinalDisplay is

	-- clock counter
	signal CLK_DIV : STD_LOGIC_VECTOR (23 downto 0);
	
	-- clock counter divided by 2^15, 244 Hz
	signal CLOCK : STD_LOGIC;
	
	-- BCD of digits
	--signal MIN_2 : STD_LOGIC_VECTOR(3 downto 0);
	--signal MIN_1 : STD_LOGIC_VECTOR(3 downto 0);
	--signal SEC_2 : STD_LOGIC_VECTOR(3 downto 0);
	signal SEC_1 : STD_LOGIC_VECTOR(3 downto 0);
	
	-- representation of 7 segment display output
	signal SEC_1_DISPLAY : STD_LOGIC_VECTOR(6 downto 0);
	
	-- 2 bits for counter, default should be 00
	signal COUNTER : STD_LOGIC_VECTOR(1 downto 0);
	
	-- which digit is being displayed
	signal AN : STD_LOGIC_VECTOR(3 downto 0);

begin

	-- set digits to 4321
	--MIN_2 <= "0100"; -- 4
	--MIN_1 <= "0011"; -- 3
	--SEC_2 <= "0010"; -- 2
	SEC_1 <= "0001"; -- 1
	
	15-- process to set up a clock divider and allow use of divided clock
	Clock_Divider : process (CLK)
		begin
			-- set up a new clock that is incremented based on the built in clock of 8 MHz
			
			-- if clock changes to 1, add 1 to CLK_DIV
			if (CLK'Event and CLK = '1') then
				CLK_DIV <= std_logic_vector(to_unsigned(to_integer(unsigned(CLK_DIV)) + 1, 4));
			end if;
		end process;
	
	-- the 16th digit divides the frequency of the 8 MHz clock by 2^15 so that it has a frequency of 244 Hz, so the period as 4 ms
	-- (it works this way becuase of how it is set up to increment CLK_DIV)
	Clock <= CLK_DIV(15);
	
	
	Multiplexed_Display : process (Clock)
		begin
			-- depending on counter, select which digit is on
			case COUNTER is
				when "00" =>
					AN <= "0111";
				when "01" =>
					AN <= "1011";
				when "10" =>
					AN <= "1101";
				when "11" =>
					AN <= "1110";
				when others =>
					AN <= "1111"; -- default all off
			end case;
						
			-- reset counter if 3, otherwise increment
			if (COUNTER = "11") then
				COUNTER <= "00";
			else
				COUNTER <= std_logic_vector(to_unsigned(to_integer(unsigned(COUNTER)) + 1, 4));
			end if;
			
			-- turn digits on
			AN1 <= AN(3);
			AN2 <= AN(2);
			AN3 <= AN(1);
			AN4 <= AN(0);
				
			-- map BCD input to desired output segments
			case SEC_1 is
				when  =>
					SEC_1_DISPLAY <= "0000001"; -- 0
				when "0001" =>
					SEC_1_DISPLAY <= "1001111"; -- 1
				when "0010" =>
					SEC_1_DISPLAY <= "0010010"; -- 2
				when "0011" =>
					SEC_1_DISPLAY <= "0000110"; -- 3
				when "0100" =>
					SEC_1_DISPLAY <= "1001100"; -- 4
				when "0101" =>
					SEC_1_DISPLAY <= "0100100"; -- 5
				when "0110" =>
					SEC_1_DISPLAY <= "0100000"; -- 6
				when "0111" =>
					SEC_1_DISPLAY <= "0001111"; -- 7
				when "1000" =>
					SEC_1_DISPLAY <= "0000000"; -- 8
				when "1001" =>
					SEC_1_DISPLAY <= "0000100"; -- 9
				when others =>
					SEC_1_DISPLAY <= "1111111"; -- blank when not a digit
			end case;
			
			C_A <= SEC_1_DISPLAY(6);
			C_B <= SEC_1_DISPLAY(5);
			C_C <= SEC_1_DISPLAY(4);
			C_D <= SEC_1_DISPLAY(3);
			C_E <= SEC_1_DISPLAY(2);
			C_F <= SEC_1_DISPLAY(1);
			C_G <= SEC_1_DISPLAY(0);
		end process;
	
end Behavioral;