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pyverilator finds internal signals by parsing VL_SIG* lines in an .h file generated by verilator. The most recent version of verilator looks like it doesn't use the VL_SIG* macros anymore. Instead it, for an 8-bit signal, it produces a line like the one below:
CData/*7:0*/ parent_module__DOT__in_reg;
pyverilator should also look for this format as well.
The text was updated successfully, but these errors were encountered:
It looks like this is the Verilator commit that introduced this bug: verilator/verilator@21a380d
Until pyverilator is updated to support this new format, you can revert to Verilator v4.020 or earlier to get rid of this problem.
pyverilator finds internal signals by parsing
VL_SIG*
lines in an.h
file generated by verilator. The most recent version of verilator looks like it doesn't use theVL_SIG*
macros anymore. Instead it, for an 8-bit signal, it produces a line like the one below:pyverilator should also look for this format as well.
The text was updated successfully, but these errors were encountered: