Hi, I'm currently an Imperial College London PhD student in the Circuits and Systems Group, under the supervision of Professor George Constantinides. My research looks at all aspects of numerical hardware design and how we can create fast but verified hardware. My main project looks at novel techniques to optimise RTL level circuit designs, with side projects investigating bitvector transformation correctness and tight arithmetic expression bounds.

Publications

DAC 23 - Automating Constraint-Aware Datapath Optimization using E-Graphs

ASP-DAC 23 - Automatic Generation of Complete Polynomial Interpolation Design Space for Hardware Architectures

ARITH 22 - Automatic Design Space Exploration for an Error Tolerant Application

FMCAD 22 - Small Proofs from Congruence Closure

EGRAPHS 22 - Abstract Interpretation on E-Graphs - co-located with PLDI 22

In Press - Formal Verification of Transcendental Fixed and Floating Point Algorithms using an Automatic Theorem Prover

Roles

EGRAPHS 2023 Program Committee Member

News

2022-05-05 - Presenting my latest research on RTL Optimisation using E-Graphs to the FPBench Community