diff --git a/xthead.adoc b/xthead.adoc
index 31de2de..0ee2ec8 100644
--- a/xthead.adoc
+++ b/xthead.adoc
@@ -50,4 +50,4 @@ include::xtheadint.adoc[]
 include::xtheadvdot.adoc[]
 include::xtheadvector.adoc[]
 
-include::xtheadmaee.adoc[]
+include::xtheadmae.adoc[]
diff --git a/xtheadmae.adoc b/xtheadmae.adoc
new file mode 100644
index 0000000..c33082f
--- /dev/null
+++ b/xtheadmae.adoc
@@ -0,0 +1,47 @@
+[#xtheadmae]
+== Memory Attribute Extension (XTheadMae)
+
+[NOTE,caption=Frozen]
+The `XTheadMae` extension is `stable`.
+
+Extension version: 1.0.
+
+The `XTheadMae` ISA extension provides a way to configure memory page attributes.
+These attributes are set in the page tabale entries (PTEs).
+
+The `XTheadMae` extension is a non-standard non-conforming extension.
+`XTheadMae` uses preserved [60:63] bits of the PTE, which have later been
+allocted to the `Svpbmt` and `Svnapot` standard extensions.
+This conflict is not on purpose, but the result of issues in the past that have been resolved since.
+Therefore, the `XTheadMae` extension and the `Svpbmt` or `Svnapot` are in conflict.
+In other words, tools should not allow to enable the `XTheadMae` extension and
+the `Svpbmt` or `Svnapot` extensions at the same time and should report an error
+if both are enabled by the user.
+
+The table below describes the page attributes corresponding to each memory type:
+
+[cols="^12,3,3,3",stripes=even,options="header"]
+|===
+| Memory type            | SO | C | B
+| Cacheable memory       | 0  | 1 | 1
+| Non-cacheable memory   | 0  | 0 | 1
+| Bufferable device      | 1  | 0 | 1
+| Non-bufferable device  | 1  | 0 | 0
+|===
+
+The table below describes extend page attributes in PTE:
+[cols="^3,^3,12",stripes=even,options="header"]
+|===
+| Fields  | Bit | Meaning
+| SO      | 63  | Strong order
+| C       | 62  | Cacheable
+| B       | 61  | Bufferable
+| T       | 60  | Trustable
+|===
+
+=== Availability
+
+The `XTheadMae` extension's availability can be probed via the
+`th.sxstatus`.MAEE bit (bit 21).
+The `XTheadMae` extension is available if and only if this bit is `1`.
+Refer to <<#xtheadsxstatus>> for more information about the `th.sxstatus` CSR.
diff --git a/xtheadmaee.adoc b/xtheadmaee.adoc
deleted file mode 100644
index c1dca3f..0000000
--- a/xtheadmaee.adoc
+++ /dev/null
@@ -1,39 +0,0 @@
-[#xtheadmaee]
-== Extend MMU address attribute (XTheadMaee)
-
-[NOTE,caption=Frozen]
-The `XTheadMaee` extension is `stable`.
-
-Extension version: 1.0.
-
-The `XTheadMaee` ISA extension provides a way to configure page attributes of addresses when virtual addresses are translated into physical addresses by extended page attributes in page table entries (PTEs).
-
-The `XTheadMaee` extension is a non-standard non-conforming extension. TheadMaee uses preserved [60:63] bits of PTE, which have been allocted to SVPBMT and SVNAPOT. This conflict is not on purpose, but the result of issues in the past that have been resolved since. Therefore, the XTheadMaee extension and the SVPBMT or SVNAPOT extension are in conflict. In other words, tools should not allow to enable the TheadMaee extension and the SVPBMT or SVNAPOT at the same time and should report an error if both are enabled by the user.
-
-The table below describes the page attributes corresponding to each memory type:
-
-[cols="^12,3,3,3",stripes=even,options="header"]
-|===
-| Memory type            | SO | C | B
-| Cacheable memory       | 0  | 1 | 1
-| Non-cacheable memory   | 0  | 0 | 1
-| Bufferable device      | 1  | 0 | 1
-| Non-bufferable device  | 1  | 0 | 0
-|===
-
-The table below describes extend page attributes in PTE:
-[cols="^3,^3,12",stripes=even,options="header"]
-|===
-| Fields  | Bit | Meaning
-| SO      | 63  | Strong order
-| C       | 62  | Cacheable
-| B       | 61  | Bufferable
-| T       | 60  | Trustable
-|===
-
-=== Availability
-
-The `XTheadMaee` extension's availability can be probed via the
-`th.sxstatus`.MAEE bit (bit 21).
-The `XTheadMaee` extension is available if and only if this bit is `1`.
-Refer to <<#xtheadsxstatus>> for more information about the `th.sxstatus` CSR.