From 01ec8a6b7b31897a4975ccb6474cd830e1b46a9c Mon Sep 17 00:00:00 2001 From: hansemandse Date: Sat, 5 Dec 2020 17:51:49 +0100 Subject: [PATCH] add default values --- axi4/src/main/scala/axi4/Bundles.scala | 69 ++++++++++++++++++- .../main/scala/axi4/FunctionalMaster.scala | 35 ++-------- 2 files changed, 74 insertions(+), 30 deletions(-) diff --git a/axi4/src/main/scala/axi4/Bundles.scala b/axi4/src/main/scala/axi4/Bundles.scala index 0dcec64..cbf1fe6 100644 --- a/axi4/src/main/scala/axi4/Bundles.scala +++ b/axi4/src/main/scala/axi4/Bundles.scala @@ -10,6 +10,7 @@ package axi4 import chisel3._ import chisel3.util.isPow2 +import chisel3.experimental.BundleLiterals._ /** AXI4 write address * @@ -39,9 +40,24 @@ object WA { * @param addrW the width of the AWADDR signal in bits * @param idW the width of the AWID signal in bits, defaults to 0 * @param userW the width of the AWUSER signal in bits, defaults to 0 - * @return + * @return an unitialized WA object */ def apply(addrW: Int, idW: Int = 0, userW: Int = 0) = new WA(addrW, idW, userW) + + /** Default values for this channel + * + * @param in a WA object + * @return an initialized (hardware) WA object + */ + def default(in: WA) = { + var defLits = Seq((x: WA) => x.addr -> 0.U, (x: WA) => x.len -> 0.U, (x: WA) => x.size -> 0.U, + (x: WA) => x.burst -> BurstEncodings.Fixed, (x: WA) => x.lock -> LockEncodings.NormalAccess, + (x: WA) => x.cache -> MemoryEncodings.DeviceNonbuf, (x: WA) => x.prot -> ProtectionEncodings.DataNsecUpriv, + (x: WA) => x.qos -> 0.U, (x: WA) => x.region -> 0.U) + if (in.idW > 0) defLits = defLits :+ ((x: WA) => x.id -> 0.U) + if (in.userW > 0) defLits = defLits :+ ((x: WA) => x.user -> 0.U) + (new WA(in.addrW, in.idW, in.userW)).Lit(defLits :_*) + } } /** AXI4 write data @@ -66,6 +82,17 @@ object WD { * @return an unitialized WD object */ def apply(dataW: Int, userW: Int = 0) = new WD(dataW, userW) + + /** Default values for this channel + * + * @param in a WD object + * @return an initialized (hardware) WD object + */ + def default(in: WD) = { + var defLits = Seq((x: WD) => x.data -> 0.U, (x: WD) => x.strb -> 0.U, (x: WD) => x.last -> false.B) + if (in.userW > 0) defLits = defLits :+ ((x: WD) => x.user -> 0.U) + (new WD(in.dataW, in.userW)).Lit(defLits :_*) + } } /** AXI4 write response @@ -88,6 +115,18 @@ object WR { * @return an unitialized WR object */ def apply(idW: Int = 0, userW: Int = 0) = new WR(idW, userW) + + /** Default values for this channel + * + * @param in a WR object + * @return an initialized (hardware) WR object + */ + def default(in: WR) = { + var defLits = Seq((x: WR) => x.resp -> ResponseEncodings.Okay) + if (in.idW > 0) defLits = defLits :+ ((x: WR) => x.id -> 0.U) + if (in.userW > 0) defLits = defLits :+ ((x: WR) => x.user -> 0.U) + (new WR(in.idW, in.userW)).Lit(defLits :_*) + } } /** AXI4 read address @@ -121,6 +160,21 @@ object RA { * @return an unitialized RA object */ def apply(addrW: Int, idW: Int = 0, userW: Int = 0) = new RA(addrW, idW, userW) + + /** Default values for this channel + * + * @param in an RA object + * @return an initialized (hardware) RA object + */ + def default(in: RA) = { + var defLits = Seq((x: RA) => x.addr -> 0.U, (x: RA) => x.len -> 0.U, (x: RA) => x.size -> 0.U, + (x: RA) => x.burst -> BurstEncodings.Fixed, (x: RA) => x.lock -> LockEncodings.NormalAccess, + (x: RA) => x.cache -> MemoryEncodings.DeviceNonbuf, (x: RA) => x.prot -> ProtectionEncodings.DataNsecUpriv, + (x: RA) => x.qos -> 0.U, (x: RA) => x.region -> 0.U) + if (in.idW > 0) defLits = defLits :+ ((x: RA) => x.id -> 0.U) + if (in.userW > 0) defLits = defLits :+ ((x: RA) => x.user -> 0.U) + (new RA(in.addrW, in.idW, in.userW)).Lit(defLits :_*) + } } /** AXI4 read data @@ -148,4 +202,17 @@ object RD { * @return an uninitialized RD object */ def apply(dataW: Int, idW: Int = 0, userW: Int = 0) = new RD(dataW, idW, userW) + + /** Default values for this channel + * + * @param in an RD object + * @return an initialized (hardware) RD object + */ + def default(in: RD) = { + var defLits = Seq((x: RD) => x.data -> 0.U, (x: RD) => x.resp -> ResponseEncodings.Okay, + (x: RD) => x.last -> false.B) + if (in.idW > 0) defLits = defLits :+ ((x: RD) => x.id -> 0.U) + if (in.userW > 0) defLits = defLits :+ ((x: RD) => x.user -> 0.U) + (new RD(in.dataW, in.idW, in.userW)).Lit(defLits :_*) + } } diff --git a/axi4/src/main/scala/axi4/FunctionalMaster.scala b/axi4/src/main/scala/axi4/FunctionalMaster.scala index e61a22e..136e754 100644 --- a/axi4/src/main/scala/axi4/FunctionalMaster.scala +++ b/axi4/src/main/scala/axi4/FunctionalMaster.scala @@ -39,56 +39,33 @@ class FunctionalMaster[T <: Slave](dut: T) { private[this] var awaitingWAddr = Seq[WriteTransaction]() private[this] var awaitingWrite = Seq[WriteTransaction]() private[this] var awaitingResp = Seq[WriteTransaction]() - private[this] var responses = Seq[Response]() + private[this] var responses = Seq[Response]() private[this] var wAddrT: TesterThreadList = _ private[this] var writeT: TesterThreadList = _ - private[this] var respT: TesterThreadList = _ + private[this] var respT: TesterThreadList = _ // For reads private[this] var awaitingRAddr = Seq[ReadTransaction]() private[this] var awaitingRead = Seq[ReadTransaction]() private[this] var readValues = Seq[Seq[BigInt]]() private[this] var rAddrT: TesterThreadList = _ - private[this] var readT: TesterThreadList = _ + private[this] var readT: TesterThreadList = _ // For random data private[this] val rng = new Random(42) /** Default values on all signals */ // Address write - if (aw.bits.idW > 0) aw.bits.id.poke(0.U) - aw.bits.addr.poke(0.U) - aw.bits.len.poke(0.U) - aw.bits.size.poke(0.U) - aw.bits.burst.poke(BurstEncodings.Fixed) - aw.bits.lock.poke(LockEncodings.NormalAccess) - aw.bits.cache.poke(MemoryEncodings.DeviceNonbuf) - aw.bits.prot.poke(ProtectionEncodings.DataNsecUpriv) - aw.bits.qos.poke(0.U) - aw.bits.region.poke(0.U) - if (aw.bits.userW > 0) aw.bits.user.poke(0.U) + aw.bits.pokePartial(WA.default(aw.bits)) aw.valid.poke(false.B) // Data write - dw.bits.data.poke(0.U) - dw.bits.strb.poke(0.U) - dw.bits.last.poke(false.B) - if (dw.bits.userW > 0) dw.bits.user.poke(0.U) + dw.bits.pokePartial(WD.default(dw.bits)) dw.valid.poke(false.B) // Write response wr.ready.poke(false.B) // Address read - if (ar.bits.idW > 0) ar.bits.id.poke(0.U) - ar.bits.addr.poke(0.U) - ar.bits.len.poke(0.U) - ar.bits.size.poke(0.U) - ar.bits.burst.poke(BurstEncodings.Fixed) - ar.bits.lock.poke(LockEncodings.NormalAccess) - ar.bits.cache.poke(MemoryEncodings.DeviceNonbuf) - ar.bits.prot.poke(ProtectionEncodings.DataNsecUpriv) - ar.bits.qos.poke(0.U) - ar.bits.region.poke(0.U) - if (ar.bits.userW > 0) ar.bits.user.poke(0.U) + ar.bits.pokePartial(RA.default(ar.bits)) ar.valid.poke(false.B) // Data read