Segfault while trying to synthesize Wally RISC-V core

[infinitymdm]

Hi folks,

I'm trying to use synlig as part of a fully open-source flow to load Wally onto a Digilent Arty A7 FPGA board. The synthesis flow is here under the synth recipe: https://github.com/infinitymdm/cvw/blob/arty-foss-flow/justfile. Since stuff is failing early in the flow, I think you should be able to test without installing nextpnr-xilinx or any of the other software I'm using.

While trying to synthesize the design, I get a segfault with pretty much zero information. The surelog.log doesn't have anything that seems to point me in the right direction either. Here's the command line output: https://pastebin.com/rbvJTYYY

I also tried running the commands individually in yosys. The plugin loads just fine, but I get that segfault as soon as I try to read_systemverilog the source files.

Related (potentially?) to #688.

Any guesses as to what's going wrong?

[alaindargelas]

@infinitymdm, the core dump is fixed here:
https://github.com/alaindargelas/synlig/tree/stable_rs

You'll now get proper error messages about the design that need to be addressed. The design is not synthesizable as-is.