From 22f570b3c0299d5f906e3a25d3f34cb56d022ca7 Mon Sep 17 00:00:00 2001
From: Aditya Naik <aditya.naik@sifive.com>
Date: Wed, 8 Oct 2025 10:33:16 -0700
Subject: [PATCH 01/13] move files over

---
 src/test/{scala-2 => scala}/chisel3/PlaceholderSpec.scala       | 0
 .../{scala-2 => scala}/chisel3/internal/ContainsProbeSpec.scala | 0
 .../{scala-2 => scala}/chisel3/internal/IdentifierSpec.scala    | 0
 .../{scala-2 => scala}/chisel3/internal/NameCollisionSpec.scala | 0
 .../{scala-2 => scala}/chisel3/internal/NamespaceSpec.scala     | 0
 .../chisel3/stage/ChiselOptionsViewSpec.scala                   | 2 +-
 src/test/{scala-2 => scala}/chisel3/testers/TestUtils.scala     | 0
 src/test/{scala-2 => scala}/chisel3/util/BitPatSpec.scala       | 0
 .../chisel3/util/experimental/decode/TruthTableSpec.scala       | 0
 src/test/{scala-2 => scala}/chiselTests/AdderTree.scala         | 2 +-
 .../{scala-2 => scala}/chiselTests/AnalogIntegrationSpec.scala  | 0
 src/test/{scala-2 => scala}/chiselTests/AnalogSpec.scala        | 0
 .../{scala-2 => scala}/chiselTests/AnnotatingDiamondSpec.scala  | 0
 .../{scala-2 => scala}/chiselTests/AnnotationInlineSpec.scala   | 0
 src/test/{scala-2 => scala}/chiselTests/AnnotationNoDedup.scala | 0
 src/test/{scala-2 => scala}/chiselTests/AsTypeOfTester.scala    | 0
 src/test/{scala-2 => scala}/chiselTests/Assert.scala            | 0
 src/test/{scala-2 => scala}/chiselTests/AsyncResetSpec.scala    | 0
 src/test/{scala-2 => scala}/chiselTests/AutoClonetypeSpec.scala | 2 +-
 .../{scala-2 => scala}/chiselTests/AutoNestedCloneSpec.scala    | 0
 src/test/{scala-2 => scala}/chiselTests/BetterNamingTests.scala | 0
 src/test/{scala-2 => scala}/chiselTests/BitwiseOps.scala        | 0
 src/test/{scala-2 => scala}/chiselTests/BlackBox.scala          | 0
 src/test/{scala-2 => scala}/chiselTests/BlackBoxImpl.scala      | 0
 src/test/{scala-2 => scala}/chiselTests/BoolSpec.scala          | 0
 src/test/{scala-2 => scala}/chiselTests/BoringUtilsSpec.scala   | 0
 src/test/{scala-2 => scala}/chiselTests/BulkConnectSpec.scala   | 0
 .../{scala-2 => scala}/chiselTests/BundleElementsSpec.scala     | 0
 src/test/{scala-2 => scala}/chiselTests/BundleLiteralSpec.scala | 0
 src/test/{scala-2 => scala}/chiselTests/BundleWire.scala        | 0
 src/test/{scala-2 => scala}/chiselTests/ChiselEnum.scala        | 0
 .../chiselTests/ChiselTestUtilitiesSpec.scala                   | 0
 src/test/{scala-2 => scala}/chiselTests/ClockSpec.scala         | 0
 src/test/{scala-2 => scala}/chiselTests/CloneModuleSpec.scala   | 0
 src/test/{scala-2 => scala}/chiselTests/ComplexAssign.scala     | 0
 src/test/{scala-2 => scala}/chiselTests/ConnectSpec.scala       | 0
 src/test/{scala-2 => scala}/chiselTests/ConnectableSpec.scala   | 0
 src/test/{scala-2 => scala}/chiselTests/ConstSpec.scala         | 0
 src/test/{scala-2 => scala}/chiselTests/Counter.scala           | 0
 src/test/{scala-2 => scala}/chiselTests/CustomBundle.scala      | 0
 src/test/{scala-2 => scala}/chiselTests/DPISpec.scala           | 0
 src/test/{scala-2 => scala}/chiselTests/DataEqualitySpec.scala  | 0
 src/test/{scala-2 => scala}/chiselTests/DataPrint.scala         | 0
 src/test/{scala-2 => scala}/chiselTests/Decoder.scala           | 0
 src/test/{scala-2 => scala}/chiselTests/DecoupledSpec.scala     | 0
 src/test/{scala-2 => scala}/chiselTests/DedupSpec.scala         | 0
 src/test/{scala-2 => scala}/chiselTests/Direction.scala         | 0
 src/test/{scala-2 => scala}/chiselTests/DisableSpec.scala       | 0
 src/test/{scala-2 => scala}/chiselTests/DontTouchSpec.scala     | 0
 .../{scala-2 => scala}/chiselTests/EnableShiftRegister.scala    | 0
 src/test/{scala-2 => scala}/chiselTests/EnumSpec.scala          | 0
 src/test/{scala-2 => scala}/chiselTests/ExtModule.scala         | 0
 src/test/{scala-2 => scala}/chiselTests/ExtModuleImpl.scala     | 0
 src/test/{scala-2 => scala}/chiselTests/FixedIOModuleSpec.scala | 0
 src/test/{scala-2 => scala}/chiselTests/GCD.scala               | 0
 src/test/{scala-2 => scala}/chiselTests/IOCompatibility.scala   | 0
 src/test/{scala-2 => scala}/chiselTests/IllegalRefSpec.scala    | 0
 .../chiselTests/ImplicitConversionsSpec.scala                   | 0
 src/test/{scala-2 => scala}/chiselTests/InlineSpec.scala        | 0
 src/test/{scala-2 => scala}/chiselTests/InstanceNameSpec.scala  | 0
 src/test/{scala-2 => scala}/chiselTests/IntegerMathSpec.scala   | 0
 src/test/{scala-2 => scala}/chiselTests/IntrinsicModule.scala   | 0
 src/test/{scala-2 => scala}/chiselTests/IntrinsicSpec.scala     | 0
 src/test/{scala-2 => scala}/chiselTests/InvalidateAPISpec.scala | 0
 src/test/{scala-2 => scala}/chiselTests/LazyCloneSpec.scala     | 0
 .../{scala-2 => scala}/chiselTests/LiteralExtractorSpec.scala   | 0
 .../{scala-2 => scala}/chiselTests/LiteralToTargetSpec.scala    | 0
 .../{scala-2 => scala}/chiselTests/LoadMemoryFromFileSpec.scala | 0
 src/test/{scala-2 => scala}/chiselTests/LogUtils.scala          | 0
 src/test/{scala-2 => scala}/chiselTests/Math.scala              | 0
 src/test/{scala-2 => scala}/chiselTests/Mem.scala               | 0
 src/test/{scala-2 => scala}/chiselTests/MemorySearch.scala      | 0
 src/test/{scala-2 => scala}/chiselTests/MixedVecSpec.scala      | 0
 src/test/{scala-2 => scala}/chiselTests/ModuleChoiceSpec.scala  | 0
 src/test/{scala-2 => scala}/chiselTests/ModuleSpec.scala        | 0
 src/test/{scala-2 => scala}/chiselTests/MulLookup.scala         | 0
 src/test/{scala-2 => scala}/chiselTests/MultiAssign.scala       | 0
 src/test/{scala-2 => scala}/chiselTests/MultiClockSpec.scala    | 0
 src/test/{scala-2 => scala}/chiselTests/MuxSpec.scala           | 0
 src/test/{scala-2 => scala}/chiselTests/NamedModuleTester.scala | 0
 src/test/{scala-2 => scala}/chiselTests/OneHotMuxSpec.scala     | 0
 src/test/{scala-2 => scala}/chiselTests/OptionBundle.scala      | 0
 src/test/{scala-2 => scala}/chiselTests/Padding.scala           | 0
 .../{scala-2 => scala}/chiselTests/ParameterizedModule.scala    | 0
 src/test/{scala-2 => scala}/chiselTests/PopCount.scala          | 0
 src/test/{scala-2 => scala}/chiselTests/PortSpec.scala          | 0
 src/test/{scala-2 => scala}/chiselTests/PrintableSpec.scala     | 0
 src/test/{scala-2 => scala}/chiselTests/Printf.scala            | 0
 src/test/{scala-2 => scala}/chiselTests/ProbeSpec.scala         | 0
 src/test/{scala-2 => scala}/chiselTests/PropertyUtils.scala     | 0
 src/test/{scala-2 => scala}/chiselTests/PublicModuleSpec.scala  | 0
 src/test/{scala-2 => scala}/chiselTests/RawModuleSpec.scala     | 0
 src/test/{scala-2 => scala}/chiselTests/ReadOnlySpec.scala      | 0
 src/test/{scala-2 => scala}/chiselTests/RebindingSpec.scala     | 0
 src/test/{scala-2 => scala}/chiselTests/RecordSpec.scala        | 0
 src/test/{scala-2 => scala}/chiselTests/ReduceTreeSpec.scala    | 0
 src/test/{scala-2 => scala}/chiselTests/RegSpec.scala           | 0
 src/test/{scala-2 => scala}/chiselTests/ResetSpec.scala         | 0
 src/test/{scala-2 => scala}/chiselTests/Risc.scala              | 0
 src/test/{scala-2 => scala}/chiselTests/SIntOps.scala           | 0
 src/test/{scala-2 => scala}/chiselTests/SimLogSpec.scala        | 0
 src/test/{scala-2 => scala}/chiselTests/SourceLocatorSpec.scala | 0
 src/test/{scala-2 => scala}/chiselTests/Stack.scala             | 0
 src/test/{scala-2 => scala}/chiselTests/Stop.scala              | 0
 src/test/{scala-2 => scala}/chiselTests/SwitchSpec.scala        | 0
 src/test/{scala-2 => scala}/chiselTests/Tbl.scala               | 0
 src/test/{scala-2 => scala}/chiselTests/TypeAliasSpec.scala     | 0
 src/test/{scala-2 => scala}/chiselTests/UIntOps.scala           | 0
 src/test/{scala-2 => scala}/chiselTests/UnitTestMainSpec.scala  | 0
 src/test/{scala-2 => scala}/chiselTests/Util.scala              | 0
 src/test/{scala-2 => scala}/chiselTests/ValidSpec.scala         | 0
 src/test/{scala-2 => scala}/chiselTests/Vec.scala               | 0
 src/test/{scala-2 => scala}/chiselTests/VecLiteralSpec.scala    | 0
 src/test/{scala-2 => scala}/chiselTests/VecToTargetSpec.scala   | 0
 src/test/{scala-2 => scala}/chiselTests/VectorPacketIO.scala    | 0
 src/test/{scala-2 => scala}/chiselTests/VerificationSpec.scala  | 0
 src/test/{scala-2 => scala}/chiselTests/WarningSpec.scala       | 0
 src/test/{scala-2 => scala}/chiselTests/WhenSpec.scala          | 0
 src/test/{scala-2 => scala}/chiselTests/WidthSpec.scala         | 0
 src/test/{scala-2 => scala}/chiselTests/WireSpec.scala          | 0
 src/test/{scala-2 => scala}/chiselTests/aop/SelectSpec.scala    | 0
 src/test/{scala-2 => scala}/chiselTests/interface/Drivers.scala | 0
 .../chiselTests/interface/InterfaceSpec.scala                   | 0
 .../chiselTests/interface/ParametricInterfaceSpec.scala         | 0
 .../chiselTests/interface/TappedInterfaceSpec.scala             | 0
 .../chiselTests/naming/IdentifierProposerSpec.scala             | 0
 .../{scala-2 => scala}/chiselTests/naming/NamePluginSpec.scala  | 0
 src/test/{scala-2 => scala}/chiselTests/naming/PrefixSpec.scala | 0
 .../{scala-2 => scala}/chiselTests/naming/TypenameSpec.scala    | 0
 .../{scala-2 => scala}/chiselTests/properties/ClassSpec.scala   | 0
 .../{scala-2 => scala}/chiselTests/properties/ObjectSpec.scala  | 0
 .../chiselTests/properties/PropertySpec.scala                   | 0
 .../chiselTests/simulator/EphemeralSimulatorSpec.scala          | 0
 src/test/{scala-2 => scala}/chiselTests/simulator/GCD.scala     | 0
 .../chiselTests/simulator/HasSimulatorSpec.scala                | 0
 .../chiselTests/simulator/LayerControlSpec.scala                | 0
 .../chiselTests/simulator/OptionalIOModule.scala                | 0
 .../chiselTests/simulator/PeekPokeAPISpec.scala                 | 0
 .../chiselTests/simulator/PeekPokeTestModule.scala              | 0
 .../chiselTests/simulator/SimulatorSpec.scala                   | 0
 .../chiselTests/simulator/scalatest/ChiselSimSpec.scala         | 0
 .../chiselTests/simulator/scalatest/HasCliOptionsSpec.scala     | 0
 .../chiselTests/stage/ChiselAnnotationsSpec.scala               | 0
 .../chiselTests/stage/WarningConfigurationSpec.scala            | 0
 .../stage/phases/AddImplicitOutputAnnotationFileSpec.scala      | 0
 .../chiselTests/stage/phases/AddImplicitOutputFileSpec.scala    | 0
 .../stage/phases/AddSerializationAnnotationsSpec.scala          | 0
 .../chiselTests/stage/phases/ChecksSpec.scala                   | 0
 .../chiselTests/stage/phases/ConvertSpec.scala                  | 0
 .../chiselTests/stage/phases/ElaborateSpec.scala                | 0
 .../chiselTests/stage/phases/EmitterSpec.scala                  | 0
 .../{scala-2 => scala}/chiselTests/testing/FileCheckSpec.scala  | 0
 .../chiselTests/testing/HasTestingDirectorySpec.scala           | 0
 .../chiselTests/testing/scalatest/HasConfigMapSpec.scala        | 0
 .../chiselTests/testing/scalatest/TestingDirectorySpec.scala    | 0
 .../chiselTests/util/AttributeAnnotationSpec.scala              | 0
 src/test/{scala-2 => scala}/chiselTests/util/BitSetSpec.scala   | 0
 src/test/{scala-2 => scala}/chiselTests/util/BitwiseSpec.scala  | 0
 src/test/{scala-2 => scala}/chiselTests/util/CatSpec.scala      | 0
 src/test/{scala-2 => scala}/chiselTests/util/PipeSpec.scala     | 0
 .../{scala-2 => scala}/chiselTests/util/PriorityMuxSpec.scala   | 0
 src/test/{scala-2 => scala}/chiselTests/util/RegSpec.scala      | 0
 src/test/{scala-2 => scala}/chiselTests/util/SRAMSpec.scala     | 0
 .../{scala-2 => scala}/chiselTests/util/circt/ClockGate.scala   | 0
 .../{scala-2 => scala}/chiselTests/util/circt/IsXSpec.scala     | 0
 .../chiselTests/util/circt/PlusArgsTestSpec.scala               | 0
 .../chiselTests/util/circt/PlusArgsValueSpec.scala              | 0
 .../{scala-2 => scala}/chiselTests/util/circt/SizeOfSpec.scala  | 0
 .../{scala-2 => scala}/chiselTests/util/circt/Synthesis.scala   | 0
 .../chiselTests/util/experimental/DecoderTableSpec.scala        | 0
 .../{scala-2 => scala}/chiselTests/util/random/PRNGSpec.scala   | 0
 src/test/{scala-2 => scala}/circtTests/ConventionSpec.scala     | 0
 .../{scala-2 => scala}/circtTests/OutputDirAnnotationSpec.scala | 0
 .../{scala-2 => scala}/circtTests/stage/ChiselMainSpec.scala    | 0
 .../{scala-2 => scala}/circtTests/stage/ChiselStageSpec.scala   | 0
 .../circtTests/stage/phases/AddImplicitOutputFileSpec.scala     | 0
 src/test/{scala-2 => scala}/cookbook/Bundle2UInt.scala          | 0
 src/test/{scala-2 => scala}/cookbook/CookbookSpec.scala         | 0
 src/test/{scala-2 => scala}/cookbook/FSM.scala                  | 0
 src/test/{scala-2 => scala}/cookbook/RegOfVec.scala             | 0
 src/test/{scala-2 => scala}/cookbook/UInt2Bundle.scala          | 0
 src/test/{scala-2 => scala}/cookbook/UInt2VecOfBool.scala       | 0
 src/test/{scala-2 => scala}/cookbook/VecOfBool2UInt.scala       | 0
 .../examples/ImplicitStateVendingMachine.scala                  | 0
 src/test/{scala-2 => scala}/examples/SimpleVendingMachine.scala | 0
 .../{scala-2 => scala}/examples/VendingMachineGenerator.scala   | 0
 src/test/{scala-2 => scala}/examples/VendingMachineUtils.scala  | 0
 187 files changed, 3 insertions(+), 3 deletions(-)
 rename src/test/{scala-2 => scala}/chisel3/PlaceholderSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chisel3/internal/ContainsProbeSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chisel3/internal/IdentifierSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chisel3/internal/NameCollisionSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chisel3/internal/NamespaceSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chisel3/stage/ChiselOptionsViewSpec.scala (96%)
 rename src/test/{scala-2 => scala}/chisel3/testers/TestUtils.scala (100%)
 rename src/test/{scala-2 => scala}/chisel3/util/BitPatSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chisel3/util/experimental/decode/TruthTableSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/AdderTree.scala (97%)
 rename src/test/{scala-2 => scala}/chiselTests/AnalogIntegrationSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/AnalogSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/AnnotatingDiamondSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/AnnotationInlineSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/AnnotationNoDedup.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/AsTypeOfTester.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/Assert.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/AsyncResetSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/AutoClonetypeSpec.scala (99%)
 rename src/test/{scala-2 => scala}/chiselTests/AutoNestedCloneSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/BetterNamingTests.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/BitwiseOps.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/BlackBox.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/BlackBoxImpl.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/BoolSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/BoringUtilsSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/BulkConnectSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/BundleElementsSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/BundleLiteralSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/BundleWire.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ChiselEnum.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ChiselTestUtilitiesSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ClockSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/CloneModuleSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ComplexAssign.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ConnectSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ConnectableSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ConstSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/Counter.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/CustomBundle.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/DPISpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/DataEqualitySpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/DataPrint.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/Decoder.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/DecoupledSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/DedupSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/Direction.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/DisableSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/DontTouchSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/EnableShiftRegister.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/EnumSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ExtModule.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ExtModuleImpl.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/FixedIOModuleSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/GCD.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/IOCompatibility.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/IllegalRefSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ImplicitConversionsSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/InlineSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/InstanceNameSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/IntegerMathSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/IntrinsicModule.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/IntrinsicSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/InvalidateAPISpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/LazyCloneSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/LiteralExtractorSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/LiteralToTargetSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/LoadMemoryFromFileSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/LogUtils.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/Math.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/Mem.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/MemorySearch.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/MixedVecSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ModuleChoiceSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ModuleSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/MulLookup.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/MultiAssign.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/MultiClockSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/MuxSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/NamedModuleTester.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/OneHotMuxSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/OptionBundle.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/Padding.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ParameterizedModule.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/PopCount.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/PortSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/PrintableSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/Printf.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ProbeSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/PropertyUtils.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/PublicModuleSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/RawModuleSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ReadOnlySpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/RebindingSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/RecordSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ReduceTreeSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/RegSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ResetSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/Risc.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/SIntOps.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/SimLogSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/SourceLocatorSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/Stack.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/Stop.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/SwitchSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/Tbl.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/TypeAliasSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/UIntOps.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/UnitTestMainSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/Util.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/ValidSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/Vec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/VecLiteralSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/VecToTargetSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/VectorPacketIO.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/VerificationSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/WarningSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/WhenSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/WidthSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/WireSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/aop/SelectSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/interface/Drivers.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/interface/InterfaceSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/interface/ParametricInterfaceSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/interface/TappedInterfaceSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/naming/IdentifierProposerSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/naming/NamePluginSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/naming/PrefixSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/naming/TypenameSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/properties/ClassSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/properties/ObjectSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/properties/PropertySpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/simulator/EphemeralSimulatorSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/simulator/GCD.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/simulator/HasSimulatorSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/simulator/LayerControlSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/simulator/OptionalIOModule.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/simulator/PeekPokeAPISpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/simulator/PeekPokeTestModule.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/simulator/SimulatorSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/simulator/scalatest/ChiselSimSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/simulator/scalatest/HasCliOptionsSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/stage/ChiselAnnotationsSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/stage/WarningConfigurationSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/stage/phases/ChecksSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/stage/phases/ConvertSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/stage/phases/ElaborateSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/stage/phases/EmitterSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/testing/FileCheckSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/testing/HasTestingDirectorySpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/testing/scalatest/HasConfigMapSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/testing/scalatest/TestingDirectorySpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/AttributeAnnotationSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/BitSetSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/BitwiseSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/CatSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/PipeSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/PriorityMuxSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/RegSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/SRAMSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/circt/ClockGate.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/circt/IsXSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/circt/PlusArgsTestSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/circt/PlusArgsValueSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/circt/SizeOfSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/circt/Synthesis.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/experimental/DecoderTableSpec.scala (100%)
 rename src/test/{scala-2 => scala}/chiselTests/util/random/PRNGSpec.scala (100%)
 rename src/test/{scala-2 => scala}/circtTests/ConventionSpec.scala (100%)
 rename src/test/{scala-2 => scala}/circtTests/OutputDirAnnotationSpec.scala (100%)
 rename src/test/{scala-2 => scala}/circtTests/stage/ChiselMainSpec.scala (100%)
 rename src/test/{scala-2 => scala}/circtTests/stage/ChiselStageSpec.scala (100%)
 rename src/test/{scala-2 => scala}/circtTests/stage/phases/AddImplicitOutputFileSpec.scala (100%)
 rename src/test/{scala-2 => scala}/cookbook/Bundle2UInt.scala (100%)
 rename src/test/{scala-2 => scala}/cookbook/CookbookSpec.scala (100%)
 rename src/test/{scala-2 => scala}/cookbook/FSM.scala (100%)
 rename src/test/{scala-2 => scala}/cookbook/RegOfVec.scala (100%)
 rename src/test/{scala-2 => scala}/cookbook/UInt2Bundle.scala (100%)
 rename src/test/{scala-2 => scala}/cookbook/UInt2VecOfBool.scala (100%)
 rename src/test/{scala-2 => scala}/cookbook/VecOfBool2UInt.scala (100%)
 rename src/test/{scala-2 => scala}/examples/ImplicitStateVendingMachine.scala (100%)
 rename src/test/{scala-2 => scala}/examples/SimpleVendingMachine.scala (100%)
 rename src/test/{scala-2 => scala}/examples/VendingMachineGenerator.scala (100%)
 rename src/test/{scala-2 => scala}/examples/VendingMachineUtils.scala (100%)

diff --git a/src/test/scala-2/chisel3/PlaceholderSpec.scala b/src/test/scala/chisel3/PlaceholderSpec.scala
similarity index 100%
rename from src/test/scala-2/chisel3/PlaceholderSpec.scala
rename to src/test/scala/chisel3/PlaceholderSpec.scala
diff --git a/src/test/scala-2/chisel3/internal/ContainsProbeSpec.scala b/src/test/scala/chisel3/internal/ContainsProbeSpec.scala
similarity index 100%
rename from src/test/scala-2/chisel3/internal/ContainsProbeSpec.scala
rename to src/test/scala/chisel3/internal/ContainsProbeSpec.scala
diff --git a/src/test/scala-2/chisel3/internal/IdentifierSpec.scala b/src/test/scala/chisel3/internal/IdentifierSpec.scala
similarity index 100%
rename from src/test/scala-2/chisel3/internal/IdentifierSpec.scala
rename to src/test/scala/chisel3/internal/IdentifierSpec.scala
diff --git a/src/test/scala-2/chisel3/internal/NameCollisionSpec.scala b/src/test/scala/chisel3/internal/NameCollisionSpec.scala
similarity index 100%
rename from src/test/scala-2/chisel3/internal/NameCollisionSpec.scala
rename to src/test/scala/chisel3/internal/NameCollisionSpec.scala
diff --git a/src/test/scala-2/chisel3/internal/NamespaceSpec.scala b/src/test/scala/chisel3/internal/NamespaceSpec.scala
similarity index 100%
rename from src/test/scala-2/chisel3/internal/NamespaceSpec.scala
rename to src/test/scala/chisel3/internal/NamespaceSpec.scala
diff --git a/src/test/scala-2/chisel3/stage/ChiselOptionsViewSpec.scala b/src/test/scala/chisel3/stage/ChiselOptionsViewSpec.scala
similarity index 96%
rename from src/test/scala-2/chisel3/stage/ChiselOptionsViewSpec.scala
rename to src/test/scala/chisel3/stage/ChiselOptionsViewSpec.scala
index 73c34e291fc..e0b07c2cab6 100644
--- a/src/test/scala-2/chisel3/stage/ChiselOptionsViewSpec.scala
+++ b/src/test/scala/chisel3/stage/ChiselOptionsViewSpec.scala
@@ -3,7 +3,7 @@
 package chisel3.stage
 
 import firrtl.options.Viewer.view
-import firrtl.RenameMap
+import firrtl.{RenameMap, seqToAnnoSeq}
 
 import chisel3.ElaboratedCircuit
 import chisel3.stage._
diff --git a/src/test/scala-2/chisel3/testers/TestUtils.scala b/src/test/scala/chisel3/testers/TestUtils.scala
similarity index 100%
rename from src/test/scala-2/chisel3/testers/TestUtils.scala
rename to src/test/scala/chisel3/testers/TestUtils.scala
diff --git a/src/test/scala-2/chisel3/util/BitPatSpec.scala b/src/test/scala/chisel3/util/BitPatSpec.scala
similarity index 100%
rename from src/test/scala-2/chisel3/util/BitPatSpec.scala
rename to src/test/scala/chisel3/util/BitPatSpec.scala
diff --git a/src/test/scala-2/chisel3/util/experimental/decode/TruthTableSpec.scala b/src/test/scala/chisel3/util/experimental/decode/TruthTableSpec.scala
similarity index 100%
rename from src/test/scala-2/chisel3/util/experimental/decode/TruthTableSpec.scala
rename to src/test/scala/chisel3/util/experimental/decode/TruthTableSpec.scala
diff --git a/src/test/scala-2/chiselTests/AdderTree.scala b/src/test/scala/chiselTests/AdderTree.scala
similarity index 97%
rename from src/test/scala-2/chiselTests/AdderTree.scala
rename to src/test/scala/chiselTests/AdderTree.scala
index 9c5b4b5f3f6..5ba178458bb 100644
--- a/src/test/scala-2/chiselTests/AdderTree.scala
+++ b/src/test/scala/chiselTests/AdderTree.scala
@@ -20,7 +20,7 @@ class AdderTreeTester(bitWidth: Int, numsToAdd: List[Int]) extends Module {
   val dut = Module(new AdderTree(genType, numsToAdd.size))
   dut.io.numIn := VecInit(numsToAdd.map(x => x.asUInt(bitWidth.W)))
   val sumCorrect = dut.io.numOut === (numsToAdd.reduce(_ + _) % (1 << bitWidth)).asUInt(bitWidth.W)
-  assert(sumCorrect)
+  chisel3.assert(sumCorrect)
   stop()
 }
 
diff --git a/src/test/scala-2/chiselTests/AnalogIntegrationSpec.scala b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/AnalogIntegrationSpec.scala
rename to src/test/scala/chiselTests/AnalogIntegrationSpec.scala
diff --git a/src/test/scala-2/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/AnalogSpec.scala
rename to src/test/scala/chiselTests/AnalogSpec.scala
diff --git a/src/test/scala-2/chiselTests/AnnotatingDiamondSpec.scala b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/AnnotatingDiamondSpec.scala
rename to src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
diff --git a/src/test/scala-2/chiselTests/AnnotationInlineSpec.scala b/src/test/scala/chiselTests/AnnotationInlineSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/AnnotationInlineSpec.scala
rename to src/test/scala/chiselTests/AnnotationInlineSpec.scala
diff --git a/src/test/scala-2/chiselTests/AnnotationNoDedup.scala b/src/test/scala/chiselTests/AnnotationNoDedup.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/AnnotationNoDedup.scala
rename to src/test/scala/chiselTests/AnnotationNoDedup.scala
diff --git a/src/test/scala-2/chiselTests/AsTypeOfTester.scala b/src/test/scala/chiselTests/AsTypeOfTester.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/AsTypeOfTester.scala
rename to src/test/scala/chiselTests/AsTypeOfTester.scala
diff --git a/src/test/scala-2/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/Assert.scala
rename to src/test/scala/chiselTests/Assert.scala
diff --git a/src/test/scala-2/chiselTests/AsyncResetSpec.scala b/src/test/scala/chiselTests/AsyncResetSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/AsyncResetSpec.scala
rename to src/test/scala/chiselTests/AsyncResetSpec.scala
diff --git a/src/test/scala-2/chiselTests/AutoClonetypeSpec.scala b/src/test/scala/chiselTests/AutoClonetypeSpec.scala
similarity index 99%
rename from src/test/scala-2/chiselTests/AutoClonetypeSpec.scala
rename to src/test/scala/chiselTests/AutoClonetypeSpec.scala
index 42f008fa65d..6411430c878 100644
--- a/src/test/scala-2/chiselTests/AutoClonetypeSpec.scala
+++ b/src/test/scala/chiselTests/AutoClonetypeSpec.scala
@@ -344,7 +344,7 @@ class AutoClonetypeSpec extends AnyFlatSpec with Matchers {
     }
     emitCHIRRTL {
       new Module {
-        implicit val x = 8
+        implicit val x: Int = 8
         val in = IO(Input(new MyBundle))
         val out = IO(Output(new MyBundle))
         out := in
diff --git a/src/test/scala-2/chiselTests/AutoNestedCloneSpec.scala b/src/test/scala/chiselTests/AutoNestedCloneSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/AutoNestedCloneSpec.scala
rename to src/test/scala/chiselTests/AutoNestedCloneSpec.scala
diff --git a/src/test/scala-2/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/BetterNamingTests.scala
rename to src/test/scala/chiselTests/BetterNamingTests.scala
diff --git a/src/test/scala-2/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/BitwiseOps.scala
rename to src/test/scala/chiselTests/BitwiseOps.scala
diff --git a/src/test/scala-2/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/BlackBox.scala
rename to src/test/scala/chiselTests/BlackBox.scala
diff --git a/src/test/scala-2/chiselTests/BlackBoxImpl.scala b/src/test/scala/chiselTests/BlackBoxImpl.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/BlackBoxImpl.scala
rename to src/test/scala/chiselTests/BlackBoxImpl.scala
diff --git a/src/test/scala-2/chiselTests/BoolSpec.scala b/src/test/scala/chiselTests/BoolSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/BoolSpec.scala
rename to src/test/scala/chiselTests/BoolSpec.scala
diff --git a/src/test/scala-2/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/BoringUtilsSpec.scala
rename to src/test/scala/chiselTests/BoringUtilsSpec.scala
diff --git a/src/test/scala-2/chiselTests/BulkConnectSpec.scala b/src/test/scala/chiselTests/BulkConnectSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/BulkConnectSpec.scala
rename to src/test/scala/chiselTests/BulkConnectSpec.scala
diff --git a/src/test/scala-2/chiselTests/BundleElementsSpec.scala b/src/test/scala/chiselTests/BundleElementsSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/BundleElementsSpec.scala
rename to src/test/scala/chiselTests/BundleElementsSpec.scala
diff --git a/src/test/scala-2/chiselTests/BundleLiteralSpec.scala b/src/test/scala/chiselTests/BundleLiteralSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/BundleLiteralSpec.scala
rename to src/test/scala/chiselTests/BundleLiteralSpec.scala
diff --git a/src/test/scala-2/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/BundleWire.scala
rename to src/test/scala/chiselTests/BundleWire.scala
diff --git a/src/test/scala-2/chiselTests/ChiselEnum.scala b/src/test/scala/chiselTests/ChiselEnum.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ChiselEnum.scala
rename to src/test/scala/chiselTests/ChiselEnum.scala
diff --git a/src/test/scala-2/chiselTests/ChiselTestUtilitiesSpec.scala b/src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ChiselTestUtilitiesSpec.scala
rename to src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala
diff --git a/src/test/scala-2/chiselTests/ClockSpec.scala b/src/test/scala/chiselTests/ClockSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ClockSpec.scala
rename to src/test/scala/chiselTests/ClockSpec.scala
diff --git a/src/test/scala-2/chiselTests/CloneModuleSpec.scala b/src/test/scala/chiselTests/CloneModuleSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/CloneModuleSpec.scala
rename to src/test/scala/chiselTests/CloneModuleSpec.scala
diff --git a/src/test/scala-2/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ComplexAssign.scala
rename to src/test/scala/chiselTests/ComplexAssign.scala
diff --git a/src/test/scala-2/chiselTests/ConnectSpec.scala b/src/test/scala/chiselTests/ConnectSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ConnectSpec.scala
rename to src/test/scala/chiselTests/ConnectSpec.scala
diff --git a/src/test/scala-2/chiselTests/ConnectableSpec.scala b/src/test/scala/chiselTests/ConnectableSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ConnectableSpec.scala
rename to src/test/scala/chiselTests/ConnectableSpec.scala
diff --git a/src/test/scala-2/chiselTests/ConstSpec.scala b/src/test/scala/chiselTests/ConstSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ConstSpec.scala
rename to src/test/scala/chiselTests/ConstSpec.scala
diff --git a/src/test/scala-2/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/Counter.scala
rename to src/test/scala/chiselTests/Counter.scala
diff --git a/src/test/scala-2/chiselTests/CustomBundle.scala b/src/test/scala/chiselTests/CustomBundle.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/CustomBundle.scala
rename to src/test/scala/chiselTests/CustomBundle.scala
diff --git a/src/test/scala-2/chiselTests/DPISpec.scala b/src/test/scala/chiselTests/DPISpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/DPISpec.scala
rename to src/test/scala/chiselTests/DPISpec.scala
diff --git a/src/test/scala-2/chiselTests/DataEqualitySpec.scala b/src/test/scala/chiselTests/DataEqualitySpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/DataEqualitySpec.scala
rename to src/test/scala/chiselTests/DataEqualitySpec.scala
diff --git a/src/test/scala-2/chiselTests/DataPrint.scala b/src/test/scala/chiselTests/DataPrint.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/DataPrint.scala
rename to src/test/scala/chiselTests/DataPrint.scala
diff --git a/src/test/scala-2/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/Decoder.scala
rename to src/test/scala/chiselTests/Decoder.scala
diff --git a/src/test/scala-2/chiselTests/DecoupledSpec.scala b/src/test/scala/chiselTests/DecoupledSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/DecoupledSpec.scala
rename to src/test/scala/chiselTests/DecoupledSpec.scala
diff --git a/src/test/scala-2/chiselTests/DedupSpec.scala b/src/test/scala/chiselTests/DedupSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/DedupSpec.scala
rename to src/test/scala/chiselTests/DedupSpec.scala
diff --git a/src/test/scala-2/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/Direction.scala
rename to src/test/scala/chiselTests/Direction.scala
diff --git a/src/test/scala-2/chiselTests/DisableSpec.scala b/src/test/scala/chiselTests/DisableSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/DisableSpec.scala
rename to src/test/scala/chiselTests/DisableSpec.scala
diff --git a/src/test/scala-2/chiselTests/DontTouchSpec.scala b/src/test/scala/chiselTests/DontTouchSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/DontTouchSpec.scala
rename to src/test/scala/chiselTests/DontTouchSpec.scala
diff --git a/src/test/scala-2/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/EnableShiftRegister.scala
rename to src/test/scala/chiselTests/EnableShiftRegister.scala
diff --git a/src/test/scala-2/chiselTests/EnumSpec.scala b/src/test/scala/chiselTests/EnumSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/EnumSpec.scala
rename to src/test/scala/chiselTests/EnumSpec.scala
diff --git a/src/test/scala-2/chiselTests/ExtModule.scala b/src/test/scala/chiselTests/ExtModule.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ExtModule.scala
rename to src/test/scala/chiselTests/ExtModule.scala
diff --git a/src/test/scala-2/chiselTests/ExtModuleImpl.scala b/src/test/scala/chiselTests/ExtModuleImpl.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ExtModuleImpl.scala
rename to src/test/scala/chiselTests/ExtModuleImpl.scala
diff --git a/src/test/scala-2/chiselTests/FixedIOModuleSpec.scala b/src/test/scala/chiselTests/FixedIOModuleSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/FixedIOModuleSpec.scala
rename to src/test/scala/chiselTests/FixedIOModuleSpec.scala
diff --git a/src/test/scala-2/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/GCD.scala
rename to src/test/scala/chiselTests/GCD.scala
diff --git a/src/test/scala-2/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/IOCompatibility.scala
rename to src/test/scala/chiselTests/IOCompatibility.scala
diff --git a/src/test/scala-2/chiselTests/IllegalRefSpec.scala b/src/test/scala/chiselTests/IllegalRefSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/IllegalRefSpec.scala
rename to src/test/scala/chiselTests/IllegalRefSpec.scala
diff --git a/src/test/scala-2/chiselTests/ImplicitConversionsSpec.scala b/src/test/scala/chiselTests/ImplicitConversionsSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ImplicitConversionsSpec.scala
rename to src/test/scala/chiselTests/ImplicitConversionsSpec.scala
diff --git a/src/test/scala-2/chiselTests/InlineSpec.scala b/src/test/scala/chiselTests/InlineSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/InlineSpec.scala
rename to src/test/scala/chiselTests/InlineSpec.scala
diff --git a/src/test/scala-2/chiselTests/InstanceNameSpec.scala b/src/test/scala/chiselTests/InstanceNameSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/InstanceNameSpec.scala
rename to src/test/scala/chiselTests/InstanceNameSpec.scala
diff --git a/src/test/scala-2/chiselTests/IntegerMathSpec.scala b/src/test/scala/chiselTests/IntegerMathSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/IntegerMathSpec.scala
rename to src/test/scala/chiselTests/IntegerMathSpec.scala
diff --git a/src/test/scala-2/chiselTests/IntrinsicModule.scala b/src/test/scala/chiselTests/IntrinsicModule.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/IntrinsicModule.scala
rename to src/test/scala/chiselTests/IntrinsicModule.scala
diff --git a/src/test/scala-2/chiselTests/IntrinsicSpec.scala b/src/test/scala/chiselTests/IntrinsicSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/IntrinsicSpec.scala
rename to src/test/scala/chiselTests/IntrinsicSpec.scala
diff --git a/src/test/scala-2/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/InvalidateAPISpec.scala
rename to src/test/scala/chiselTests/InvalidateAPISpec.scala
diff --git a/src/test/scala-2/chiselTests/LazyCloneSpec.scala b/src/test/scala/chiselTests/LazyCloneSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/LazyCloneSpec.scala
rename to src/test/scala/chiselTests/LazyCloneSpec.scala
diff --git a/src/test/scala-2/chiselTests/LiteralExtractorSpec.scala b/src/test/scala/chiselTests/LiteralExtractorSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/LiteralExtractorSpec.scala
rename to src/test/scala/chiselTests/LiteralExtractorSpec.scala
diff --git a/src/test/scala-2/chiselTests/LiteralToTargetSpec.scala b/src/test/scala/chiselTests/LiteralToTargetSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/LiteralToTargetSpec.scala
rename to src/test/scala/chiselTests/LiteralToTargetSpec.scala
diff --git a/src/test/scala-2/chiselTests/LoadMemoryFromFileSpec.scala b/src/test/scala/chiselTests/LoadMemoryFromFileSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/LoadMemoryFromFileSpec.scala
rename to src/test/scala/chiselTests/LoadMemoryFromFileSpec.scala
diff --git a/src/test/scala-2/chiselTests/LogUtils.scala b/src/test/scala/chiselTests/LogUtils.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/LogUtils.scala
rename to src/test/scala/chiselTests/LogUtils.scala
diff --git a/src/test/scala-2/chiselTests/Math.scala b/src/test/scala/chiselTests/Math.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/Math.scala
rename to src/test/scala/chiselTests/Math.scala
diff --git a/src/test/scala-2/chiselTests/Mem.scala b/src/test/scala/chiselTests/Mem.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/Mem.scala
rename to src/test/scala/chiselTests/Mem.scala
diff --git a/src/test/scala-2/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/MemorySearch.scala
rename to src/test/scala/chiselTests/MemorySearch.scala
diff --git a/src/test/scala-2/chiselTests/MixedVecSpec.scala b/src/test/scala/chiselTests/MixedVecSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/MixedVecSpec.scala
rename to src/test/scala/chiselTests/MixedVecSpec.scala
diff --git a/src/test/scala-2/chiselTests/ModuleChoiceSpec.scala b/src/test/scala/chiselTests/ModuleChoiceSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ModuleChoiceSpec.scala
rename to src/test/scala/chiselTests/ModuleChoiceSpec.scala
diff --git a/src/test/scala-2/chiselTests/ModuleSpec.scala b/src/test/scala/chiselTests/ModuleSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ModuleSpec.scala
rename to src/test/scala/chiselTests/ModuleSpec.scala
diff --git a/src/test/scala-2/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/MulLookup.scala
rename to src/test/scala/chiselTests/MulLookup.scala
diff --git a/src/test/scala-2/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/MultiAssign.scala
rename to src/test/scala/chiselTests/MultiAssign.scala
diff --git a/src/test/scala-2/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/MultiClockSpec.scala
rename to src/test/scala/chiselTests/MultiClockSpec.scala
diff --git a/src/test/scala-2/chiselTests/MuxSpec.scala b/src/test/scala/chiselTests/MuxSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/MuxSpec.scala
rename to src/test/scala/chiselTests/MuxSpec.scala
diff --git a/src/test/scala-2/chiselTests/NamedModuleTester.scala b/src/test/scala/chiselTests/NamedModuleTester.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/NamedModuleTester.scala
rename to src/test/scala/chiselTests/NamedModuleTester.scala
diff --git a/src/test/scala-2/chiselTests/OneHotMuxSpec.scala b/src/test/scala/chiselTests/OneHotMuxSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/OneHotMuxSpec.scala
rename to src/test/scala/chiselTests/OneHotMuxSpec.scala
diff --git a/src/test/scala-2/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/OptionBundle.scala
rename to src/test/scala/chiselTests/OptionBundle.scala
diff --git a/src/test/scala-2/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/Padding.scala
rename to src/test/scala/chiselTests/Padding.scala
diff --git a/src/test/scala-2/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ParameterizedModule.scala
rename to src/test/scala/chiselTests/ParameterizedModule.scala
diff --git a/src/test/scala-2/chiselTests/PopCount.scala b/src/test/scala/chiselTests/PopCount.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/PopCount.scala
rename to src/test/scala/chiselTests/PopCount.scala
diff --git a/src/test/scala-2/chiselTests/PortSpec.scala b/src/test/scala/chiselTests/PortSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/PortSpec.scala
rename to src/test/scala/chiselTests/PortSpec.scala
diff --git a/src/test/scala-2/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/PrintableSpec.scala
rename to src/test/scala/chiselTests/PrintableSpec.scala
diff --git a/src/test/scala-2/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/Printf.scala
rename to src/test/scala/chiselTests/Printf.scala
diff --git a/src/test/scala-2/chiselTests/ProbeSpec.scala b/src/test/scala/chiselTests/ProbeSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ProbeSpec.scala
rename to src/test/scala/chiselTests/ProbeSpec.scala
diff --git a/src/test/scala-2/chiselTests/PropertyUtils.scala b/src/test/scala/chiselTests/PropertyUtils.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/PropertyUtils.scala
rename to src/test/scala/chiselTests/PropertyUtils.scala
diff --git a/src/test/scala-2/chiselTests/PublicModuleSpec.scala b/src/test/scala/chiselTests/PublicModuleSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/PublicModuleSpec.scala
rename to src/test/scala/chiselTests/PublicModuleSpec.scala
diff --git a/src/test/scala-2/chiselTests/RawModuleSpec.scala b/src/test/scala/chiselTests/RawModuleSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/RawModuleSpec.scala
rename to src/test/scala/chiselTests/RawModuleSpec.scala
diff --git a/src/test/scala-2/chiselTests/ReadOnlySpec.scala b/src/test/scala/chiselTests/ReadOnlySpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ReadOnlySpec.scala
rename to src/test/scala/chiselTests/ReadOnlySpec.scala
diff --git a/src/test/scala-2/chiselTests/RebindingSpec.scala b/src/test/scala/chiselTests/RebindingSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/RebindingSpec.scala
rename to src/test/scala/chiselTests/RebindingSpec.scala
diff --git a/src/test/scala-2/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/RecordSpec.scala
rename to src/test/scala/chiselTests/RecordSpec.scala
diff --git a/src/test/scala-2/chiselTests/ReduceTreeSpec.scala b/src/test/scala/chiselTests/ReduceTreeSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ReduceTreeSpec.scala
rename to src/test/scala/chiselTests/ReduceTreeSpec.scala
diff --git a/src/test/scala-2/chiselTests/RegSpec.scala b/src/test/scala/chiselTests/RegSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/RegSpec.scala
rename to src/test/scala/chiselTests/RegSpec.scala
diff --git a/src/test/scala-2/chiselTests/ResetSpec.scala b/src/test/scala/chiselTests/ResetSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ResetSpec.scala
rename to src/test/scala/chiselTests/ResetSpec.scala
diff --git a/src/test/scala-2/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/Risc.scala
rename to src/test/scala/chiselTests/Risc.scala
diff --git a/src/test/scala-2/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/SIntOps.scala
rename to src/test/scala/chiselTests/SIntOps.scala
diff --git a/src/test/scala-2/chiselTests/SimLogSpec.scala b/src/test/scala/chiselTests/SimLogSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/SimLogSpec.scala
rename to src/test/scala/chiselTests/SimLogSpec.scala
diff --git a/src/test/scala-2/chiselTests/SourceLocatorSpec.scala b/src/test/scala/chiselTests/SourceLocatorSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/SourceLocatorSpec.scala
rename to src/test/scala/chiselTests/SourceLocatorSpec.scala
diff --git a/src/test/scala-2/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/Stack.scala
rename to src/test/scala/chiselTests/Stack.scala
diff --git a/src/test/scala-2/chiselTests/Stop.scala b/src/test/scala/chiselTests/Stop.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/Stop.scala
rename to src/test/scala/chiselTests/Stop.scala
diff --git a/src/test/scala-2/chiselTests/SwitchSpec.scala b/src/test/scala/chiselTests/SwitchSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/SwitchSpec.scala
rename to src/test/scala/chiselTests/SwitchSpec.scala
diff --git a/src/test/scala-2/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/Tbl.scala
rename to src/test/scala/chiselTests/Tbl.scala
diff --git a/src/test/scala-2/chiselTests/TypeAliasSpec.scala b/src/test/scala/chiselTests/TypeAliasSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/TypeAliasSpec.scala
rename to src/test/scala/chiselTests/TypeAliasSpec.scala
diff --git a/src/test/scala-2/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/UIntOps.scala
rename to src/test/scala/chiselTests/UIntOps.scala
diff --git a/src/test/scala-2/chiselTests/UnitTestMainSpec.scala b/src/test/scala/chiselTests/UnitTestMainSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/UnitTestMainSpec.scala
rename to src/test/scala/chiselTests/UnitTestMainSpec.scala
diff --git a/src/test/scala-2/chiselTests/Util.scala b/src/test/scala/chiselTests/Util.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/Util.scala
rename to src/test/scala/chiselTests/Util.scala
diff --git a/src/test/scala-2/chiselTests/ValidSpec.scala b/src/test/scala/chiselTests/ValidSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/ValidSpec.scala
rename to src/test/scala/chiselTests/ValidSpec.scala
diff --git a/src/test/scala-2/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/Vec.scala
rename to src/test/scala/chiselTests/Vec.scala
diff --git a/src/test/scala-2/chiselTests/VecLiteralSpec.scala b/src/test/scala/chiselTests/VecLiteralSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/VecLiteralSpec.scala
rename to src/test/scala/chiselTests/VecLiteralSpec.scala
diff --git a/src/test/scala-2/chiselTests/VecToTargetSpec.scala b/src/test/scala/chiselTests/VecToTargetSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/VecToTargetSpec.scala
rename to src/test/scala/chiselTests/VecToTargetSpec.scala
diff --git a/src/test/scala-2/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/VectorPacketIO.scala
rename to src/test/scala/chiselTests/VectorPacketIO.scala
diff --git a/src/test/scala-2/chiselTests/VerificationSpec.scala b/src/test/scala/chiselTests/VerificationSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/VerificationSpec.scala
rename to src/test/scala/chiselTests/VerificationSpec.scala
diff --git a/src/test/scala-2/chiselTests/WarningSpec.scala b/src/test/scala/chiselTests/WarningSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/WarningSpec.scala
rename to src/test/scala/chiselTests/WarningSpec.scala
diff --git a/src/test/scala-2/chiselTests/WhenSpec.scala b/src/test/scala/chiselTests/WhenSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/WhenSpec.scala
rename to src/test/scala/chiselTests/WhenSpec.scala
diff --git a/src/test/scala-2/chiselTests/WidthSpec.scala b/src/test/scala/chiselTests/WidthSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/WidthSpec.scala
rename to src/test/scala/chiselTests/WidthSpec.scala
diff --git a/src/test/scala-2/chiselTests/WireSpec.scala b/src/test/scala/chiselTests/WireSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/WireSpec.scala
rename to src/test/scala/chiselTests/WireSpec.scala
diff --git a/src/test/scala-2/chiselTests/aop/SelectSpec.scala b/src/test/scala/chiselTests/aop/SelectSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/aop/SelectSpec.scala
rename to src/test/scala/chiselTests/aop/SelectSpec.scala
diff --git a/src/test/scala-2/chiselTests/interface/Drivers.scala b/src/test/scala/chiselTests/interface/Drivers.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/interface/Drivers.scala
rename to src/test/scala/chiselTests/interface/Drivers.scala
diff --git a/src/test/scala-2/chiselTests/interface/InterfaceSpec.scala b/src/test/scala/chiselTests/interface/InterfaceSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/interface/InterfaceSpec.scala
rename to src/test/scala/chiselTests/interface/InterfaceSpec.scala
diff --git a/src/test/scala-2/chiselTests/interface/ParametricInterfaceSpec.scala b/src/test/scala/chiselTests/interface/ParametricInterfaceSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/interface/ParametricInterfaceSpec.scala
rename to src/test/scala/chiselTests/interface/ParametricInterfaceSpec.scala
diff --git a/src/test/scala-2/chiselTests/interface/TappedInterfaceSpec.scala b/src/test/scala/chiselTests/interface/TappedInterfaceSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/interface/TappedInterfaceSpec.scala
rename to src/test/scala/chiselTests/interface/TappedInterfaceSpec.scala
diff --git a/src/test/scala-2/chiselTests/naming/IdentifierProposerSpec.scala b/src/test/scala/chiselTests/naming/IdentifierProposerSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/naming/IdentifierProposerSpec.scala
rename to src/test/scala/chiselTests/naming/IdentifierProposerSpec.scala
diff --git a/src/test/scala-2/chiselTests/naming/NamePluginSpec.scala b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/naming/NamePluginSpec.scala
rename to src/test/scala/chiselTests/naming/NamePluginSpec.scala
diff --git a/src/test/scala-2/chiselTests/naming/PrefixSpec.scala b/src/test/scala/chiselTests/naming/PrefixSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/naming/PrefixSpec.scala
rename to src/test/scala/chiselTests/naming/PrefixSpec.scala
diff --git a/src/test/scala-2/chiselTests/naming/TypenameSpec.scala b/src/test/scala/chiselTests/naming/TypenameSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/naming/TypenameSpec.scala
rename to src/test/scala/chiselTests/naming/TypenameSpec.scala
diff --git a/src/test/scala-2/chiselTests/properties/ClassSpec.scala b/src/test/scala/chiselTests/properties/ClassSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/properties/ClassSpec.scala
rename to src/test/scala/chiselTests/properties/ClassSpec.scala
diff --git a/src/test/scala-2/chiselTests/properties/ObjectSpec.scala b/src/test/scala/chiselTests/properties/ObjectSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/properties/ObjectSpec.scala
rename to src/test/scala/chiselTests/properties/ObjectSpec.scala
diff --git a/src/test/scala-2/chiselTests/properties/PropertySpec.scala b/src/test/scala/chiselTests/properties/PropertySpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/properties/PropertySpec.scala
rename to src/test/scala/chiselTests/properties/PropertySpec.scala
diff --git a/src/test/scala-2/chiselTests/simulator/EphemeralSimulatorSpec.scala b/src/test/scala/chiselTests/simulator/EphemeralSimulatorSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/simulator/EphemeralSimulatorSpec.scala
rename to src/test/scala/chiselTests/simulator/EphemeralSimulatorSpec.scala
diff --git a/src/test/scala-2/chiselTests/simulator/GCD.scala b/src/test/scala/chiselTests/simulator/GCD.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/simulator/GCD.scala
rename to src/test/scala/chiselTests/simulator/GCD.scala
diff --git a/src/test/scala-2/chiselTests/simulator/HasSimulatorSpec.scala b/src/test/scala/chiselTests/simulator/HasSimulatorSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/simulator/HasSimulatorSpec.scala
rename to src/test/scala/chiselTests/simulator/HasSimulatorSpec.scala
diff --git a/src/test/scala-2/chiselTests/simulator/LayerControlSpec.scala b/src/test/scala/chiselTests/simulator/LayerControlSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/simulator/LayerControlSpec.scala
rename to src/test/scala/chiselTests/simulator/LayerControlSpec.scala
diff --git a/src/test/scala-2/chiselTests/simulator/OptionalIOModule.scala b/src/test/scala/chiselTests/simulator/OptionalIOModule.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/simulator/OptionalIOModule.scala
rename to src/test/scala/chiselTests/simulator/OptionalIOModule.scala
diff --git a/src/test/scala-2/chiselTests/simulator/PeekPokeAPISpec.scala b/src/test/scala/chiselTests/simulator/PeekPokeAPISpec.scala
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rename from src/test/scala-2/chiselTests/simulator/PeekPokeAPISpec.scala
rename to src/test/scala/chiselTests/simulator/PeekPokeAPISpec.scala
diff --git a/src/test/scala-2/chiselTests/simulator/PeekPokeTestModule.scala b/src/test/scala/chiselTests/simulator/PeekPokeTestModule.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/simulator/PeekPokeTestModule.scala
rename to src/test/scala/chiselTests/simulator/PeekPokeTestModule.scala
diff --git a/src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala b/src/test/scala/chiselTests/simulator/SimulatorSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala
rename to src/test/scala/chiselTests/simulator/SimulatorSpec.scala
diff --git a/src/test/scala-2/chiselTests/simulator/scalatest/ChiselSimSpec.scala b/src/test/scala/chiselTests/simulator/scalatest/ChiselSimSpec.scala
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rename from src/test/scala-2/chiselTests/simulator/scalatest/ChiselSimSpec.scala
rename to src/test/scala/chiselTests/simulator/scalatest/ChiselSimSpec.scala
diff --git a/src/test/scala-2/chiselTests/simulator/scalatest/HasCliOptionsSpec.scala b/src/test/scala/chiselTests/simulator/scalatest/HasCliOptionsSpec.scala
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rename from src/test/scala-2/chiselTests/simulator/scalatest/HasCliOptionsSpec.scala
rename to src/test/scala/chiselTests/simulator/scalatest/HasCliOptionsSpec.scala
diff --git a/src/test/scala-2/chiselTests/stage/ChiselAnnotationsSpec.scala b/src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala
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rename from src/test/scala-2/chiselTests/stage/ChiselAnnotationsSpec.scala
rename to src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala
diff --git a/src/test/scala-2/chiselTests/stage/WarningConfigurationSpec.scala b/src/test/scala/chiselTests/stage/WarningConfigurationSpec.scala
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rename from src/test/scala-2/chiselTests/stage/WarningConfigurationSpec.scala
rename to src/test/scala/chiselTests/stage/WarningConfigurationSpec.scala
diff --git a/src/test/scala-2/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala
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rename from src/test/scala-2/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala
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diff --git a/src/test/scala-2/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala
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rename from src/test/scala-2/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala
rename to src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala
diff --git a/src/test/scala-2/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala b/src/test/scala/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala
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rename from src/test/scala-2/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala
rename to src/test/scala/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala
diff --git a/src/test/scala-2/chiselTests/stage/phases/ChecksSpec.scala b/src/test/scala/chiselTests/stage/phases/ChecksSpec.scala
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rename from src/test/scala-2/chiselTests/stage/phases/ChecksSpec.scala
rename to src/test/scala/chiselTests/stage/phases/ChecksSpec.scala
diff --git a/src/test/scala-2/chiselTests/stage/phases/ConvertSpec.scala b/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala
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rename from src/test/scala-2/chiselTests/stage/phases/ConvertSpec.scala
rename to src/test/scala/chiselTests/stage/phases/ConvertSpec.scala
diff --git a/src/test/scala-2/chiselTests/stage/phases/ElaborateSpec.scala b/src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala
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rename from src/test/scala-2/chiselTests/stage/phases/ElaborateSpec.scala
rename to src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala
diff --git a/src/test/scala-2/chiselTests/stage/phases/EmitterSpec.scala b/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala
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rename from src/test/scala-2/chiselTests/stage/phases/EmitterSpec.scala
rename to src/test/scala/chiselTests/stage/phases/EmitterSpec.scala
diff --git a/src/test/scala-2/chiselTests/testing/FileCheckSpec.scala b/src/test/scala/chiselTests/testing/FileCheckSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/testing/FileCheckSpec.scala
rename to src/test/scala/chiselTests/testing/FileCheckSpec.scala
diff --git a/src/test/scala-2/chiselTests/testing/HasTestingDirectorySpec.scala b/src/test/scala/chiselTests/testing/HasTestingDirectorySpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/testing/HasTestingDirectorySpec.scala
rename to src/test/scala/chiselTests/testing/HasTestingDirectorySpec.scala
diff --git a/src/test/scala-2/chiselTests/testing/scalatest/HasConfigMapSpec.scala b/src/test/scala/chiselTests/testing/scalatest/HasConfigMapSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/testing/scalatest/HasConfigMapSpec.scala
rename to src/test/scala/chiselTests/testing/scalatest/HasConfigMapSpec.scala
diff --git a/src/test/scala-2/chiselTests/testing/scalatest/TestingDirectorySpec.scala b/src/test/scala/chiselTests/testing/scalatest/TestingDirectorySpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/testing/scalatest/TestingDirectorySpec.scala
rename to src/test/scala/chiselTests/testing/scalatest/TestingDirectorySpec.scala
diff --git a/src/test/scala-2/chiselTests/util/AttributeAnnotationSpec.scala b/src/test/scala/chiselTests/util/AttributeAnnotationSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/AttributeAnnotationSpec.scala
rename to src/test/scala/chiselTests/util/AttributeAnnotationSpec.scala
diff --git a/src/test/scala-2/chiselTests/util/BitSetSpec.scala b/src/test/scala/chiselTests/util/BitSetSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/BitSetSpec.scala
rename to src/test/scala/chiselTests/util/BitSetSpec.scala
diff --git a/src/test/scala-2/chiselTests/util/BitwiseSpec.scala b/src/test/scala/chiselTests/util/BitwiseSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/BitwiseSpec.scala
rename to src/test/scala/chiselTests/util/BitwiseSpec.scala
diff --git a/src/test/scala-2/chiselTests/util/CatSpec.scala b/src/test/scala/chiselTests/util/CatSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/CatSpec.scala
rename to src/test/scala/chiselTests/util/CatSpec.scala
diff --git a/src/test/scala-2/chiselTests/util/PipeSpec.scala b/src/test/scala/chiselTests/util/PipeSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/PipeSpec.scala
rename to src/test/scala/chiselTests/util/PipeSpec.scala
diff --git a/src/test/scala-2/chiselTests/util/PriorityMuxSpec.scala b/src/test/scala/chiselTests/util/PriorityMuxSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/PriorityMuxSpec.scala
rename to src/test/scala/chiselTests/util/PriorityMuxSpec.scala
diff --git a/src/test/scala-2/chiselTests/util/RegSpec.scala b/src/test/scala/chiselTests/util/RegSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/RegSpec.scala
rename to src/test/scala/chiselTests/util/RegSpec.scala
diff --git a/src/test/scala-2/chiselTests/util/SRAMSpec.scala b/src/test/scala/chiselTests/util/SRAMSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/SRAMSpec.scala
rename to src/test/scala/chiselTests/util/SRAMSpec.scala
diff --git a/src/test/scala-2/chiselTests/util/circt/ClockGate.scala b/src/test/scala/chiselTests/util/circt/ClockGate.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/circt/ClockGate.scala
rename to src/test/scala/chiselTests/util/circt/ClockGate.scala
diff --git a/src/test/scala-2/chiselTests/util/circt/IsXSpec.scala b/src/test/scala/chiselTests/util/circt/IsXSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/circt/IsXSpec.scala
rename to src/test/scala/chiselTests/util/circt/IsXSpec.scala
diff --git a/src/test/scala-2/chiselTests/util/circt/PlusArgsTestSpec.scala b/src/test/scala/chiselTests/util/circt/PlusArgsTestSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/circt/PlusArgsTestSpec.scala
rename to src/test/scala/chiselTests/util/circt/PlusArgsTestSpec.scala
diff --git a/src/test/scala-2/chiselTests/util/circt/PlusArgsValueSpec.scala b/src/test/scala/chiselTests/util/circt/PlusArgsValueSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/circt/PlusArgsValueSpec.scala
rename to src/test/scala/chiselTests/util/circt/PlusArgsValueSpec.scala
diff --git a/src/test/scala-2/chiselTests/util/circt/SizeOfSpec.scala b/src/test/scala/chiselTests/util/circt/SizeOfSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/circt/SizeOfSpec.scala
rename to src/test/scala/chiselTests/util/circt/SizeOfSpec.scala
diff --git a/src/test/scala-2/chiselTests/util/circt/Synthesis.scala b/src/test/scala/chiselTests/util/circt/Synthesis.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/circt/Synthesis.scala
rename to src/test/scala/chiselTests/util/circt/Synthesis.scala
diff --git a/src/test/scala-2/chiselTests/util/experimental/DecoderTableSpec.scala b/src/test/scala/chiselTests/util/experimental/DecoderTableSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/experimental/DecoderTableSpec.scala
rename to src/test/scala/chiselTests/util/experimental/DecoderTableSpec.scala
diff --git a/src/test/scala-2/chiselTests/util/random/PRNGSpec.scala b/src/test/scala/chiselTests/util/random/PRNGSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/util/random/PRNGSpec.scala
rename to src/test/scala/chiselTests/util/random/PRNGSpec.scala
diff --git a/src/test/scala-2/circtTests/ConventionSpec.scala b/src/test/scala/circtTests/ConventionSpec.scala
similarity index 100%
rename from src/test/scala-2/circtTests/ConventionSpec.scala
rename to src/test/scala/circtTests/ConventionSpec.scala
diff --git a/src/test/scala-2/circtTests/OutputDirAnnotationSpec.scala b/src/test/scala/circtTests/OutputDirAnnotationSpec.scala
similarity index 100%
rename from src/test/scala-2/circtTests/OutputDirAnnotationSpec.scala
rename to src/test/scala/circtTests/OutputDirAnnotationSpec.scala
diff --git a/src/test/scala-2/circtTests/stage/ChiselMainSpec.scala b/src/test/scala/circtTests/stage/ChiselMainSpec.scala
similarity index 100%
rename from src/test/scala-2/circtTests/stage/ChiselMainSpec.scala
rename to src/test/scala/circtTests/stage/ChiselMainSpec.scala
diff --git a/src/test/scala-2/circtTests/stage/ChiselStageSpec.scala b/src/test/scala/circtTests/stage/ChiselStageSpec.scala
similarity index 100%
rename from src/test/scala-2/circtTests/stage/ChiselStageSpec.scala
rename to src/test/scala/circtTests/stage/ChiselStageSpec.scala
diff --git a/src/test/scala-2/circtTests/stage/phases/AddImplicitOutputFileSpec.scala b/src/test/scala/circtTests/stage/phases/AddImplicitOutputFileSpec.scala
similarity index 100%
rename from src/test/scala-2/circtTests/stage/phases/AddImplicitOutputFileSpec.scala
rename to src/test/scala/circtTests/stage/phases/AddImplicitOutputFileSpec.scala
diff --git a/src/test/scala-2/cookbook/Bundle2UInt.scala b/src/test/scala/cookbook/Bundle2UInt.scala
similarity index 100%
rename from src/test/scala-2/cookbook/Bundle2UInt.scala
rename to src/test/scala/cookbook/Bundle2UInt.scala
diff --git a/src/test/scala-2/cookbook/CookbookSpec.scala b/src/test/scala/cookbook/CookbookSpec.scala
similarity index 100%
rename from src/test/scala-2/cookbook/CookbookSpec.scala
rename to src/test/scala/cookbook/CookbookSpec.scala
diff --git a/src/test/scala-2/cookbook/FSM.scala b/src/test/scala/cookbook/FSM.scala
similarity index 100%
rename from src/test/scala-2/cookbook/FSM.scala
rename to src/test/scala/cookbook/FSM.scala
diff --git a/src/test/scala-2/cookbook/RegOfVec.scala b/src/test/scala/cookbook/RegOfVec.scala
similarity index 100%
rename from src/test/scala-2/cookbook/RegOfVec.scala
rename to src/test/scala/cookbook/RegOfVec.scala
diff --git a/src/test/scala-2/cookbook/UInt2Bundle.scala b/src/test/scala/cookbook/UInt2Bundle.scala
similarity index 100%
rename from src/test/scala-2/cookbook/UInt2Bundle.scala
rename to src/test/scala/cookbook/UInt2Bundle.scala
diff --git a/src/test/scala-2/cookbook/UInt2VecOfBool.scala b/src/test/scala/cookbook/UInt2VecOfBool.scala
similarity index 100%
rename from src/test/scala-2/cookbook/UInt2VecOfBool.scala
rename to src/test/scala/cookbook/UInt2VecOfBool.scala
diff --git a/src/test/scala-2/cookbook/VecOfBool2UInt.scala b/src/test/scala/cookbook/VecOfBool2UInt.scala
similarity index 100%
rename from src/test/scala-2/cookbook/VecOfBool2UInt.scala
rename to src/test/scala/cookbook/VecOfBool2UInt.scala
diff --git a/src/test/scala-2/examples/ImplicitStateVendingMachine.scala b/src/test/scala/examples/ImplicitStateVendingMachine.scala
similarity index 100%
rename from src/test/scala-2/examples/ImplicitStateVendingMachine.scala
rename to src/test/scala/examples/ImplicitStateVendingMachine.scala
diff --git a/src/test/scala-2/examples/SimpleVendingMachine.scala b/src/test/scala/examples/SimpleVendingMachine.scala
similarity index 100%
rename from src/test/scala-2/examples/SimpleVendingMachine.scala
rename to src/test/scala/examples/SimpleVendingMachine.scala
diff --git a/src/test/scala-2/examples/VendingMachineGenerator.scala b/src/test/scala/examples/VendingMachineGenerator.scala
similarity index 100%
rename from src/test/scala-2/examples/VendingMachineGenerator.scala
rename to src/test/scala/examples/VendingMachineGenerator.scala
diff --git a/src/test/scala-2/examples/VendingMachineUtils.scala b/src/test/scala/examples/VendingMachineUtils.scala
similarity index 100%
rename from src/test/scala-2/examples/VendingMachineUtils.scala
rename to src/test/scala/examples/VendingMachineUtils.scala

From cc858f3e2c20c1f3d4a15aa18ebd8d0f3d4e7456 Mon Sep 17 00:00:00 2001
From: Aditya Naik <aditya.naik@sifive.com>
Date: Wed, 19 Nov 2025 08:44:17 -0800
Subject: [PATCH 02/13] Remove structural types from UIntOps and SIntOps

---
 src/test/scala/chiselTests/SIntOps.scala |  4 +-
 src/test/scala/chiselTests/UIntOps.scala | 90 +++++++++++++++++-------
 2 files changed, 66 insertions(+), 28 deletions(-)

diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 02144d9fb3f..9997ed104c0 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -202,13 +202,13 @@ class SIntOpsSpec extends AnyPropSpec with Matchers with ShiftRightWidthBehavior
   }
 
   property("Static right-shift should have a minimum width of 1") {
-    testShiftRightWidthBehavior(SInt)(chiselMinWidth = 1, firrtlMinWidth = 1)
+    testSIntShiftRightWidthBehavior(chiselMinWidth = 1, firrtlMinWidth = 1)
   }
 
   property("Static right-shift should have width of 0 in Chisel and 1 in FIRRTL with --use-legacy-width") {
     val args = Array("--use-legacy-width")
 
-    testShiftRightWidthBehavior(SInt)(chiselMinWidth = 0, firrtlMinWidth = 1, args = args)
+    testSIntShiftRightWidthBehavior(chiselMinWidth = 0, firrtlMinWidth = 1, args = args)
 
     // Focused test to show the mismatch
     class TestModule extends Module {
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index e6041a41f37..f1e8490aaf6 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -214,62 +214,100 @@ class UIntLitZeroWidthTester extends Module {
 }
 
 trait ShiftRightWidthBehavior extends WidthHelpers {
-  // The UInt and SInt objects don't share a type, so make one up that they can conform to structurally
-  type BitsFactory[T <: Bits] = {
-    def apply():         T
-    def apply(w: Width): T
+  def testSIntShiftRightWidthBehavior(chiselMinWidth: Int, firrtlMinWidth: Int, args: Iterable[String] = Nil): Unit = {
+    assertKnownWidth(4, args) {
+      val in = IO(Input(SInt(8.W)))
+      in >> 4
+    }
+    assertKnownWidth(chiselMinWidth, args) {
+      val in = IO(Input(SInt(8.W)))
+      in >> 8
+    }
+    assertKnownWidth(chiselMinWidth, args) {
+      val in = IO(Input(SInt(8.W)))
+      in >> 16
+    }
+    assertKnownWidth(chiselMinWidth, args) {
+      val in = IO(Input(SInt(0.W)))
+      in >> 8
+    }
+    assertKnownWidth(chiselMinWidth, args) {
+      val in = IO(Input(SInt(0.W)))
+      in >> 0
+    }
+    assertInferredWidth(4, args) {
+      val in = IO(Input(SInt(8.W)))
+      val w = WireInit(SInt(), in)
+      w >> 4
+    }
+    assertInferredWidth(firrtlMinWidth, args) {
+      val in = IO(Input(SInt(8.W)))
+      val w = WireInit(SInt(), in)
+      w >> 8
+    }
+    assertInferredWidth(firrtlMinWidth, args) {
+      val in = IO(Input(SInt(8.W)))
+      val w = WireInit(SInt(), in)
+      w >> 16
+    }
+    assertInferredWidth(firrtlMinWidth, args) {
+      val in = IO(Input(SInt(0.W)))
+      val w = WireInit(SInt(), in)
+      w >> 8
+    }
+    assertInferredWidth(firrtlMinWidth, args) {
+      val in = IO(Input(SInt(0.W)))
+      val w = WireInit(SInt(), in)
+      w >> 0
+    }
   }
-
-  def testShiftRightWidthBehavior[T <: Bits](
-    factory: BitsFactory[T]
-  )(chiselMinWidth: Int, firrtlMinWidth: Int, args: Iterable[String] = Nil): Unit = {
+  def testUIntShiftRightWidthBehavior(chiselMinWidth: Int, firrtlMinWidth: Int, args: Iterable[String] = Nil): Unit = {
     assertKnownWidth(4, args) {
-      val in = IO(Input(factory(8.W)))
+      val in = IO(Input(UInt(8.W)))
       in >> 4
     }
     assertKnownWidth(chiselMinWidth, args) {
-      val in = IO(Input(factory(8.W)))
+      val in = IO(Input(UInt(8.W)))
       in >> 8
     }
     assertKnownWidth(chiselMinWidth, args) {
-      val in = IO(Input(factory(8.W)))
+      val in = IO(Input(UInt(8.W)))
       in >> 16
     }
     assertKnownWidth(chiselMinWidth, args) {
-      val in = IO(Input(factory(0.W)))
+      val in = IO(Input(UInt(0.W)))
       in >> 8
     }
     assertKnownWidth(chiselMinWidth, args) {
-      val in = IO(Input(factory(0.W)))
+      val in = IO(Input(UInt(0.W)))
       in >> 0
     }
     assertInferredWidth(4, args) {
-      val in = IO(Input(factory(8.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(8.W)))
+      val w = WireInit(UInt(), in)
       w >> 4
     }
     assertInferredWidth(firrtlMinWidth, args) {
-      val in = IO(Input(factory(8.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(8.W)))
+      val w = WireInit(UInt(), in)
       w >> 8
     }
     assertInferredWidth(firrtlMinWidth, args) {
-      val in = IO(Input(factory(8.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(8.W)))
+      val w = WireInit(UInt(), in)
       w >> 16
     }
     assertInferredWidth(firrtlMinWidth, args) {
-      val in = IO(Input(factory(0.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(0.W)))
+      val w = WireInit(UInt(), in)
       w >> 8
     }
     assertInferredWidth(firrtlMinWidth, args) {
-      val in = IO(Input(factory(0.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(0.W)))
+      val w = WireInit(UInt(), in)
       w >> 0
     }
   }
-
 }
 
 class UIntOpsSpec extends AnyPropSpec with Matchers with LogUtils with ShiftRightWidthBehavior with ChiselSim {
@@ -551,13 +589,13 @@ class UIntOpsSpec extends AnyPropSpec with Matchers with LogUtils with ShiftRigh
   }
 
   property("Static right-shift should have a minimum width of 0") {
-    testShiftRightWidthBehavior(UInt)(chiselMinWidth = 0, firrtlMinWidth = 0)
+    testUIntShiftRightWidthBehavior(chiselMinWidth = 0, firrtlMinWidth = 0)
   }
 
   property("Static right-shift should have width of 0 in Chisel and 1 in FIRRTL with --use-legacy-width") {
     val args = Array("--use-legacy-width")
 
-    testShiftRightWidthBehavior(UInt)(chiselMinWidth = 0, firrtlMinWidth = 1, args = args)
+    testUIntShiftRightWidthBehavior(chiselMinWidth = 0, firrtlMinWidth = 1, args = args)
 
     // Focused test to show the mismatch
     class TestModule extends Module {

From 73d4a94bf67db4dff30d6e64b927d4b47e0ee792 Mon Sep 17 00:00:00 2001
From: Aditya Naik <aditya.naik@sifive.com>
Date: Wed, 19 Nov 2025 08:45:16 -0800
Subject: [PATCH 03/13] Move back unsupported files

---
 .../chisel3/internal/IdentifierSpec.scala     |   0
 .../chiselTests/AsTypeOfTester.scala          |   0
 .../chiselTests/BundleElementsSpec.scala      |   0
 .../chiselTests/BundleLiteralSpec.scala       |   0
 .../chiselTests/ChiselEnum.scala              |   0
 .../chiselTests/CloneModuleSpec.scala         |   0
 .../chiselTests/ConnectableSpec.scala         |   0
 .../chiselTests/DPISpec.scala                 |   0
 .../chiselTests/DataEqualitySpec.scala        |   0
 .../chiselTests/DataPrint.scala               |   0
 .../chiselTests/FixedIOModuleSpec.scala       |   0
 .../{scala => scala-2}/chiselTests/Mem.scala  |   0
 .../chiselTests/MuxSpec.scala                 |   0
 .../chiselTests/ProbeSpec.scala               |   1 +
 .../chiselTests/PublicModuleSpec.scala        |   0
 .../chiselTests/RawModuleSpec.scala           |   0
 .../experimental/OpaqueTypeSpec.scala         | 265 ------------------
 17 files changed, 1 insertion(+), 265 deletions(-)
 rename src/test/{scala => scala-2}/chisel3/internal/IdentifierSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/AsTypeOfTester.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/BundleElementsSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/BundleLiteralSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/ChiselEnum.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/CloneModuleSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/ConnectableSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/DPISpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/DataEqualitySpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/DataPrint.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/FixedIOModuleSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/Mem.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/MuxSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/ProbeSpec.scala (99%)
 rename src/test/{scala => scala-2}/chiselTests/PublicModuleSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/RawModuleSpec.scala (100%)
 delete mode 100644 src/test/scala-2/chiselTests/experimental/OpaqueTypeSpec.scala

diff --git a/src/test/scala/chisel3/internal/IdentifierSpec.scala b/src/test/scala-2/chisel3/internal/IdentifierSpec.scala
similarity index 100%
rename from src/test/scala/chisel3/internal/IdentifierSpec.scala
rename to src/test/scala-2/chisel3/internal/IdentifierSpec.scala
diff --git a/src/test/scala/chiselTests/AsTypeOfTester.scala b/src/test/scala-2/chiselTests/AsTypeOfTester.scala
similarity index 100%
rename from src/test/scala/chiselTests/AsTypeOfTester.scala
rename to src/test/scala-2/chiselTests/AsTypeOfTester.scala
diff --git a/src/test/scala/chiselTests/BundleElementsSpec.scala b/src/test/scala-2/chiselTests/BundleElementsSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/BundleElementsSpec.scala
rename to src/test/scala-2/chiselTests/BundleElementsSpec.scala
diff --git a/src/test/scala/chiselTests/BundleLiteralSpec.scala b/src/test/scala-2/chiselTests/BundleLiteralSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/BundleLiteralSpec.scala
rename to src/test/scala-2/chiselTests/BundleLiteralSpec.scala
diff --git a/src/test/scala/chiselTests/ChiselEnum.scala b/src/test/scala-2/chiselTests/ChiselEnum.scala
similarity index 100%
rename from src/test/scala/chiselTests/ChiselEnum.scala
rename to src/test/scala-2/chiselTests/ChiselEnum.scala
diff --git a/src/test/scala/chiselTests/CloneModuleSpec.scala b/src/test/scala-2/chiselTests/CloneModuleSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/CloneModuleSpec.scala
rename to src/test/scala-2/chiselTests/CloneModuleSpec.scala
diff --git a/src/test/scala/chiselTests/ConnectableSpec.scala b/src/test/scala-2/chiselTests/ConnectableSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/ConnectableSpec.scala
rename to src/test/scala-2/chiselTests/ConnectableSpec.scala
diff --git a/src/test/scala/chiselTests/DPISpec.scala b/src/test/scala-2/chiselTests/DPISpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/DPISpec.scala
rename to src/test/scala-2/chiselTests/DPISpec.scala
diff --git a/src/test/scala/chiselTests/DataEqualitySpec.scala b/src/test/scala-2/chiselTests/DataEqualitySpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/DataEqualitySpec.scala
rename to src/test/scala-2/chiselTests/DataEqualitySpec.scala
diff --git a/src/test/scala/chiselTests/DataPrint.scala b/src/test/scala-2/chiselTests/DataPrint.scala
similarity index 100%
rename from src/test/scala/chiselTests/DataPrint.scala
rename to src/test/scala-2/chiselTests/DataPrint.scala
diff --git a/src/test/scala/chiselTests/FixedIOModuleSpec.scala b/src/test/scala-2/chiselTests/FixedIOModuleSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/FixedIOModuleSpec.scala
rename to src/test/scala-2/chiselTests/FixedIOModuleSpec.scala
diff --git a/src/test/scala/chiselTests/Mem.scala b/src/test/scala-2/chiselTests/Mem.scala
similarity index 100%
rename from src/test/scala/chiselTests/Mem.scala
rename to src/test/scala-2/chiselTests/Mem.scala
diff --git a/src/test/scala/chiselTests/MuxSpec.scala b/src/test/scala-2/chiselTests/MuxSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/MuxSpec.scala
rename to src/test/scala-2/chiselTests/MuxSpec.scala
diff --git a/src/test/scala/chiselTests/ProbeSpec.scala b/src/test/scala-2/chiselTests/ProbeSpec.scala
similarity index 99%
rename from src/test/scala/chiselTests/ProbeSpec.scala
rename to src/test/scala-2/chiselTests/ProbeSpec.scala
index 6cae1e4c893..e1c289da75f 100644
--- a/src/test/scala/chiselTests/ProbeSpec.scala
+++ b/src/test/scala-2/chiselTests/ProbeSpec.scala
@@ -12,6 +12,7 @@ import chisel3.testing.scalatest.FileCheck
 import circt.stage.ChiselStage
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
+import scala.reflect.Selectable.reflectiveSelectable
 
 class ProbeSpec extends AnyFlatSpec with Matchers with FileCheck with ChiselSim {
   // Strip SourceInfos and split into lines
diff --git a/src/test/scala/chiselTests/PublicModuleSpec.scala b/src/test/scala-2/chiselTests/PublicModuleSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/PublicModuleSpec.scala
rename to src/test/scala-2/chiselTests/PublicModuleSpec.scala
diff --git a/src/test/scala/chiselTests/RawModuleSpec.scala b/src/test/scala-2/chiselTests/RawModuleSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/RawModuleSpec.scala
rename to src/test/scala-2/chiselTests/RawModuleSpec.scala
diff --git a/src/test/scala-2/chiselTests/experimental/OpaqueTypeSpec.scala b/src/test/scala-2/chiselTests/experimental/OpaqueTypeSpec.scala
deleted file mode 100644
index d1279f2260e..00000000000
--- a/src/test/scala-2/chiselTests/experimental/OpaqueTypeSpec.scala
+++ /dev/null
@@ -1,265 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests
-package experimental
-
-import chisel3._
-import chisel3.util.Valid
-import chisel3.experimental.OpaqueType
-import chisel3.reflect.DataMirror
-import circt.stage.ChiselStage
-import org.scalatest.flatspec.AnyFlatSpec
-import org.scalatest.matchers.should.Matchers
-import scala.collection.immutable.SeqMap
-
-object OpaqueTypeSpec {
-
-  class SingleElementRecord extends Record with OpaqueType {
-    private val underlying = UInt(8.W)
-    val elements = SeqMap("" -> underlying)
-
-    def +(that: SingleElementRecord): SingleElementRecord = {
-      val _w = Wire(new SingleElementRecord)
-      _w.underlying := this.underlying + that.underlying
-      _w
-    }
-  }
-
-  class SingleElementRecordModule extends Module {
-    val in1 = IO(Input(new SingleElementRecord))
-    val in2 = IO(Input(new SingleElementRecord))
-    val out = IO(Output(new SingleElementRecord))
-
-    val r = new SingleElementRecord
-
-    out := in1 + in2
-  }
-
-  class InnerRecord extends Record with OpaqueType {
-    val k = new InnerInnerRecord
-    val elements = SeqMap("" -> k)
-  }
-
-  class InnerInnerRecord extends Record with OpaqueType {
-    val k = new SingleElementRecord
-    val elements = SeqMap("" -> k)
-  }
-
-  class NestedRecordModule extends Module {
-    val in = IO(Input(new InnerRecord))
-    val out = IO(Output(new InnerRecord))
-    val inst = Module(new InnerModule)
-    inst.io.foo := in
-    out := inst.io.bar
-  }
-
-  class InnerModule extends Module {
-    val io = IO(new Bundle {
-      val foo = Input(new InnerRecord)
-      val bar = Output(new InnerRecord)
-    })
-
-    // DO NOT do this; just for testing element connections
-    io.bar.elements.head._2 := io.foo.elements.head._2
-  }
-
-  class NamedSingleElementRecord extends Record with OpaqueType {
-    private val underlying = UInt(8.W)
-    val elements = SeqMap("unused" -> underlying)
-  }
-
-  class NamedSingleElementModule extends Module {
-    val in = IO(Input(new NamedSingleElementRecord))
-    val out = IO(Output(new NamedSingleElementRecord))
-    out := in
-  }
-
-  class ErroneousOverride extends Record with OpaqueType {
-    private val underlyingA = UInt(8.W)
-    private val underlyingB = UInt(8.W)
-    val elements = SeqMap("x" -> underlyingA, "y" -> underlyingB)
-
-    override def opaqueType = true
-  }
-
-  class ErroneousOverrideModule extends Module {
-    val in = IO(Input(new ErroneousOverride))
-    val out = IO(Output(new ErroneousOverride))
-    out := in
-  }
-
-  class NotActuallyOpaqueType extends Record with OpaqueType {
-    private val underlyingA = UInt(8.W)
-    private val underlyingB = UInt(8.W)
-    val elements = SeqMap("x" -> underlyingA, "y" -> underlyingB)
-
-    override def opaqueType = false
-  }
-
-  class NotActuallyOpaqueTypeModule extends Module {
-    val in = IO(Input(new NotActuallyOpaqueType))
-    val out = IO(Output(new NotActuallyOpaqueType))
-    out := in
-  }
-
-  // Illustrate how to dyanmically decide between OpaqueType or not
-  sealed trait MaybeBoxed[T <: Data] extends Record {
-    def underlying: T
-    def boxed:      Boolean
-  }
-  object MaybeBoxed {
-    def apply[T <: Data](gen: T, boxed: Boolean): MaybeBoxed[T] = {
-      if (boxed) new Boxed(gen) else new Unboxed(gen)
-    }
-  }
-  class Boxed[T <: Data](gen: T) extends MaybeBoxed[T] {
-    def boxed = true
-    lazy val elements = SeqMap("underlying" -> gen)
-    def underlying = elements.head._2
-  }
-  class Unboxed[T <: Data](gen: T) extends MaybeBoxed[T] with OpaqueType {
-    def boxed = false
-    lazy val elements = SeqMap("" -> gen)
-    def underlying = elements.head._2
-  }
-
-  class MaybeNoAsUInt(noAsUInt: Boolean) extends Record with OpaqueType {
-    lazy val elements = SeqMap("" -> UInt(8.W))
-    override protected def errorOnAsUInt = noAsUInt
-  }
-}
-
-class OpaqueTypeSpec extends AnyFlatSpec with Matchers {
-  import OpaqueTypeSpec._
-
-  behavior.of("OpaqueTypes")
-
-  they should "support OpaqueType for maps with single unnamed elements" in {
-    val singleElementChirrtl = ChiselStage.emitCHIRRTL { new SingleElementRecordModule }
-    singleElementChirrtl should include("input in1 : UInt<8>")
-    singleElementChirrtl should include("input in2 : UInt<8>")
-    singleElementChirrtl should include("add(in1, in2)")
-  }
-
-  they should "work correctly for toTarget in nested OpaqueType Records" in {
-    var mod: NestedRecordModule = null
-    ChiselStage.emitCHIRRTL { mod = new NestedRecordModule; mod }
-    val testStrings = Seq(
-      mod.inst.io.foo.toTarget.serialize,
-      mod.inst.io.foo.k.toTarget.serialize,
-      mod.inst.io.foo.k.k.toTarget.serialize,
-      mod.inst.io.foo.elements.head._2.toTarget.serialize,
-      mod.inst.io.foo.k.elements.head._2.toTarget.serialize,
-      mod.inst.io.foo.k.k.elements.head._2.toTarget.serialize
-    )
-    testStrings.foreach(x => assert(x == "~|InnerModule>io.foo"))
-  }
-
-  they should "work correctly with DataMirror in nested OpaqueType Records" in {
-    var mod: NestedRecordModule = null
-    ChiselStage.emitCHIRRTL { mod = new NestedRecordModule; mod }
-    val ports = DataMirror.fullModulePorts(mod.inst)
-    val expectedPorts = Seq(
-      ("clock", mod.inst.clock),
-      ("reset", mod.inst.reset),
-      ("io", mod.inst.io),
-      ("io_bar", mod.inst.io.bar),
-      ("io_bar", mod.inst.io.bar.k),
-      ("io_bar", mod.inst.io.bar.k.k),
-      ("io_bar", mod.inst.io.bar.k.k.elements.head._2),
-      ("io_foo", mod.inst.io.foo),
-      ("io_foo", mod.inst.io.foo.k),
-      ("io_foo", mod.inst.io.foo.k.k),
-      ("io_foo", mod.inst.io.foo.k.k.elements.head._2)
-    )
-    ports shouldBe expectedPorts
-  }
-
-  they should "work correctly when connecting nested OpaqueType elements" in {
-    val nestedRecordChirrtl = ChiselStage.emitCHIRRTL { new NestedRecordModule }
-    nestedRecordChirrtl should include("input in : UInt<8>")
-    nestedRecordChirrtl should include("output out : UInt<8>")
-    nestedRecordChirrtl should include("connect inst.io.foo, in")
-    nestedRecordChirrtl should include("connect out, inst.io.bar")
-    nestedRecordChirrtl should include("output io : { flip foo : UInt<8>, bar : UInt<8>}")
-    nestedRecordChirrtl should include("connect io.bar, io.foo")
-  }
-
-  they should "throw an error when map contains a named element and OpaqueType is mixed in" in {
-    (the[Exception] thrownBy {
-      ChiselStage.emitCHIRRTL { new NamedSingleElementModule }
-    }).getMessage should include("Opaque types must have exactly one element with an empty name")
-  }
-
-  they should "throw an error when map contains more than one element and OpaqueType is mixed in" in {
-    (the[Exception] thrownBy {
-      ChiselStage.emitCHIRRTL { new ErroneousOverrideModule }
-    }).getMessage should include("Opaque types must have exactly one element with an empty name")
-  }
-
-  they should "work correctly when an OpaqueType overrides the def as false" in {
-    val chirrtl = ChiselStage.emitCHIRRTL(new NotActuallyOpaqueTypeModule)
-    chirrtl should include("input in : { y : UInt<8>, x : UInt<8>}")
-    chirrtl should include("output out : { y : UInt<8>, x : UInt<8>}")
-    chirrtl should include("connect out, in")
-  }
-
-  they should "support conditional OpaqueTypes via traits and factory methods" in {
-    class MyModule extends Module {
-      val in0 = IO(Input(MaybeBoxed(UInt(8.W), true)))
-      val out0 = IO(Output(MaybeBoxed(UInt(8.W), true)))
-      val in1 = IO(Input(MaybeBoxed(UInt(8.W), false)))
-      val out1 = IO(Output(MaybeBoxed(UInt(8.W), false)))
-      out0 := in0
-      out1 := in1
-    }
-    val chirrtl = ChiselStage.emitCHIRRTL(new MyModule)
-    chirrtl should include("input in0 : { underlying : UInt<8>}")
-    chirrtl should include("input in1 : UInt<8>")
-  }
-
-  they should "work with .toTarget" in {
-    var m: SingleElementRecordModule = null
-    ChiselStage.emitCHIRRTL { m = new SingleElementRecordModule; m }
-    val q = m.in1.toTarget.toString
-    assert(q == "~|SingleElementRecordModule>in1")
-  }
-
-  they should "NOT work with .toTarget on non-data OpaqueType Record" in {
-    var m: SingleElementRecordModule = null
-    ChiselStage.emitCHIRRTL { m = new SingleElementRecordModule; m }
-    a[ChiselException] shouldBe thrownBy { m.r.toTarget }
-  }
-
-  they should "support making .asUInt illegal" in {
-    class AsUIntTester(gen: Data) extends RawModule {
-      val in = IO(Input(gen))
-      val out = IO(Output(UInt()))
-      out :#= in.asUInt
-    }
-    // First check that it works when it should
-    val chirrtl = ChiselStage.emitCHIRRTL(new AsUIntTester(new MaybeNoAsUInt(false)))
-    chirrtl should include("connect out, in")
-
-    val e = the[ChiselException] thrownBy {
-      ChiselStage.emitCHIRRTL(new AsUIntTester(new MaybeNoAsUInt(true)), Array("--throw-on-first-error"))
-    }
-    e.getMessage should include("MaybeNoAsUInt does not support .asUInt.")
-  }
-
-  they should "support give a decent error for .asUInt nested in an Aggregate" in {
-    class AsUIntTester(gen: Data) extends RawModule {
-      val in = IO(Input(Valid(gen)))
-      val out = IO(Output(UInt()))
-      out :#= in.asUInt
-    }
-    // First check that it works when it should
-    val chirrtl = ChiselStage.emitCHIRRTL(new AsUIntTester(new MaybeNoAsUInt(false)))
-    chirrtl should include("cat(in.valid, in.bits)")
-
-    val e1 = the[ChiselException] thrownBy {
-      ChiselStage.emitCHIRRTL(new AsUIntTester(new MaybeNoAsUInt(true)), Array("--throw-on-first-error"))
-    }
-    e1.getMessage should include("Field '_.bits' of type MaybeNoAsUInt does not support .asUInt.")
-  }
-}

From f6c4de6c86a9f5229d7a2eced42b36cc96779254 Mon Sep 17 00:00:00 2001
From: Aditya Naik <aditya.naik@sifive.com>
Date: Wed, 19 Nov 2025 12:24:31 -0800
Subject: [PATCH 04/13] Move back unsupported files

---
 .../chiselTests/VecLiteralSpec.scala          |   0
 .../chiselTests/WarningSpec.scala             |   0
 .../chiselTests/aop/SelectSpec.scala          |   0
 .../chiselTests/interface/Drivers.scala       |   2 +-
 .../chiselTests/interface/InterfaceSpec.scala |   0
 .../interface/ParametricInterfaceSpec.scala   |   0
 .../interface/TappedInterfaceSpec.scala       |   0
 .../chiselTests/properties/ClassSpec.scala    |   0
 .../chiselTests/properties/ObjectSpec.scala   |   0
 .../chiselTests/properties/PropertySpec.scala |   0
 .../simulator/EphemeralSimulatorSpec.scala    |   0
 .../chiselTests/simulator/GCD.scala           |   0
 .../simulator/HasSimulatorSpec.scala          |   0
 .../simulator/LayerControlSpec.scala          |   0
 .../simulator/OptionalIOModule.scala          |   0
 .../simulator/PeekPokeAPISpec.scala           |   0
 .../simulator/PeekPokeTestModule.scala        |   0
 .../chiselTests/simulator/SimulatorSpec.scala |   2 +-
 .../simulator/scalatest/ChiselSimSpec.scala   |   0
 .../scalatest/HasCliOptionsSpec.scala         |   0
 .../chiselTests}/stage/ChiselStageSpec.scala  |   4 +-
 .../stage/WarningConfigurationSpec.scala      |   0
 .../scalatest/TestingDirectorySpec.scala      |   0
 .../chiselTests/util/SRAMSpec.scala           |   0
 .../{scala => scala-2}/cookbook/FSM.scala     |   0
 .../experimental/OpaqueTypeSpec.scala         | 265 ++++++++++++++++++
 26 files changed, 269 insertions(+), 4 deletions(-)
 rename src/test/{scala => scala-2}/chiselTests/VecLiteralSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/WarningSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/aop/SelectSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/interface/Drivers.scala (98%)
 rename src/test/{scala => scala-2}/chiselTests/interface/InterfaceSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/interface/ParametricInterfaceSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/interface/TappedInterfaceSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/properties/ClassSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/properties/ObjectSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/properties/PropertySpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/simulator/EphemeralSimulatorSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/simulator/GCD.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/simulator/HasSimulatorSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/simulator/LayerControlSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/simulator/OptionalIOModule.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/simulator/PeekPokeAPISpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/simulator/PeekPokeTestModule.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/simulator/SimulatorSpec.scala (99%)
 rename src/test/{scala => scala-2}/chiselTests/simulator/scalatest/ChiselSimSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/simulator/scalatest/HasCliOptionsSpec.scala (100%)
 rename src/test/{scala/circtTests => scala-2/chiselTests}/stage/ChiselStageSpec.scala (99%)
 rename src/test/{scala => scala-2}/chiselTests/stage/WarningConfigurationSpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/testing/scalatest/TestingDirectorySpec.scala (100%)
 rename src/test/{scala => scala-2}/chiselTests/util/SRAMSpec.scala (100%)
 rename src/test/{scala => scala-2}/cookbook/FSM.scala (100%)
 create mode 100644 src/test/scala/chiselTests/experimental/OpaqueTypeSpec.scala

diff --git a/src/test/scala/chiselTests/VecLiteralSpec.scala b/src/test/scala-2/chiselTests/VecLiteralSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/VecLiteralSpec.scala
rename to src/test/scala-2/chiselTests/VecLiteralSpec.scala
diff --git a/src/test/scala/chiselTests/WarningSpec.scala b/src/test/scala-2/chiselTests/WarningSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/WarningSpec.scala
rename to src/test/scala-2/chiselTests/WarningSpec.scala
diff --git a/src/test/scala/chiselTests/aop/SelectSpec.scala b/src/test/scala-2/chiselTests/aop/SelectSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/aop/SelectSpec.scala
rename to src/test/scala-2/chiselTests/aop/SelectSpec.scala
diff --git a/src/test/scala/chiselTests/interface/Drivers.scala b/src/test/scala-2/chiselTests/interface/Drivers.scala
similarity index 98%
rename from src/test/scala/chiselTests/interface/Drivers.scala
rename to src/test/scala-2/chiselTests/interface/Drivers.scala
index 138b8aca04b..67fbcc24c2d 100644
--- a/src/test/scala/chiselTests/interface/Drivers.scala
+++ b/src/test/scala-2/chiselTests/interface/Drivers.scala
@@ -5,7 +5,7 @@ import java.io.File
 import chisel3.RawModule
 import chisel3.stage.ChiselGeneratorAnnotation
 import circt.stage.{ChiselStage, FirtoolOption}
-import firrtl.AnnotationSeq
+import firrtl.{AnnotationSeq, seqToAnnoSeq}
 import firrtl.options.{StageError, StageUtils}
 import sys.process._
 
diff --git a/src/test/scala/chiselTests/interface/InterfaceSpec.scala b/src/test/scala-2/chiselTests/interface/InterfaceSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/interface/InterfaceSpec.scala
rename to src/test/scala-2/chiselTests/interface/InterfaceSpec.scala
diff --git a/src/test/scala/chiselTests/interface/ParametricInterfaceSpec.scala b/src/test/scala-2/chiselTests/interface/ParametricInterfaceSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/interface/ParametricInterfaceSpec.scala
rename to src/test/scala-2/chiselTests/interface/ParametricInterfaceSpec.scala
diff --git a/src/test/scala/chiselTests/interface/TappedInterfaceSpec.scala b/src/test/scala-2/chiselTests/interface/TappedInterfaceSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/interface/TappedInterfaceSpec.scala
rename to src/test/scala-2/chiselTests/interface/TappedInterfaceSpec.scala
diff --git a/src/test/scala/chiselTests/properties/ClassSpec.scala b/src/test/scala-2/chiselTests/properties/ClassSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/properties/ClassSpec.scala
rename to src/test/scala-2/chiselTests/properties/ClassSpec.scala
diff --git a/src/test/scala/chiselTests/properties/ObjectSpec.scala b/src/test/scala-2/chiselTests/properties/ObjectSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/properties/ObjectSpec.scala
rename to src/test/scala-2/chiselTests/properties/ObjectSpec.scala
diff --git a/src/test/scala/chiselTests/properties/PropertySpec.scala b/src/test/scala-2/chiselTests/properties/PropertySpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/properties/PropertySpec.scala
rename to src/test/scala-2/chiselTests/properties/PropertySpec.scala
diff --git a/src/test/scala/chiselTests/simulator/EphemeralSimulatorSpec.scala b/src/test/scala-2/chiselTests/simulator/EphemeralSimulatorSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/simulator/EphemeralSimulatorSpec.scala
rename to src/test/scala-2/chiselTests/simulator/EphemeralSimulatorSpec.scala
diff --git a/src/test/scala/chiselTests/simulator/GCD.scala b/src/test/scala-2/chiselTests/simulator/GCD.scala
similarity index 100%
rename from src/test/scala/chiselTests/simulator/GCD.scala
rename to src/test/scala-2/chiselTests/simulator/GCD.scala
diff --git a/src/test/scala/chiselTests/simulator/HasSimulatorSpec.scala b/src/test/scala-2/chiselTests/simulator/HasSimulatorSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/simulator/HasSimulatorSpec.scala
rename to src/test/scala-2/chiselTests/simulator/HasSimulatorSpec.scala
diff --git a/src/test/scala/chiselTests/simulator/LayerControlSpec.scala b/src/test/scala-2/chiselTests/simulator/LayerControlSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/simulator/LayerControlSpec.scala
rename to src/test/scala-2/chiselTests/simulator/LayerControlSpec.scala
diff --git a/src/test/scala/chiselTests/simulator/OptionalIOModule.scala b/src/test/scala-2/chiselTests/simulator/OptionalIOModule.scala
similarity index 100%
rename from src/test/scala/chiselTests/simulator/OptionalIOModule.scala
rename to src/test/scala-2/chiselTests/simulator/OptionalIOModule.scala
diff --git a/src/test/scala/chiselTests/simulator/PeekPokeAPISpec.scala b/src/test/scala-2/chiselTests/simulator/PeekPokeAPISpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/simulator/PeekPokeAPISpec.scala
rename to src/test/scala-2/chiselTests/simulator/PeekPokeAPISpec.scala
diff --git a/src/test/scala/chiselTests/simulator/PeekPokeTestModule.scala b/src/test/scala-2/chiselTests/simulator/PeekPokeTestModule.scala
similarity index 100%
rename from src/test/scala/chiselTests/simulator/PeekPokeTestModule.scala
rename to src/test/scala-2/chiselTests/simulator/PeekPokeTestModule.scala
diff --git a/src/test/scala/chiselTests/simulator/SimulatorSpec.scala b/src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala
similarity index 99%
rename from src/test/scala/chiselTests/simulator/SimulatorSpec.scala
rename to src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala
index f4f0d78e66f..04f7041a0f2 100644
--- a/src/test/scala/chiselTests/simulator/SimulatorSpec.scala
+++ b/src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala
@@ -7,7 +7,7 @@ import chisel3.simulator._
 import chisel3.util.{HasExtModuleInline, HasExtModulePath, HasExtModuleResource}
 import org.scalatest.funspec.AnyFunSpec
 import org.scalatest.matchers.must.Matchers
-import org.scalatest.matchers.should.Matchers.convertToAnyShouldWrapper
+// import org.scalatest.matchers.should.Matchers.convertToStringShouldWrapperForVerb
 import svsim._
 
 class VerilatorSimulator(val workspacePath: String) extends Simulator[verilator.Backend] {
diff --git a/src/test/scala/chiselTests/simulator/scalatest/ChiselSimSpec.scala b/src/test/scala-2/chiselTests/simulator/scalatest/ChiselSimSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/simulator/scalatest/ChiselSimSpec.scala
rename to src/test/scala-2/chiselTests/simulator/scalatest/ChiselSimSpec.scala
diff --git a/src/test/scala/chiselTests/simulator/scalatest/HasCliOptionsSpec.scala b/src/test/scala-2/chiselTests/simulator/scalatest/HasCliOptionsSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/simulator/scalatest/HasCliOptionsSpec.scala
rename to src/test/scala-2/chiselTests/simulator/scalatest/HasCliOptionsSpec.scala
diff --git a/src/test/scala/circtTests/stage/ChiselStageSpec.scala b/src/test/scala-2/chiselTests/stage/ChiselStageSpec.scala
similarity index 99%
rename from src/test/scala/circtTests/stage/ChiselStageSpec.scala
rename to src/test/scala-2/chiselTests/stage/ChiselStageSpec.scala
index d4c11b88454..df7e690cf9b 100644
--- a/src/test/scala/circtTests/stage/ChiselStageSpec.scala
+++ b/src/test/scala-2/chiselTests/stage/ChiselStageSpec.scala
@@ -123,12 +123,12 @@ object ChiselStageSpec {
   }
 
   class RecoverableErrorFakeSourceInfo extends RawModule {
-    implicit val info = SourceLine("Foo", 3, 10)
+    implicit val info: SourceLine = SourceLine("Foo", 3, 10)
     3.U >> -1
   }
 
   class ErrorCaughtByFirtool extends RawModule {
-    implicit val info = SourceLine("Foo", 3, 10)
+    implicit val info: SourceLine = SourceLine("Foo", 3, 10)
     val w = Wire(UInt(8.W))
   }
 
diff --git a/src/test/scala/chiselTests/stage/WarningConfigurationSpec.scala b/src/test/scala-2/chiselTests/stage/WarningConfigurationSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/stage/WarningConfigurationSpec.scala
rename to src/test/scala-2/chiselTests/stage/WarningConfigurationSpec.scala
diff --git a/src/test/scala/chiselTests/testing/scalatest/TestingDirectorySpec.scala b/src/test/scala-2/chiselTests/testing/scalatest/TestingDirectorySpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/testing/scalatest/TestingDirectorySpec.scala
rename to src/test/scala-2/chiselTests/testing/scalatest/TestingDirectorySpec.scala
diff --git a/src/test/scala/chiselTests/util/SRAMSpec.scala b/src/test/scala-2/chiselTests/util/SRAMSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/util/SRAMSpec.scala
rename to src/test/scala-2/chiselTests/util/SRAMSpec.scala
diff --git a/src/test/scala/cookbook/FSM.scala b/src/test/scala-2/cookbook/FSM.scala
similarity index 100%
rename from src/test/scala/cookbook/FSM.scala
rename to src/test/scala-2/cookbook/FSM.scala
diff --git a/src/test/scala/chiselTests/experimental/OpaqueTypeSpec.scala b/src/test/scala/chiselTests/experimental/OpaqueTypeSpec.scala
new file mode 100644
index 00000000000..3a9c01311c0
--- /dev/null
+++ b/src/test/scala/chiselTests/experimental/OpaqueTypeSpec.scala
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests
+package experimental
+
+import chisel3._
+import chisel3.util.Valid
+import chisel3.experimental.OpaqueType
+import chisel3.reflect.DataMirror
+import circt.stage.ChiselStage
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
+import scala.collection.immutable.SeqMap
+
+object OpaqueTypeSpec {
+
+  class SingleElementRecord extends Record with OpaqueType {
+    private val underlying = UInt(8.W)
+    val elements = SeqMap("" -> underlying)
+
+    def +(that: SingleElementRecord): SingleElementRecord = {
+      val _w = Wire(new SingleElementRecord)
+      _w.underlying := this.underlying + that.underlying
+      _w
+    }
+  }
+
+  class SingleElementRecordModule extends Module {
+    val in1 = IO(Input(new SingleElementRecord))
+    val in2 = IO(Input(new SingleElementRecord))
+    val out = IO(Output(new SingleElementRecord))
+
+    val r = new SingleElementRecord
+
+    out := in1 + in2
+  }
+
+  class InnerRecord extends Record with OpaqueType {
+    val k = new InnerInnerRecord
+    val elements = SeqMap("" -> k)
+  }
+
+  class InnerInnerRecord extends Record with OpaqueType {
+    val k = new SingleElementRecord
+    val elements = SeqMap("" -> k)
+  }
+
+  class NestedRecordModule extends Module {
+    val in = IO(Input(new InnerRecord))
+    val out = IO(Output(new InnerRecord))
+    val inst = Module(new InnerModule)
+    inst.io.foo := in
+    out := inst.io.bar
+  }
+
+  class InnerModule extends Module {
+    val io = IO(new Bundle {
+      val foo = Input(new InnerRecord)
+      val bar = Output(new InnerRecord)
+    })
+
+    // DO NOT do this; just for testing element connections
+    io.bar.elements.head._2 := io.foo.elements.head._2
+  }
+
+  class NamedSingleElementRecord extends Record with OpaqueType {
+    private val underlying = UInt(8.W)
+    val elements = SeqMap("unused" -> underlying)
+  }
+
+  class NamedSingleElementModule extends Module {
+    val in = IO(Input(new NamedSingleElementRecord))
+    val out = IO(Output(new NamedSingleElementRecord))
+    out := in
+  }
+
+  class ErroneousOverride extends Record with OpaqueType {
+    private val underlyingA = UInt(8.W)
+    private val underlyingB = UInt(8.W)
+    val elements = SeqMap("x" -> underlyingA, "y" -> underlyingB)
+
+    override def opaqueType = true
+  }
+
+  class ErroneousOverrideModule extends Module {
+    val in = IO(Input(new ErroneousOverride))
+    val out = IO(Output(new ErroneousOverride))
+    out := in
+  }
+
+  class NotActuallyOpaqueType extends Record with OpaqueType {
+    private val underlyingA = UInt(8.W)
+    private val underlyingB = UInt(8.W)
+    val elements = SeqMap("x" -> underlyingA, "y" -> underlyingB)
+
+    override def opaqueType = false
+  }
+
+  class NotActuallyOpaqueTypeModule extends Module {
+    val in = IO(Input(new NotActuallyOpaqueType))
+    val out = IO(Output(new NotActuallyOpaqueType))
+    out := in
+  }
+
+  // Illustrate how to dyanmically decide between OpaqueType or not
+  sealed trait MaybeBoxed[T <: Data] extends Record {
+    def underlying: T
+    def boxed:      Boolean
+  }
+  object MaybeBoxed {
+    def apply[T <: Data](gen: T, boxed: Boolean): MaybeBoxed[T] = {
+      if (boxed) new Boxed(gen) else new Unboxed(gen)
+    }
+  }
+  class Boxed[T <: Data](gen: T) extends MaybeBoxed[T] {
+    def boxed = true
+    lazy val elements = SeqMap("underlying" -> gen)
+    def underlying = elements.head._2.asInstanceOf[T]
+  }
+  class Unboxed[T <: Data](gen: T) extends MaybeBoxed[T] with OpaqueType {
+    def boxed = false
+    lazy val elements = SeqMap("" -> gen)
+    def underlying = elements.head._2.asInstanceOf[T]
+  }
+
+  class MaybeNoAsUInt(noAsUInt: Boolean) extends Record with OpaqueType {
+    lazy val elements = SeqMap("" -> UInt(8.W))
+    override protected def errorOnAsUInt = noAsUInt
+  }
+}
+
+class OpaqueTypeSpec extends AnyFlatSpec with Matchers {
+  import OpaqueTypeSpec._
+
+  behavior.of("OpaqueTypes")
+
+  they should "support OpaqueType for maps with single unnamed elements" in {
+    val singleElementChirrtl = ChiselStage.emitCHIRRTL { new SingleElementRecordModule }
+    singleElementChirrtl should include("input in1 : UInt<8>")
+    singleElementChirrtl should include("input in2 : UInt<8>")
+    singleElementChirrtl should include("add(in1, in2)")
+  }
+
+  they should "work correctly for toTarget in nested OpaqueType Records" in {
+    var mod: NestedRecordModule = null
+    ChiselStage.emitCHIRRTL { mod = new NestedRecordModule; mod }
+    val testStrings = Seq(
+      mod.inst.io.foo.toTarget.serialize,
+      mod.inst.io.foo.k.toTarget.serialize,
+      mod.inst.io.foo.k.k.toTarget.serialize,
+      mod.inst.io.foo.elements.head._2.toTarget.serialize,
+      mod.inst.io.foo.k.elements.head._2.toTarget.serialize,
+      mod.inst.io.foo.k.k.elements.head._2.toTarget.serialize
+    )
+    testStrings.foreach(x => assert(x == "~|InnerModule>io.foo"))
+  }
+
+  they should "work correctly with DataMirror in nested OpaqueType Records" in {
+    var mod: NestedRecordModule = null
+    ChiselStage.emitCHIRRTL { mod = new NestedRecordModule; mod }
+    val ports = DataMirror.fullModulePorts(mod.inst)
+    val expectedPorts = Seq(
+      ("clock", mod.inst.clock),
+      ("reset", mod.inst.reset),
+      ("io", mod.inst.io),
+      ("io_bar", mod.inst.io.bar),
+      ("io_bar", mod.inst.io.bar.k),
+      ("io_bar", mod.inst.io.bar.k.k),
+      ("io_bar", mod.inst.io.bar.k.k.elements.head._2),
+      ("io_foo", mod.inst.io.foo),
+      ("io_foo", mod.inst.io.foo.k),
+      ("io_foo", mod.inst.io.foo.k.k),
+      ("io_foo", mod.inst.io.foo.k.k.elements.head._2)
+    )
+    ports shouldBe expectedPorts
+  }
+
+  they should "work correctly when connecting nested OpaqueType elements" in {
+    val nestedRecordChirrtl = ChiselStage.emitCHIRRTL { new NestedRecordModule }
+    nestedRecordChirrtl should include("input in : UInt<8>")
+    nestedRecordChirrtl should include("output out : UInt<8>")
+    nestedRecordChirrtl should include("connect inst.io.foo, in")
+    nestedRecordChirrtl should include("connect out, inst.io.bar")
+    nestedRecordChirrtl should include("output io : { flip foo : UInt<8>, bar : UInt<8>}")
+    nestedRecordChirrtl should include("connect io.bar, io.foo")
+  }
+
+  they should "throw an error when map contains a named element and OpaqueType is mixed in" in {
+    (the[Exception] thrownBy {
+      ChiselStage.emitCHIRRTL { new NamedSingleElementModule }
+    }).getMessage should include("Opaque types must have exactly one element with an empty name")
+  }
+
+  they should "throw an error when map contains more than one element and OpaqueType is mixed in" in {
+    (the[Exception] thrownBy {
+      ChiselStage.emitCHIRRTL { new ErroneousOverrideModule }
+    }).getMessage should include("Opaque types must have exactly one element with an empty name")
+  }
+
+  they should "work correctly when an OpaqueType overrides the def as false" in {
+    val chirrtl = ChiselStage.emitCHIRRTL(new NotActuallyOpaqueTypeModule)
+    chirrtl should include("input in : { y : UInt<8>, x : UInt<8>}")
+    chirrtl should include("output out : { y : UInt<8>, x : UInt<8>}")
+    chirrtl should include("connect out, in")
+  }
+
+  they should "support conditional OpaqueTypes via traits and factory methods" in {
+    class MyModule extends Module {
+      val in0 = IO(Input(MaybeBoxed(UInt(8.W), true)))
+      val out0 = IO(Output(MaybeBoxed(UInt(8.W), true)))
+      val in1 = IO(Input(MaybeBoxed(UInt(8.W), false)))
+      val out1 = IO(Output(MaybeBoxed(UInt(8.W), false)))
+      out0 := in0
+      out1 := in1
+    }
+    val chirrtl = ChiselStage.emitCHIRRTL(new MyModule)
+    chirrtl should include("input in0 : { underlying : UInt<8>}")
+    chirrtl should include("input in1 : UInt<8>")
+  }
+
+  they should "work with .toTarget" in {
+    var m: SingleElementRecordModule = null
+    ChiselStage.emitCHIRRTL { m = new SingleElementRecordModule; m }
+    val q = m.in1.toTarget.toString
+    assert(q == "~|SingleElementRecordModule>in1")
+  }
+
+  they should "NOT work with .toTarget on non-data OpaqueType Record" in {
+    var m: SingleElementRecordModule = null
+    ChiselStage.emitCHIRRTL { m = new SingleElementRecordModule; m }
+    a[ChiselException] shouldBe thrownBy { m.r.toTarget }
+  }
+
+  they should "support making .asUInt illegal" in {
+    class AsUIntTester(gen: Data) extends RawModule {
+      val in = IO(Input(gen))
+      val out = IO(Output(UInt()))
+      out :#= in.asUInt
+    }
+    // First check that it works when it should
+    val chirrtl = ChiselStage.emitCHIRRTL(new AsUIntTester(new MaybeNoAsUInt(false)))
+    chirrtl should include("connect out, in")
+
+    val e = the[ChiselException] thrownBy {
+      ChiselStage.emitCHIRRTL(new AsUIntTester(new MaybeNoAsUInt(true)), Array("--throw-on-first-error"))
+    }
+    e.getMessage should include("MaybeNoAsUInt does not support .asUInt.")
+  }
+
+  they should "support give a decent error for .asUInt nested in an Aggregate" in {
+    class AsUIntTester(gen: Data) extends RawModule {
+      val in = IO(Input(Valid(gen)))
+      val out = IO(Output(UInt()))
+      out :#= in.asUInt
+    }
+    // First check that it works when it should
+    val chirrtl = ChiselStage.emitCHIRRTL(new AsUIntTester(new MaybeNoAsUInt(false)))
+    chirrtl should include("cat(in.valid, in.bits)")
+
+    val e1 = the[ChiselException] thrownBy {
+      ChiselStage.emitCHIRRTL(new AsUIntTester(new MaybeNoAsUInt(true)), Array("--throw-on-first-error"))
+    }
+    e1.getMessage should include("Field '_.bits' of type MaybeNoAsUInt does not support .asUInt.")
+  }
+}

From 7565069f05439cf4ceca6ca3ed12b2211fa96658 Mon Sep 17 00:00:00 2001
From: Aditya Naik <aditya.naik@sifive.com>
Date: Wed, 19 Nov 2025 14:57:43 -0800
Subject: [PATCH 05/13] Move BoringUtilsSpec to scala-2

---
 src/test/{scala => scala-2}/chiselTests/BoringUtilsSpec.scala | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename src/test/{scala => scala-2}/chiselTests/BoringUtilsSpec.scala (100%)

diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala-2/chiselTests/BoringUtilsSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/BoringUtilsSpec.scala
rename to src/test/scala-2/chiselTests/BoringUtilsSpec.scala

From 9fd5dd3cb59242b82adc20e65f36b09e26064165 Mon Sep 17 00:00:00 2001
From: Aditya Naik <aditya.naik@sifive.com>
Date: Mon, 24 Nov 2025 16:12:22 -0800
Subject: [PATCH 06/13] Add and update files

---
 src/test/scala/chiselTests/AutoNestedCloneSpec.scala     | 9 ++++++++-
 src/test/scala/chiselTests/BlackBox.scala                | 4 ++--
 src/test/scala/chiselTests/BoolSpec.scala                | 1 +
 src/test/scala/chiselTests/BulkConnectSpec.scala         | 3 ++-
 src/test/scala/chiselTests/ClockSpec.scala               | 1 +
 src/test/scala/chiselTests/Decoder.scala                 | 2 +-
 src/test/scala/chiselTests/ExtModule.scala               | 1 +
 src/test/scala/chiselTests/IntrinsicSpec.scala           | 1 +
 src/test/scala/chiselTests/LiteralToTargetSpec.scala     | 9 ++++-----
 src/test/scala/chiselTests/LogUtils.scala                | 1 +
 src/test/scala/chiselTests/ModuleChoiceSpec.scala        | 5 +++--
 src/test/scala/chiselTests/ModuleSpec.scala              | 2 ++
 src/test/scala/chiselTests/SimLogSpec.scala              | 2 +-
 src/test/scala/chiselTests/Vec.scala                     | 2 ++
 src/test/scala/chiselTests/naming/NamePluginSpec.scala   | 1 -
 src/test/scala/chiselTests/naming/PrefixSpec.scala       | 1 -
 .../scala/chiselTests/stage/ChiselAnnotationsSpec.scala  | 1 +
 .../phases/AddImplicitOutputAnnotationFileSpec.scala     | 2 +-
 .../stage/phases/AddImplicitOutputFileSpec.scala         | 2 +-
 .../stage/phases/AddSerializationAnnotationsSpec.scala   | 2 +-
 src/test/scala/chiselTests/stage/phases/ChecksSpec.scala | 2 +-
 .../scala/chiselTests/stage/phases/ConvertSpec.scala     | 2 +-
 .../scala/chiselTests/stage/phases/ElaborateSpec.scala   | 1 +
 .../scala/chiselTests/stage/phases/EmitterSpec.scala     | 3 ++-
 .../chiselTests/testing/HasTestingDirectorySpec.scala    | 2 +-
 src/test/scala/circtTests/OutputDirAnnotationSpec.scala  | 2 +-
 .../stage/phases/AddImplicitOutputFileSpec.scala         | 1 +
 27 files changed, 42 insertions(+), 23 deletions(-)

diff --git a/src/test/scala/chiselTests/AutoNestedCloneSpec.scala b/src/test/scala/chiselTests/AutoNestedCloneSpec.scala
index b69abfc2d8f..75fcd2359d2 100644
--- a/src/test/scala/chiselTests/AutoNestedCloneSpec.scala
+++ b/src/test/scala/chiselTests/AutoNestedCloneSpec.scala
@@ -126,12 +126,19 @@ class AutoNestedCloneSpec extends AnyFlatSpec with Matchers {
         val foo = new Bundle {
           val x = Input(Vec(n, gen))
         }
-        val bar = Output(Option(new { def mkBundle = new Bundle { val x = Vec(n, gen) } }).get.mkBundle)
+        trait HasMkBundle { def mkBundle: Bundle }
+
+        val mk: HasMkBundle =
+          new HasMkBundle {
+            def mkBundle: Bundle = new Bundle { val x = Vec(n, gen) }
+          }
+        val bar = Output(mk.mkBundle)
       }
       val io = IO(new MyBundle(4, UInt(8.W)))
       val myWire = WireInit(io.foo)
       val myWire2 = WireInit(io.bar)
       io.bar.x := io.foo.x
+
     })
   }
 }
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 38886dd9852..114bd3493ce 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -401,7 +401,7 @@ class BlackBoxSpec extends AnyFlatSpec with Matchers with ChiselSim with FileChe
     class Bar extends BlackBox {
       final val io = IO {
         new Bundle {
-          val a = Output(probe.Probe(Bool(), layers.Verification))
+          val a = Output(probe.Probe(Bool(), chisel3.layers.Verification))
         }
       }
     }
@@ -411,7 +411,7 @@ class BlackBoxSpec extends AnyFlatSpec with Matchers with ChiselSim with FileChe
     class Baz extends BlackBox(knownLayers = Seq(A)) {
       final val io = IO {
         new Bundle {
-          val a = Output(probe.Probe(Bool(), layers.Verification))
+          val a = Output(probe.Probe(Bool(), chisel3.layers.Verification))
         }
       }
     }
diff --git a/src/test/scala/chiselTests/BoolSpec.scala b/src/test/scala/chiselTests/BoolSpec.scala
index 4294ef5b6a9..721e59a9356 100644
--- a/src/test/scala/chiselTests/BoolSpec.scala
+++ b/src/test/scala/chiselTests/BoolSpec.scala
@@ -6,6 +6,7 @@ import chisel3._
 import chisel3.simulator.scalatest.ChiselSim
 import chisel3.simulator.stimulus.RunUntilFinished
 import org.scalatest.flatspec.AnyFlatSpec
+import scala.reflect.Selectable.reflectiveSelectable
 
 class BoolSpec extends AnyFlatSpec with ChiselSim {
 
diff --git a/src/test/scala/chiselTests/BulkConnectSpec.scala b/src/test/scala/chiselTests/BulkConnectSpec.scala
index adbd49217e0..3188968f932 100644
--- a/src/test/scala/chiselTests/BulkConnectSpec.scala
+++ b/src/test/scala/chiselTests/BulkConnectSpec.scala
@@ -5,6 +5,7 @@ import chisel3.util.Decoupled
 import circt.stage.ChiselStage
 import org.scalatest.matchers.should.Matchers
 import org.scalatest.propspec.AnyPropSpec
+import scala.reflect.Selectable.reflectiveSelectable
 
 class BulkConnectSpec extends AnyPropSpec with Matchers {
   property("Chisel connects should emit FIRRTL bulk connects when possible") {
@@ -73,7 +74,7 @@ class BulkConnectSpec extends AnyPropSpec with Matchers {
     val chirrtl = ChiselStage.emitCHIRRTL(new Module {
       val io: MyBundle = IO(Flipped(new MyBundle))
 
-      val bb = Module(new BlackBox {
+      val bb = Module[BlackBox { def io: MyBundle }](new BlackBox {
         val io: MyBundle = IO(Flipped(new MyBundle))
       })
 
diff --git a/src/test/scala/chiselTests/ClockSpec.scala b/src/test/scala/chiselTests/ClockSpec.scala
index ae54c51d7ea..2a40a01a1b6 100644
--- a/src/test/scala/chiselTests/ClockSpec.scala
+++ b/src/test/scala/chiselTests/ClockSpec.scala
@@ -8,6 +8,7 @@ import chisel3.simulator.stimulus.RunUntilFinished
 import circt.stage.ChiselStage
 import org.scalatest.propspec.AnyPropSpec
 import org.scalatest.matchers.should.Matchers
+import scala.reflect.Selectable.reflectiveSelectable
 
 class ClockAsUIntTester extends Module {
   assert(true.B.asClock.asUInt === 1.U)
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index 48870cc9851..95ed8d27805 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -14,7 +14,7 @@ class Decoder(bitpats: List[String]) extends Module {
     val inst = Input(UInt(32.W))
     val matched = Output(Bool())
   })
-  io.matched := VecInit(bitpats.map(BitPat(_) === io.inst)).reduce(_ || _)
+  io.matched := VecInit(bitpats.map(BitPat(_) === io.inst).reduce(_ || _))
 }
 
 class DecoderTester(pairs: List[(String, String)]) extends Module {
diff --git a/src/test/scala/chiselTests/ExtModule.scala b/src/test/scala/chiselTests/ExtModule.scala
index 2b55a36e474..8a689adc83b 100644
--- a/src/test/scala/chiselTests/ExtModule.scala
+++ b/src/test/scala/chiselTests/ExtModule.scala
@@ -11,6 +11,7 @@ import chisel3.util.HasExtModuleResource
 import circt.stage.ChiselStage
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
+import scala.reflect.Selectable.reflectiveSelectable
 
 // Avoid collisions with regular BlackBox tests by putting ExtModule blackboxes
 // in their own scope.
diff --git a/src/test/scala/chiselTests/IntrinsicSpec.scala b/src/test/scala/chiselTests/IntrinsicSpec.scala
index 172679e3ffa..61c50cb7b26 100644
--- a/src/test/scala/chiselTests/IntrinsicSpec.scala
+++ b/src/test/scala/chiselTests/IntrinsicSpec.scala
@@ -4,6 +4,7 @@ package chiselTests
 
 import chisel3._
 import circt.stage.ChiselStage
+import chisel3.experimental.{fromIntToIntParam, fromStringToStringParam}
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 
diff --git a/src/test/scala/chiselTests/LiteralToTargetSpec.scala b/src/test/scala/chiselTests/LiteralToTargetSpec.scala
index d27270bdda0..9c65450a059 100644
--- a/src/test/scala/chiselTests/LiteralToTargetSpec.scala
+++ b/src/test/scala/chiselTests/LiteralToTargetSpec.scala
@@ -8,11 +8,8 @@ import org.scalatest.freespec.AnyFreeSpec
 import org.scalatest.matchers.should.Matchers
 
 class LiteralToTargetSpec extends AnyFreeSpec with Matchers {
-
   "Literal Data should fail to be converted to ReferenceTarget" in {
-
-    (the[ChiselException] thrownBy {
-
+    val ex = the[ChiselException] thrownBy {
       class Bar extends RawModule {
         val a = 1.U
       }
@@ -23,6 +20,8 @@ class LiteralToTargetSpec extends AnyFreeSpec with Matchers {
       }
 
       ChiselStage.emitCHIRRTL(new Foo)
-    } should have).message("Illegal component name: UInt<1>(0h1) (note: literals are illegal)")
+    }
+
+    ex.getMessage shouldBe "Illegal component name: UInt<1>(0h1) (note: literals are illegal)"
   }
 }
diff --git a/src/test/scala/chiselTests/LogUtils.scala b/src/test/scala/chiselTests/LogUtils.scala
index 9d0eb86cfc7..e87f475c1ae 100644
--- a/src/test/scala/chiselTests/LogUtils.scala
+++ b/src/test/scala/chiselTests/LogUtils.scala
@@ -4,6 +4,7 @@ package chiselTests
 
 import java.io.{ByteArrayOutputStream, PrintStream}
 import logger.{LogLevel, LogLevelAnnotation, Logger}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 
 trait LogUtils {
 
diff --git a/src/test/scala/chiselTests/ModuleChoiceSpec.scala b/src/test/scala/chiselTests/ModuleChoiceSpec.scala
index 438c91c4ac5..1456176aa65 100644
--- a/src/test/scala/chiselTests/ModuleChoiceSpec.scala
+++ b/src/test/scala/chiselTests/ModuleChoiceSpec.scala
@@ -9,6 +9,7 @@ import chisel3.testing.scalatest.FileCheck
 import circt.stage.ChiselStage
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
+import scala.reflect.Selectable.reflectiveSelectable
 
 object Platform extends Group {
   object FPGA extends Case
@@ -34,8 +35,8 @@ class ModuleWithChoice[T <: Data](
   default: => FixedIOBaseModule[T]
 )(alternateImpls: Seq[(Case, () => FixedIOBaseModule[T])])
     extends Module {
-  val inst = ModuleChoice(default)(alternateImpls)
-  val io = IO(inst.cloneType)
+  val inst: T = ModuleChoice[T](default, alternateImpls)
+  val io: T = IO(chiselTypeOf(inst))
   io <> inst
 }
 
diff --git a/src/test/scala/chiselTests/ModuleSpec.scala b/src/test/scala/chiselTests/ModuleSpec.scala
index 79de51146c5..477ecd4bd83 100644
--- a/src/test/scala/chiselTests/ModuleSpec.scala
+++ b/src/test/scala/chiselTests/ModuleSpec.scala
@@ -9,9 +9,11 @@ import chisel3.stage.ChiselGeneratorAnnotation
 import circt.stage.{CIRCTTarget, CIRCTTargetAnnotation, ChiselStage, FirtoolOption}
 import firrtl.annotations.NoTargetAnnotation
 import firrtl.options.{TargetDirAnnotation, Unserializable}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import org.scalatest.matchers.should.Matchers
 import org.scalatest.propspec.AnyPropSpec
 import scala.io.Source
+import scala.reflect.Selectable.reflectiveSelectable
 
 class SimpleIO extends Bundle {
   val in = Input(UInt(32.W))
diff --git a/src/test/scala/chiselTests/SimLogSpec.scala b/src/test/scala/chiselTests/SimLogSpec.scala
index d3c6aa6745d..b6424cdd2ed 100644
--- a/src/test/scala/chiselTests/SimLogSpec.scala
+++ b/src/test/scala/chiselTests/SimLogSpec.scala
@@ -33,7 +33,7 @@ class SimLogSpec extends AnyFlatSpec with Matchers with FileCheck with ChiselSim
     class MyModule extends Module {
       val in = IO(Input(UInt(8.W)))
       val fd = SimLog.file("logfile.log")
-      fd.printf("in = %d\n", in)
+      // fd.printf("in = %d\n", in)
     }
     ChiselStage
       .emitCHIRRTL(new MyModule)
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 3bd6f619e69..e250e539b52 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -326,6 +326,8 @@ class VecSpec extends AnyPropSpec with Matchers with LogUtils with FileCheck {
       }
       require(bundleWithZeroEntryVec.getWidth == 1)
 
+      import scala.reflect.Selectable.reflectiveSelectable
+
       val m = Module(new Module {
         val io = IO(Output(bundleWithZeroEntryVec))
         val zero = WireInit(0.U.asTypeOf(bundleWithZeroEntryVec))
diff --git a/src/test/scala/chiselTests/naming/NamePluginSpec.scala b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
index 5e3d138adb8..427b9b2fc1c 100644
--- a/src/test/scala/chiselTests/naming/NamePluginSpec.scala
+++ b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
@@ -3,7 +3,6 @@
 package chiselTests.naming
 
 import chisel3._
-import chisel3.aop.Select
 import chisel3.experimental.prefix
 import chisel3.experimental.AffectsChiselName
 import chisel3.testing.scalatest.FileCheck
diff --git a/src/test/scala/chiselTests/naming/PrefixSpec.scala b/src/test/scala/chiselTests/naming/PrefixSpec.scala
index a84afb9e280..024731a0f26 100644
--- a/src/test/scala/chiselTests/naming/PrefixSpec.scala
+++ b/src/test/scala/chiselTests/naming/PrefixSpec.scala
@@ -3,7 +3,6 @@
 package chiselTests.naming
 
 import chisel3._
-import chisel3.aop.Select
 import chisel3.experimental.{noPrefix, prefix, skipPrefix, AffectsChiselPrefix}
 import chisel3.testing.scalatest.FileCheck
 import circt.stage.ChiselStage
diff --git a/src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala b/src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala
index c601f51ffef..092fd02b84b 100644
--- a/src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala
+++ b/src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala
@@ -8,6 +8,7 @@ import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation, Design
 import firrtl.options.OptionsException
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 
 class ChiselAnnotationsSpecFoo extends RawModule {
   val in = IO(Input(Bool()))
diff --git a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala
index faf411ed427..303d04a53e8 100644
--- a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala
@@ -6,7 +6,7 @@ import chisel3.RawModule
 import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.stage.phases.{AddImplicitOutputAnnotationFile, Elaborate}
 
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, AnnotationSeq, seqToAnnoSeq}
 import firrtl.options.{OutputAnnotationFileAnnotation, Phase}
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
diff --git a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala
index 20274e7af42..622231d07a0 100644
--- a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala
@@ -6,7 +6,7 @@ import chisel3.RawModule
 import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOutputFileAnnotation}
 import chisel3.stage.phases.{AddImplicitOutputFile, Elaborate}
 
-import firrtl.AnnotationSeq
+import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
 import firrtl.options.{Phase, StageOptions, TargetDirAnnotation}
 import firrtl.options.Viewer.view
 import org.scalatest.flatspec.AnyFlatSpec
diff --git a/src/test/scala/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala b/src/test/scala/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala
index 82c708c0eb6..c076f07b057 100644
--- a/src/test/scala/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala
@@ -7,7 +7,7 @@ import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOutputFileAnnotation, Cir
 import chisel3.stage.CircuitSerializationAnnotation._
 import chisel3.stage.phases.{AddImplicitOutputFile, AddSerializationAnnotations, Elaborate}
 
-import firrtl.AnnotationSeq
+import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
 import firrtl.options.{Dependency, Phase, PhaseManager, TargetDirAnnotation}
 import firrtl.options.Viewer.view
 import org.scalatest.flatspec.AnyFlatSpec
diff --git a/src/test/scala/chiselTests/stage/phases/ChecksSpec.scala b/src/test/scala/chiselTests/stage/phases/ChecksSpec.scala
index eb647a75bda..4c7fb0b6302 100644
--- a/src/test/scala/chiselTests/stage/phases/ChecksSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/ChecksSpec.scala
@@ -5,7 +5,7 @@ package chiselTests.stage.phases
 import chisel3.stage.{ChiselOutputFileAnnotation, PrintFullStackTraceAnnotation}
 import chisel3.stage.phases.Checks
 
-import firrtl.AnnotationSeq
+import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
 import firrtl.annotations.NoTargetAnnotation
 import firrtl.options.{OptionsException, Phase}
 import org.scalatest.flatspec.AnyFlatSpec
diff --git a/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala b/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala
index 0372c6fdabe..8b3327aee0f 100644
--- a/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala
@@ -6,7 +6,7 @@ import chisel3._
 import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.stage.phases.{Convert, Elaborate}
 
-import firrtl.AnnotationSeq
+import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
 import firrtl.annotations.{Annotation, NoTargetAnnotation}
 import firrtl.options.Phase
 import firrtl.stage.FirrtlCircuitAnnotation
diff --git a/src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala b/src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala
index 78812bba506..102de40f637 100644
--- a/src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala
@@ -7,6 +7,7 @@ import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation}
 import chisel3.stage.phases.Elaborate
 
 import firrtl.options.Phase
+import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 
diff --git a/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala b/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala
index ed9964ad99d..90b5cf36f81 100644
--- a/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala
@@ -6,7 +6,8 @@ import chisel3.RawModule
 import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation, ChiselOutputFileAnnotation}
 import chisel3.stage.phases.{Convert, Elaborate, Emitter}
 
-import firrtl.{AnnotationSeq, EmittedFirrtlCircuitAnnotation}
+import firrtl.EmittedFirrtlCircuitAnnotation
+import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
 import firrtl.options.{Phase, TargetDirAnnotation}
 
 import java.io.File
diff --git a/src/test/scala/chiselTests/testing/HasTestingDirectorySpec.scala b/src/test/scala/chiselTests/testing/HasTestingDirectorySpec.scala
index 6a1aaef6867..9e3feb5b206 100644
--- a/src/test/scala/chiselTests/testing/HasTestingDirectorySpec.scala
+++ b/src/test/scala/chiselTests/testing/HasTestingDirectorySpec.scala
@@ -68,7 +68,7 @@ class HasTestingDirectorySpec extends AnyFlatSpec with Matchers {
       testingDirectory.getDirectory
     }
 
-    implicit val bar = implicitly[HasTestingDirectory]
+    implicit val bar: HasTestingDirectory = implicitly[HasTestingDirectory]
 
     foo should be(foo)
 
diff --git a/src/test/scala/circtTests/OutputDirAnnotationSpec.scala b/src/test/scala/circtTests/OutputDirAnnotationSpec.scala
index b26a6372471..61e5b71c97c 100644
--- a/src/test/scala/circtTests/OutputDirAnnotationSpec.scala
+++ b/src/test/scala/circtTests/OutputDirAnnotationSpec.scala
@@ -7,7 +7,7 @@ import circt.outputDir
 import circt.stage.ChiselStage
 import org.scalatest.funspec.AnyFunSpec
 import org.scalatest.matchers.should.Matchers
-import chiselTests.experimental.hierarchy.Utils
+// import chiselTests.experimental.hierarchy.Utils
 
 class OutputDirAnnotationSpec extends AnyFunSpec with Matchers {
   describe("output directory annotation works") {
diff --git a/src/test/scala/circtTests/stage/phases/AddImplicitOutputFileSpec.scala b/src/test/scala/circtTests/stage/phases/AddImplicitOutputFileSpec.scala
index ce8b76d739b..c980dfdd2b8 100644
--- a/src/test/scala/circtTests/stage/phases/AddImplicitOutputFileSpec.scala
+++ b/src/test/scala/circtTests/stage/phases/AddImplicitOutputFileSpec.scala
@@ -5,6 +5,7 @@ package circtTests.stage.phases
 import firrtl.ir
 import firrtl.options.Phase
 import firrtl.stage.{FirrtlCircuitAnnotation, OutputFileAnnotation}
+import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
 import circt.stage.phases.AddImplicitOutputFile
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers

From 58c7d6c3c3870165e927fb3d095577dbd9b0db3e Mon Sep 17 00:00:00 2001
From: Aditya Naik <aditya.naik@sifive.com>
Date: Mon, 24 Nov 2025 23:53:16 -0800
Subject: [PATCH 07/13] Scalafmt

---
 .../chiselTests/interface/Drivers.scala       |   2 +-
 .../chisel3/stage/ChiselOptionsViewSpec.scala |   2 +-
 src/test/scala/chisel3/util/BitPatSpec.scala  | 264 +++++++++---------
 .../chiselTests/AutoNestedCloneSpec.scala     | 258 ++++++++---------
 .../scala/chiselTests/ModuleChoiceSpec.scala  |   2 +-
 .../AddImplicitOutputAnnotationFileSpec.scala |   2 +-
 .../phases/AddImplicitOutputFileSpec.scala    |   2 +-
 .../AddSerializationAnnotationsSpec.scala     |   2 +-
 .../chiselTests/stage/phases/ChecksSpec.scala |   2 +-
 .../stage/phases/ConvertSpec.scala            |   2 +-
 .../stage/phases/ElaborateSpec.scala          |   2 +-
 .../stage/phases/EmitterSpec.scala            |   2 +-
 .../phases/AddImplicitOutputFileSpec.scala    |   2 +-
 13 files changed, 272 insertions(+), 272 deletions(-)

diff --git a/src/test/scala-2/chiselTests/interface/Drivers.scala b/src/test/scala-2/chiselTests/interface/Drivers.scala
index 67fbcc24c2d..44682db1691 100644
--- a/src/test/scala-2/chiselTests/interface/Drivers.scala
+++ b/src/test/scala-2/chiselTests/interface/Drivers.scala
@@ -5,7 +5,7 @@ import java.io.File
 import chisel3.RawModule
 import chisel3.stage.ChiselGeneratorAnnotation
 import circt.stage.{ChiselStage, FirtoolOption}
-import firrtl.{AnnotationSeq, seqToAnnoSeq}
+import firrtl.{seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{StageError, StageUtils}
 import sys.process._
 
diff --git a/src/test/scala/chisel3/stage/ChiselOptionsViewSpec.scala b/src/test/scala/chisel3/stage/ChiselOptionsViewSpec.scala
index e0b07c2cab6..0145adfaea1 100644
--- a/src/test/scala/chisel3/stage/ChiselOptionsViewSpec.scala
+++ b/src/test/scala/chisel3/stage/ChiselOptionsViewSpec.scala
@@ -3,7 +3,7 @@
 package chisel3.stage
 
 import firrtl.options.Viewer.view
-import firrtl.{RenameMap, seqToAnnoSeq}
+import firrtl.{seqToAnnoSeq, RenameMap}
 
 import chisel3.ElaboratedCircuit
 import chisel3.stage._
diff --git a/src/test/scala/chisel3/util/BitPatSpec.scala b/src/test/scala/chisel3/util/BitPatSpec.scala
index 3b1d58a6164..b5287337999 100644
--- a/src/test/scala/chisel3/util/BitPatSpec.scala
+++ b/src/test/scala/chisel3/util/BitPatSpec.scala
@@ -1,132 +1,132 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chisel3.util
-
-import chisel3._
-import chisel3.util.BitPat
-import _root_.circt.stage.ChiselStage
-import org.scalatest.flatspec.AnyFlatSpec
-import org.scalatest.matchers.should.Matchers
-
-object EnumExample extends ChiselEnum {
-  val VAL1, VAL2, VAL3 = Value
-}
-
-class BitPatSpec extends AnyFlatSpec with Matchers {
-  behavior.of(classOf[BitPat].toString)
-
-  it should "convert a BitPat to readable form" in {
-    val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
-    BitPat("b" + testPattern).toString should be(s"BitPat($testPattern)")
-  }
-
-  it should "convert a BitPat to raw form" in {
-    val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
-    BitPat("b" + testPattern).rawString should be(testPattern)
-  }
-
-  it should "not fail if BitPat width is 0" in {
-    intercept[IllegalArgumentException] { BitPat("b") }
-  }
-
-  it should "concat BitPat via ##" in {
-    (BitPat.Y(4) ## BitPat.dontCare(3) ## BitPat.N(2)).toString should be(s"BitPat(1111???00)")
-  }
-
-  it should "throw when BitPat apply to a Hardware" in {
-    intercept[java.lang.IllegalArgumentException] {
-      ChiselStage.emitCHIRRTL(new chisel3.Module {
-        BitPat(chisel3.Reg(chisel3.Bool()))
-      })
-    }
-  }
-
-  it should "index and return new BitPat" in {
-    val b = BitPat("b1001???")
-    b(0) should be(BitPat.dontCare(1))
-    b(6) should be(BitPat.Y())
-    b(5) should be(BitPat.N())
-  }
-
-  it should "slice and return new BitPat" in {
-    val b = BitPat("b1001???")
-    b(2, 0) should be(BitPat("b???"))
-    b(4, 3) should be(BitPat("b01"))
-    b(6, 6) should be(BitPat("b1"))
-  }
-
-  it should "parse UInt literals correctly" in {
-    BitPat(0.U) should be(new BitPat(0, 1, 1))
-    // Note that this parses as 1-bit width, there are other APIs that don't support zero-width UInts correctly
-    BitPat(0.U(0.W)) should be(new BitPat(0, 1, 1))
-    BitPat(1.U) should be(new BitPat(1, 1, 1))
-    BitPat(2.U) should be(new BitPat(2, 3, 2))
-    BitPat(0xdeadbeefL.U) should be(new BitPat(BigInt("deadbeef", 16), BigInt("ffffffff", 16), 32))
-  }
-
-  it should "support .hasDontCares" in {
-    BitPat("b?").hasDontCares should be(true)
-    BitPat("b??").hasDontCares should be(true)
-    BitPat("b0?").hasDontCares should be(true)
-    BitPat("b?1").hasDontCares should be(true)
-    BitPat("b0").hasDontCares should be(false)
-    BitPat("b10").hasDontCares should be(false)
-    BitPat("b01").hasDontCares should be(false)
-    BitPat(0xdeadbeefL.U).hasDontCares should be(false)
-    // Zero-width not supported yet
-    intercept[IllegalArgumentException] { BitPat("b").hasDontCares should be(false) }
-  }
-
-  it should "support .allZeros" in {
-    BitPat("b?").allZeros should be(false)
-    BitPat("b??").allZeros should be(false)
-    BitPat("b0?").allZeros should be(false)
-    BitPat("b?1").allZeros should be(false)
-    BitPat("b0").allZeros should be(true)
-    BitPat("b10").allZeros should be(false)
-    BitPat("b01").allZeros should be(false)
-    BitPat(0.U(128.W)).allZeros should be(true)
-    BitPat.N(23).allZeros should be(true)
-    BitPat(0xdeadbeefL.U).allZeros should be(false)
-    // Zero-width not supported yet
-    intercept[IllegalArgumentException] { BitPat("b").allZeros should be(true) }
-  }
-
-  it should "support .allOnes" in {
-    BitPat("b?").allOnes should be(false)
-    BitPat("b??").allOnes should be(false)
-    BitPat("b0?").allOnes should be(false)
-    BitPat("b?1").allOnes should be(false)
-    BitPat("b0").allOnes should be(false)
-    BitPat("b10").allOnes should be(false)
-    BitPat("b01").allOnes should be(false)
-    BitPat("b1").allOnes should be(true)
-    BitPat("b" + ("1" * 128)).allOnes should be(true)
-    BitPat.Y(23).allOnes should be(true)
-    BitPat(0xdeadbeefL.U).allOnes should be(false)
-    // Zero-width not supported yet
-    intercept[IllegalArgumentException] { BitPat("b").allOnes should be(true) }
-  }
-
-  it should "support .allDontCares" in {
-    BitPat("b?").allDontCares should be(true)
-    BitPat("b??").allDontCares should be(true)
-    BitPat("b0?").allDontCares should be(false)
-    BitPat("b?1").allDontCares should be(false)
-    BitPat("b0").allDontCares should be(false)
-    BitPat("b10").allDontCares should be(false)
-    BitPat("b1").allDontCares should be(false)
-    BitPat("b" + ("1" * 128)).allDontCares should be(false)
-    BitPat.dontCare(23).allDontCares should be(true)
-    BitPat(0xdeadbeefL.U).allDontCares should be(false)
-    // Zero-width not supported yet
-    intercept[IllegalArgumentException] { BitPat("b").allDontCares should be(true) }
-  }
-
-  it should "convert to BitPat from ChiselEnum" in {
-    val b = BitPat(EnumExample.VAL1)
-    val c = BitPat(EnumExample.VAL3)
-    b should be(BitPat("b00"))
-    c should be(BitPat("b10"))
-  }
-}
+// // SPDX-License-Identifier: Apache-2.0
+
+// package chisel3.util
+
+// import chisel3._
+// import chisel3.util.BitPat
+// import _root_.circt.stage.ChiselStage
+// import org.scalatest.flatspec.AnyFlatSpec
+// import org.scalatest.matchers.should.Matchers
+
+// object EnumExample extends ChiselEnum {
+//   val VAL1, VAL2, VAL3 = Value
+// }
+
+// class BitPatSpec extends AnyFlatSpec with Matchers {
+//   behavior.of(classOf[BitPat].toString)
+
+//   it should "convert a BitPat to readable form" in {
+//     val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
+//     BitPat("b" + testPattern).toString should be(s"BitPat($testPattern)")
+//   }
+
+//   it should "convert a BitPat to raw form" in {
+//     val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
+//     BitPat("b" + testPattern).rawString should be(testPattern)
+//   }
+
+//   it should "not fail if BitPat width is 0" in {
+//     intercept[IllegalArgumentException] { BitPat("b") }
+//   }
+
+//   it should "concat BitPat via ##" in {
+//     (BitPat.Y(4) ## BitPat.dontCare(3) ## BitPat.N(2)).toString should be(s"BitPat(1111???00)")
+//   }
+
+//   it should "throw when BitPat apply to a Hardware" in {
+//     intercept[java.lang.IllegalArgumentException] {
+//       ChiselStage.emitCHIRRTL(new chisel3.Module {
+//         BitPat(chisel3.Reg(chisel3.Bool()))
+//       })
+//     }
+//   }
+
+//   it should "index and return new BitPat" in {
+//     val b = BitPat("b1001???")
+//     b(0) should be(BitPat.dontCare(1))
+//     b(6) should be(BitPat.Y())
+//     b(5) should be(BitPat.N())
+//   }
+
+//   it should "slice and return new BitPat" in {
+//     val b = BitPat("b1001???")
+//     b(2, 0) should be(BitPat("b???"))
+//     b(4, 3) should be(BitPat("b01"))
+//     b(6, 6) should be(BitPat("b1"))
+//   }
+
+//   it should "parse UInt literals correctly" in {
+//     BitPat(0.U) should be(new BitPat(0, 1, 1))
+//     // Note that this parses as 1-bit width, there are other APIs that don't support zero-width UInts correctly
+//     BitPat(0.U(0.W)) should be(new BitPat(0, 1, 1))
+//     BitPat(1.U) should be(new BitPat(1, 1, 1))
+//     BitPat(2.U) should be(new BitPat(2, 3, 2))
+//     BitPat(0xdeadbeefL.U) should be(new BitPat(BigInt("deadbeef", 16), BigInt("ffffffff", 16), 32))
+//   }
+
+//   it should "support .hasDontCares" in {
+//     BitPat("b?").hasDontCares should be(true)
+//     BitPat("b??").hasDontCares should be(true)
+//     BitPat("b0?").hasDontCares should be(true)
+//     BitPat("b?1").hasDontCares should be(true)
+//     BitPat("b0").hasDontCares should be(false)
+//     BitPat("b10").hasDontCares should be(false)
+//     BitPat("b01").hasDontCares should be(false)
+//     BitPat(0xdeadbeefL.U).hasDontCares should be(false)
+//     // Zero-width not supported yet
+//     intercept[IllegalArgumentException] { BitPat("b").hasDontCares should be(false) }
+//   }
+
+//   it should "support .allZeros" in {
+//     BitPat("b?").allZeros should be(false)
+//     BitPat("b??").allZeros should be(false)
+//     BitPat("b0?").allZeros should be(false)
+//     BitPat("b?1").allZeros should be(false)
+//     BitPat("b0").allZeros should be(true)
+//     BitPat("b10").allZeros should be(false)
+//     BitPat("b01").allZeros should be(false)
+//     BitPat(0.U(128.W)).allZeros should be(true)
+//     BitPat.N(23).allZeros should be(true)
+//     BitPat(0xdeadbeefL.U).allZeros should be(false)
+//     // Zero-width not supported yet
+//     intercept[IllegalArgumentException] { BitPat("b").allZeros should be(true) }
+//   }
+
+//   it should "support .allOnes" in {
+//     BitPat("b?").allOnes should be(false)
+//     BitPat("b??").allOnes should be(false)
+//     BitPat("b0?").allOnes should be(false)
+//     BitPat("b?1").allOnes should be(false)
+//     BitPat("b0").allOnes should be(false)
+//     BitPat("b10").allOnes should be(false)
+//     BitPat("b01").allOnes should be(false)
+//     BitPat("b1").allOnes should be(true)
+//     BitPat("b" + ("1" * 128)).allOnes should be(true)
+//     BitPat.Y(23).allOnes should be(true)
+//     BitPat(0xdeadbeefL.U).allOnes should be(false)
+//     // Zero-width not supported yet
+//     intercept[IllegalArgumentException] { BitPat("b").allOnes should be(true) }
+//   }
+
+//   it should "support .allDontCares" in {
+//     BitPat("b?").allDontCares should be(true)
+//     BitPat("b??").allDontCares should be(true)
+//     BitPat("b0?").allDontCares should be(false)
+//     BitPat("b?1").allDontCares should be(false)
+//     BitPat("b0").allDontCares should be(false)
+//     BitPat("b10").allDontCares should be(false)
+//     BitPat("b1").allDontCares should be(false)
+//     BitPat("b" + ("1" * 128)).allDontCares should be(false)
+//     BitPat.dontCare(23).allDontCares should be(true)
+//     BitPat(0xdeadbeefL.U).allDontCares should be(false)
+//     // Zero-width not supported yet
+//     intercept[IllegalArgumentException] { BitPat("b").allDontCares should be(true) }
+//   }
+
+//   it should "convert to BitPat from ChiselEnum" in {
+//     val b = BitPat(EnumExample.VAL1)
+//     val c = BitPat(EnumExample.VAL3)
+//     b should be(BitPat("b00"))
+//     c should be(BitPat("b10"))
+//   }
+// }
diff --git a/src/test/scala/chiselTests/AutoNestedCloneSpec.scala b/src/test/scala/chiselTests/AutoNestedCloneSpec.scala
index 75fcd2359d2..6a263e83790 100644
--- a/src/test/scala/chiselTests/AutoNestedCloneSpec.scala
+++ b/src/test/scala/chiselTests/AutoNestedCloneSpec.scala
@@ -1,144 +1,144 @@
-// SPDX-License-Identifier: Apache-2.0
+// // SPDX-License-Identifier: Apache-2.0
 
-package chiselTests
+// package chiselTests
 
-import chisel3._
-import circt.stage.ChiselStage.emitCHIRRTL
-import org.scalatest.flatspec.AnyFlatSpec
-import org.scalatest.matchers.should.Matchers
+// import chisel3._
+// import circt.stage.ChiselStage.emitCHIRRTL
+// import org.scalatest.flatspec.AnyFlatSpec
+// import org.scalatest.matchers.should.Matchers
 
-class BundleWithAnonymousInner(val w: Int) extends Bundle {
-  val inner = new Bundle {
-    val foo = Input(UInt(w.W))
-  }
-}
+// class BundleWithAnonymousInner(val w: Int) extends Bundle {
+//   val inner = new Bundle {
+//     val foo = Input(UInt(w.W))
+//   }
+// }
 
-class AutoNestedCloneSpec extends AnyFlatSpec with Matchers {
+// class AutoNestedCloneSpec extends AnyFlatSpec with Matchers {
 
-  behavior.of("autoCloneType of inner Bundle in Chisel3")
+//   behavior.of("autoCloneType of inner Bundle in Chisel3")
 
-  it should "clone a doubly-nested inner bundle successfully" in {
-    emitCHIRRTL {
-      class Outer(val w: Int) extends Module {
-        class Middle(val w: Int) {
-          class InnerIOType extends Bundle {
-            val in = Input(UInt(w.W))
-          }
-          def getIO: InnerIOType = new InnerIOType
-        }
-        val io = IO(new Bundle {})
-        val myWire = Wire((new Middle(w)).getIO)
-      }
-      new Outer(2)
-    }
-  }
+//   it should "clone a doubly-nested inner bundle successfully" in {
+//     emitCHIRRTL {
+//       class Outer(val w: Int) extends Module {
+//         class Middle(val w: Int) {
+//           class InnerIOType extends Bundle {
+//             val in = Input(UInt(w.W))
+//           }
+//           def getIO: InnerIOType = new InnerIOType
+//         }
+//         val io = IO(new Bundle {})
+//         val myWire = Wire((new Middle(w)).getIO)
+//       }
+//       new Outer(2)
+//     }
+//   }
 
-  it should "clone an anonymous inner bundle successfully" in {
-    emitCHIRRTL {
-      class TestTop(val w: Int) extends Module {
-        val io = IO(new Bundle {})
-        val myWire = Wire(new Bundle { val a = UInt(w.W) })
-      }
-      new TestTop(2)
-    }
-  }
+//   it should "clone an anonymous inner bundle successfully" in {
+//     emitCHIRRTL {
+//       class TestTop(val w: Int) extends Module {
+//         val io = IO(new Bundle {})
+//         val myWire = Wire(new Bundle { val a = UInt(w.W) })
+//       }
+//       new TestTop(2)
+//     }
+//   }
 
-  it should "pick the correct $outer instance for an anonymous inner bundle" in {
-    emitCHIRRTL {
-      class Inner(val w: Int) extends Module {
-        val io = IO(new Bundle {
-          val in = Input(UInt(w.W))
-          val out = Output(UInt(w.W))
-        })
-      }
-      class Outer(val w: Int) extends Module {
-        val io = IO(new Bundle {
-          val in = Input(UInt(w.W))
-          val out = Output(UInt(w.W))
-        })
-        val i = Module(new Inner(w))
-        val iw = Wire(chiselTypeOf(i.io))
-        iw <> io
-        i.io <> iw
-      }
-      new Outer(2)
-    }
-  }
+//   it should "pick the correct $outer instance for an anonymous inner bundle" in {
+//     emitCHIRRTL {
+//       class Inner(val w: Int) extends Module {
+//         val io = IO(new Bundle {
+//           val in = Input(UInt(w.W))
+//           val out = Output(UInt(w.W))
+//         })
+//       }
+//       class Outer(val w: Int) extends Module {
+//         val io = IO(new Bundle {
+//           val in = Input(UInt(w.W))
+//           val out = Output(UInt(w.W))
+//         })
+//         val i = Module(new Inner(w))
+//         val iw = Wire(chiselTypeOf(i.io))
+//         iw <> io
+//         i.io <> iw
+//       }
+//       new Outer(2)
+//     }
+//   }
 
-  it should "clone an anonymous, bound, inner bundle of another bundle successfully" in {
-    emitCHIRRTL {
-      class TestModule(w: Int) extends Module {
-        val io = IO(new BundleWithAnonymousInner(w))
-        val w0 = WireDefault(io)
-        val w1 = WireDefault(io.inner)
-      }
-      new TestModule(8)
-    }
-  }
+//   it should "clone an anonymous, bound, inner bundle of another bundle successfully" in {
+//     emitCHIRRTL {
+//       class TestModule(w: Int) extends Module {
+//         val io = IO(new BundleWithAnonymousInner(w))
+//         val w0 = WireDefault(io)
+//         val w1 = WireDefault(io.inner)
+//       }
+//       new TestModule(8)
+//     }
+//   }
 
-  it should "clone an anonymous, inner bundle of a Module, bound to another bundle successfully" in {
-    emitCHIRRTL {
-      class TestModule(w: Int) extends Module {
-        val bun = new Bundle {
-          val foo = UInt(w.W)
-        }
-        val io = IO(new Bundle {
-          val inner = Input(bun)
-        })
-        val w0 = WireDefault(io)
-        val w1 = WireDefault(io.inner)
-      }
-      new TestModule(8)
-    }
-  }
+//   it should "clone an anonymous, inner bundle of a Module, bound to another bundle successfully" in {
+//     emitCHIRRTL {
+//       class TestModule(w: Int) extends Module {
+//         val bun = new Bundle {
+//           val foo = UInt(w.W)
+//         }
+//         val io = IO(new Bundle {
+//           val inner = Input(bun)
+//         })
+//         val w0 = WireDefault(io)
+//         val w1 = WireDefault(io.inner)
+//       }
+//       new TestModule(8)
+//     }
+//   }
 
-  it should "clone a double-nested anonymous Bundle" in {
-    emitCHIRRTL {
-      class TestModule() extends Module {
-        val io = IO(new Bundle {
-          val inner = Input(new Bundle {
-            val x = UInt(8.W)
-          })
-        })
-      }
-      new TestModule()
-    }
-  }
+//   it should "clone a double-nested anonymous Bundle" in {
+//     emitCHIRRTL {
+//       class TestModule() extends Module {
+//         val io = IO(new Bundle {
+//           val inner = Input(new Bundle {
+//             val x = UInt(8.W)
+//           })
+//         })
+//       }
+//       new TestModule()
+//     }
+//   }
 
-  it should "support an anonymous doubly-nested inner bundle" in {
-    emitCHIRRTL {
-      class Outer(val w: Int) extends Module {
-        class Middle(val w: Int) {
-          def getIO: Bundle = new Bundle {
-            val in = Input(UInt(w.W))
-          }
-        }
-        val io = IO(new Bundle {})
-        val myWire = Wire((new Middle(w)).getIO)
-      }
-      new Outer(2)
-    }
-  }
+//   it should "support an anonymous doubly-nested inner bundle" in {
+//     emitCHIRRTL {
+//       class Outer(val w: Int) extends Module {
+//         class Middle(val w: Int) {
+//           def getIO: Bundle = new Bundle {
+//             val in = Input(UInt(w.W))
+//           }
+//         }
+//         val io = IO(new Bundle {})
+//         val myWire = Wire((new Middle(w)).getIO)
+//       }
+//       new Outer(2)
+//     }
+//   }
 
-  it should "support anonymous Inner bundles that capture type parameters from outer Bundles" in {
-    emitCHIRRTL(new Module {
-      class MyBundle[T <: Data](n: Int, gen: T) extends Bundle {
-        val foo = new Bundle {
-          val x = Input(Vec(n, gen))
-        }
-        trait HasMkBundle { def mkBundle: Bundle }
+//   it should "support anonymous Inner bundles that capture type parameters from outer Bundles" in {
+//     emitCHIRRTL(new Module {
+//       class MyBundle[T <: Data](n: Int, gen: T) extends Bundle {
+//         val foo = new Bundle {
+//           val x = Input(Vec(n, gen))
+//         }
+//         trait HasMkBundle { def mkBundle: Bundle }
 
-        val mk: HasMkBundle =
-          new HasMkBundle {
-            def mkBundle: Bundle = new Bundle { val x = Vec(n, gen) }
-          }
-        val bar = Output(mk.mkBundle)
-      }
-      val io = IO(new MyBundle(4, UInt(8.W)))
-      val myWire = WireInit(io.foo)
-      val myWire2 = WireInit(io.bar)
-      io.bar.x := io.foo.x
+//         val mk: HasMkBundle =
+//           new HasMkBundle {
+//             def mkBundle: Bundle = new Bundle { val x = Vec(n, gen) }
+//           }
+//         val bar = Output(mk.mkBundle)
+//       }
+//       val io = IO(new MyBundle(4, UInt(8.W)))
+//       val myWire = WireInit(io.foo)
+//       val myWire2 = WireInit(io.bar)
+//       io.bar.x := io.foo.x
 
-    })
-  }
-}
+//     })
+//   }
+// }
diff --git a/src/test/scala/chiselTests/ModuleChoiceSpec.scala b/src/test/scala/chiselTests/ModuleChoiceSpec.scala
index 1456176aa65..e51a822db17 100644
--- a/src/test/scala/chiselTests/ModuleChoiceSpec.scala
+++ b/src/test/scala/chiselTests/ModuleChoiceSpec.scala
@@ -36,7 +36,7 @@ class ModuleWithChoice[T <: Data](
 )(alternateImpls: Seq[(Case, () => FixedIOBaseModule[T])])
     extends Module {
   val inst: T = ModuleChoice[T](default, alternateImpls)
-  val io: T = IO(chiselTypeOf(inst))
+  val io:   T = IO(chiselTypeOf(inst))
   io <> inst
 }
 
diff --git a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala
index 303d04a53e8..6ba8eacd2c9 100644
--- a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala
@@ -6,7 +6,7 @@ import chisel3.RawModule
 import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.stage.phases.{AddImplicitOutputAnnotationFile, Elaborate}
 
-import firrtl.{annoSeqToSeq, AnnotationSeq, seqToAnnoSeq}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{OutputAnnotationFileAnnotation, Phase}
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
diff --git a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala
index 622231d07a0..d0987b9be09 100644
--- a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala
@@ -6,7 +6,7 @@ import chisel3.RawModule
 import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOutputFileAnnotation}
 import chisel3.stage.phases.{AddImplicitOutputFile, Elaborate}
 
-import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{Phase, StageOptions, TargetDirAnnotation}
 import firrtl.options.Viewer.view
 import org.scalatest.flatspec.AnyFlatSpec
diff --git a/src/test/scala/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala b/src/test/scala/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala
index c076f07b057..8a96426a5af 100644
--- a/src/test/scala/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala
@@ -7,7 +7,7 @@ import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOutputFileAnnotation, Cir
 import chisel3.stage.CircuitSerializationAnnotation._
 import chisel3.stage.phases.{AddImplicitOutputFile, AddSerializationAnnotations, Elaborate}
 
-import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{Dependency, Phase, PhaseManager, TargetDirAnnotation}
 import firrtl.options.Viewer.view
 import org.scalatest.flatspec.AnyFlatSpec
diff --git a/src/test/scala/chiselTests/stage/phases/ChecksSpec.scala b/src/test/scala/chiselTests/stage/phases/ChecksSpec.scala
index 4c7fb0b6302..bbb7ccba8ed 100644
--- a/src/test/scala/chiselTests/stage/phases/ChecksSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/ChecksSpec.scala
@@ -5,7 +5,7 @@ package chiselTests.stage.phases
 import chisel3.stage.{ChiselOutputFileAnnotation, PrintFullStackTraceAnnotation}
 import chisel3.stage.phases.Checks
 
-import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.annotations.NoTargetAnnotation
 import firrtl.options.{OptionsException, Phase}
 import org.scalatest.flatspec.AnyFlatSpec
diff --git a/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala b/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala
index 8b3327aee0f..70ea2022633 100644
--- a/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala
@@ -6,7 +6,7 @@ import chisel3._
 import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.stage.phases.{Convert, Elaborate}
 
-import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.annotations.{Annotation, NoTargetAnnotation}
 import firrtl.options.Phase
 import firrtl.stage.FirrtlCircuitAnnotation
diff --git a/src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala b/src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala
index 102de40f637..34cc3c64f56 100644
--- a/src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala
@@ -7,7 +7,7 @@ import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation}
 import chisel3.stage.phases.Elaborate
 
 import firrtl.options.Phase
-import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 
diff --git a/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala b/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala
index 90b5cf36f81..2cbb9ab0c04 100644
--- a/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala
@@ -7,7 +7,7 @@ import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation, Chisel
 import chisel3.stage.phases.{Convert, Elaborate, Emitter}
 
 import firrtl.EmittedFirrtlCircuitAnnotation
-import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{Phase, TargetDirAnnotation}
 
 import java.io.File
diff --git a/src/test/scala/circtTests/stage/phases/AddImplicitOutputFileSpec.scala b/src/test/scala/circtTests/stage/phases/AddImplicitOutputFileSpec.scala
index c980dfdd2b8..b348623f58f 100644
--- a/src/test/scala/circtTests/stage/phases/AddImplicitOutputFileSpec.scala
+++ b/src/test/scala/circtTests/stage/phases/AddImplicitOutputFileSpec.scala
@@ -5,7 +5,7 @@ package circtTests.stage.phases
 import firrtl.ir
 import firrtl.options.Phase
 import firrtl.stage.{FirrtlCircuitAnnotation, OutputFileAnnotation}
-import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import circt.stage.phases.AddImplicitOutputFile
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers

From 559d775e6fdde1162db3de90ee12141f000beed0 Mon Sep 17 00:00:00 2001
From: Aditya Naik <aditya.naik@sifive.com>
Date: Tue, 25 Nov 2025 00:07:10 -0800
Subject: [PATCH 08/13] Move ComplexAssign back

---
 src/test/{scala => scala-2}/chiselTests/ComplexAssign.scala | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename src/test/{scala => scala-2}/chiselTests/ComplexAssign.scala (100%)

diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala-2/chiselTests/ComplexAssign.scala
similarity index 100%
rename from src/test/scala/chiselTests/ComplexAssign.scala
rename to src/test/scala-2/chiselTests/ComplexAssign.scala

From 996f20e1d73524d926e7df7248a232f09ca68b13 Mon Sep 17 00:00:00 2001
From: Aditya Naik <aditya.naik@sifive.com>
Date: Tue, 25 Nov 2025 00:08:33 -0800
Subject: [PATCH 09/13] Move back OpaqueTypeSpec

---
 .../chiselTests/experimental/OpaqueTypeSpec.scala                 | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename src/test/{scala => scala-2}/chiselTests/experimental/OpaqueTypeSpec.scala (100%)

diff --git a/src/test/scala/chiselTests/experimental/OpaqueTypeSpec.scala b/src/test/scala-2/chiselTests/experimental/OpaqueTypeSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/experimental/OpaqueTypeSpec.scala
rename to src/test/scala-2/chiselTests/experimental/OpaqueTypeSpec.scala

From a2b6de5141ef3f833e89377aee1eac7736e95992 Mon Sep 17 00:00:00 2001
From: Aditya Naik <aditya.naik@sifive.com>
Date: Tue, 25 Nov 2025 00:25:40 -0800
Subject: [PATCH 10/13] Move back Direction.scala

---
 src/test/{scala => scala-2}/chiselTests/Direction.scala | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename src/test/{scala => scala-2}/chiselTests/Direction.scala (100%)

diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala-2/chiselTests/Direction.scala
similarity index 100%
rename from src/test/scala/chiselTests/Direction.scala
rename to src/test/scala-2/chiselTests/Direction.scala

From 3df13ac78c52bafb3838dd6accf24445a19515b1 Mon Sep 17 00:00:00 2001
From: Aditya Naik <aditya.naik@sifive.com>
Date: Tue, 25 Nov 2025 00:25:53 -0800
Subject: [PATCH 11/13] Move back InstanceNameSpec

---
 src/test/{scala => scala-2}/chiselTests/InstanceNameSpec.scala | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename src/test/{scala => scala-2}/chiselTests/InstanceNameSpec.scala (100%)

diff --git a/src/test/scala/chiselTests/InstanceNameSpec.scala b/src/test/scala-2/chiselTests/InstanceNameSpec.scala
similarity index 100%
rename from src/test/scala/chiselTests/InstanceNameSpec.scala
rename to src/test/scala-2/chiselTests/InstanceNameSpec.scala

From 9ff3b1cf2054172120709438f6a69f67dcee5de8 Mon Sep 17 00:00:00 2001
From: Aditya Naik <aditya.naik@sifive.com>
Date: Tue, 25 Nov 2025 00:26:22 -0800
Subject: [PATCH 12/13] Test updates

---
 src/test/scala/chiselTests/BlackBox.scala                       | 2 +-
 .../scala/chiselTests/testing/HasTestingDirectorySpec.scala     | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 114bd3493ce..946552f93ae 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -361,7 +361,7 @@ class BlackBoxSpec extends AnyFlatSpec with Matchers with ChiselSim with FileChe
     object A extends layer.Layer(layer.LayerConfig.Extract())
 
     sealed trait NoIo { this: BlackBox =>
-      final val io = IO(new Bundle {})
+      final val io = chisel3.IO(new Bundle {})
     }
 
     // No known layers
diff --git a/src/test/scala/chiselTests/testing/HasTestingDirectorySpec.scala b/src/test/scala/chiselTests/testing/HasTestingDirectorySpec.scala
index 9e3feb5b206..d4c00270c8d 100644
--- a/src/test/scala/chiselTests/testing/HasTestingDirectorySpec.scala
+++ b/src/test/scala/chiselTests/testing/HasTestingDirectorySpec.scala
@@ -68,8 +68,6 @@ class HasTestingDirectorySpec extends AnyFlatSpec with Matchers {
       testingDirectory.getDirectory
     }
 
-    implicit val bar: HasTestingDirectory = implicitly[HasTestingDirectory]
-
     foo should be(foo)
 
   }

From 85ad8fa6110777c4e42f9d55cf337d80bf3d05a8 Mon Sep 17 00:00:00 2001
From: Aditya Naik <aditya.naik@sifive.com>
Date: Tue, 25 Nov 2025 12:19:18 -0800
Subject: [PATCH 13/13] Remove reflectiveSelectable import

---
 .../scala-2/chisel3/util/BitPatSpec.scala     | 132 ++++++++++++++++
 .../chiselTests/AutoNestedCloneSpec.scala     | 137 +++++++++++++++++
 src/test/scala-2/chiselTests/ProbeSpec.scala  |   1 -
 src/test/scala/chisel3/util/BitPatSpec.scala  | 132 ----------------
 .../chiselTests/AutoNestedCloneSpec.scala     | 144 ------------------
 src/test/scala/chiselTests/BoolSpec.scala     |   1 -
 .../scala/chiselTests/BulkConnectSpec.scala   |   1 -
 src/test/scala/chiselTests/ClockSpec.scala    |   1 -
 src/test/scala/chiselTests/ExtModule.scala    |   1 -
 .../scala/chiselTests/ModuleChoiceSpec.scala  |   1 -
 src/test/scala/chiselTests/ModuleSpec.scala   |   1 -
 src/test/scala/chiselTests/Vec.scala          |   2 -
 12 files changed, 269 insertions(+), 285 deletions(-)
 create mode 100644 src/test/scala-2/chisel3/util/BitPatSpec.scala
 create mode 100644 src/test/scala-2/chiselTests/AutoNestedCloneSpec.scala
 delete mode 100644 src/test/scala/chisel3/util/BitPatSpec.scala
 delete mode 100644 src/test/scala/chiselTests/AutoNestedCloneSpec.scala

diff --git a/src/test/scala-2/chisel3/util/BitPatSpec.scala b/src/test/scala-2/chisel3/util/BitPatSpec.scala
new file mode 100644
index 00000000000..3b1d58a6164
--- /dev/null
+++ b/src/test/scala-2/chisel3/util/BitPatSpec.scala
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chisel3.util
+
+import chisel3._
+import chisel3.util.BitPat
+import _root_.circt.stage.ChiselStage
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
+
+object EnumExample extends ChiselEnum {
+  val VAL1, VAL2, VAL3 = Value
+}
+
+class BitPatSpec extends AnyFlatSpec with Matchers {
+  behavior.of(classOf[BitPat].toString)
+
+  it should "convert a BitPat to readable form" in {
+    val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
+    BitPat("b" + testPattern).toString should be(s"BitPat($testPattern)")
+  }
+
+  it should "convert a BitPat to raw form" in {
+    val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
+    BitPat("b" + testPattern).rawString should be(testPattern)
+  }
+
+  it should "not fail if BitPat width is 0" in {
+    intercept[IllegalArgumentException] { BitPat("b") }
+  }
+
+  it should "concat BitPat via ##" in {
+    (BitPat.Y(4) ## BitPat.dontCare(3) ## BitPat.N(2)).toString should be(s"BitPat(1111???00)")
+  }
+
+  it should "throw when BitPat apply to a Hardware" in {
+    intercept[java.lang.IllegalArgumentException] {
+      ChiselStage.emitCHIRRTL(new chisel3.Module {
+        BitPat(chisel3.Reg(chisel3.Bool()))
+      })
+    }
+  }
+
+  it should "index and return new BitPat" in {
+    val b = BitPat("b1001???")
+    b(0) should be(BitPat.dontCare(1))
+    b(6) should be(BitPat.Y())
+    b(5) should be(BitPat.N())
+  }
+
+  it should "slice and return new BitPat" in {
+    val b = BitPat("b1001???")
+    b(2, 0) should be(BitPat("b???"))
+    b(4, 3) should be(BitPat("b01"))
+    b(6, 6) should be(BitPat("b1"))
+  }
+
+  it should "parse UInt literals correctly" in {
+    BitPat(0.U) should be(new BitPat(0, 1, 1))
+    // Note that this parses as 1-bit width, there are other APIs that don't support zero-width UInts correctly
+    BitPat(0.U(0.W)) should be(new BitPat(0, 1, 1))
+    BitPat(1.U) should be(new BitPat(1, 1, 1))
+    BitPat(2.U) should be(new BitPat(2, 3, 2))
+    BitPat(0xdeadbeefL.U) should be(new BitPat(BigInt("deadbeef", 16), BigInt("ffffffff", 16), 32))
+  }
+
+  it should "support .hasDontCares" in {
+    BitPat("b?").hasDontCares should be(true)
+    BitPat("b??").hasDontCares should be(true)
+    BitPat("b0?").hasDontCares should be(true)
+    BitPat("b?1").hasDontCares should be(true)
+    BitPat("b0").hasDontCares should be(false)
+    BitPat("b10").hasDontCares should be(false)
+    BitPat("b01").hasDontCares should be(false)
+    BitPat(0xdeadbeefL.U).hasDontCares should be(false)
+    // Zero-width not supported yet
+    intercept[IllegalArgumentException] { BitPat("b").hasDontCares should be(false) }
+  }
+
+  it should "support .allZeros" in {
+    BitPat("b?").allZeros should be(false)
+    BitPat("b??").allZeros should be(false)
+    BitPat("b0?").allZeros should be(false)
+    BitPat("b?1").allZeros should be(false)
+    BitPat("b0").allZeros should be(true)
+    BitPat("b10").allZeros should be(false)
+    BitPat("b01").allZeros should be(false)
+    BitPat(0.U(128.W)).allZeros should be(true)
+    BitPat.N(23).allZeros should be(true)
+    BitPat(0xdeadbeefL.U).allZeros should be(false)
+    // Zero-width not supported yet
+    intercept[IllegalArgumentException] { BitPat("b").allZeros should be(true) }
+  }
+
+  it should "support .allOnes" in {
+    BitPat("b?").allOnes should be(false)
+    BitPat("b??").allOnes should be(false)
+    BitPat("b0?").allOnes should be(false)
+    BitPat("b?1").allOnes should be(false)
+    BitPat("b0").allOnes should be(false)
+    BitPat("b10").allOnes should be(false)
+    BitPat("b01").allOnes should be(false)
+    BitPat("b1").allOnes should be(true)
+    BitPat("b" + ("1" * 128)).allOnes should be(true)
+    BitPat.Y(23).allOnes should be(true)
+    BitPat(0xdeadbeefL.U).allOnes should be(false)
+    // Zero-width not supported yet
+    intercept[IllegalArgumentException] { BitPat("b").allOnes should be(true) }
+  }
+
+  it should "support .allDontCares" in {
+    BitPat("b?").allDontCares should be(true)
+    BitPat("b??").allDontCares should be(true)
+    BitPat("b0?").allDontCares should be(false)
+    BitPat("b?1").allDontCares should be(false)
+    BitPat("b0").allDontCares should be(false)
+    BitPat("b10").allDontCares should be(false)
+    BitPat("b1").allDontCares should be(false)
+    BitPat("b" + ("1" * 128)).allDontCares should be(false)
+    BitPat.dontCare(23).allDontCares should be(true)
+    BitPat(0xdeadbeefL.U).allDontCares should be(false)
+    // Zero-width not supported yet
+    intercept[IllegalArgumentException] { BitPat("b").allDontCares should be(true) }
+  }
+
+  it should "convert to BitPat from ChiselEnum" in {
+    val b = BitPat(EnumExample.VAL1)
+    val c = BitPat(EnumExample.VAL3)
+    b should be(BitPat("b00"))
+    c should be(BitPat("b10"))
+  }
+}
diff --git a/src/test/scala-2/chiselTests/AutoNestedCloneSpec.scala b/src/test/scala-2/chiselTests/AutoNestedCloneSpec.scala
new file mode 100644
index 00000000000..b69abfc2d8f
--- /dev/null
+++ b/src/test/scala-2/chiselTests/AutoNestedCloneSpec.scala
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests
+
+import chisel3._
+import circt.stage.ChiselStage.emitCHIRRTL
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
+
+class BundleWithAnonymousInner(val w: Int) extends Bundle {
+  val inner = new Bundle {
+    val foo = Input(UInt(w.W))
+  }
+}
+
+class AutoNestedCloneSpec extends AnyFlatSpec with Matchers {
+
+  behavior.of("autoCloneType of inner Bundle in Chisel3")
+
+  it should "clone a doubly-nested inner bundle successfully" in {
+    emitCHIRRTL {
+      class Outer(val w: Int) extends Module {
+        class Middle(val w: Int) {
+          class InnerIOType extends Bundle {
+            val in = Input(UInt(w.W))
+          }
+          def getIO: InnerIOType = new InnerIOType
+        }
+        val io = IO(new Bundle {})
+        val myWire = Wire((new Middle(w)).getIO)
+      }
+      new Outer(2)
+    }
+  }
+
+  it should "clone an anonymous inner bundle successfully" in {
+    emitCHIRRTL {
+      class TestTop(val w: Int) extends Module {
+        val io = IO(new Bundle {})
+        val myWire = Wire(new Bundle { val a = UInt(w.W) })
+      }
+      new TestTop(2)
+    }
+  }
+
+  it should "pick the correct $outer instance for an anonymous inner bundle" in {
+    emitCHIRRTL {
+      class Inner(val w: Int) extends Module {
+        val io = IO(new Bundle {
+          val in = Input(UInt(w.W))
+          val out = Output(UInt(w.W))
+        })
+      }
+      class Outer(val w: Int) extends Module {
+        val io = IO(new Bundle {
+          val in = Input(UInt(w.W))
+          val out = Output(UInt(w.W))
+        })
+        val i = Module(new Inner(w))
+        val iw = Wire(chiselTypeOf(i.io))
+        iw <> io
+        i.io <> iw
+      }
+      new Outer(2)
+    }
+  }
+
+  it should "clone an anonymous, bound, inner bundle of another bundle successfully" in {
+    emitCHIRRTL {
+      class TestModule(w: Int) extends Module {
+        val io = IO(new BundleWithAnonymousInner(w))
+        val w0 = WireDefault(io)
+        val w1 = WireDefault(io.inner)
+      }
+      new TestModule(8)
+    }
+  }
+
+  it should "clone an anonymous, inner bundle of a Module, bound to another bundle successfully" in {
+    emitCHIRRTL {
+      class TestModule(w: Int) extends Module {
+        val bun = new Bundle {
+          val foo = UInt(w.W)
+        }
+        val io = IO(new Bundle {
+          val inner = Input(bun)
+        })
+        val w0 = WireDefault(io)
+        val w1 = WireDefault(io.inner)
+      }
+      new TestModule(8)
+    }
+  }
+
+  it should "clone a double-nested anonymous Bundle" in {
+    emitCHIRRTL {
+      class TestModule() extends Module {
+        val io = IO(new Bundle {
+          val inner = Input(new Bundle {
+            val x = UInt(8.W)
+          })
+        })
+      }
+      new TestModule()
+    }
+  }
+
+  it should "support an anonymous doubly-nested inner bundle" in {
+    emitCHIRRTL {
+      class Outer(val w: Int) extends Module {
+        class Middle(val w: Int) {
+          def getIO: Bundle = new Bundle {
+            val in = Input(UInt(w.W))
+          }
+        }
+        val io = IO(new Bundle {})
+        val myWire = Wire((new Middle(w)).getIO)
+      }
+      new Outer(2)
+    }
+  }
+
+  it should "support anonymous Inner bundles that capture type parameters from outer Bundles" in {
+    emitCHIRRTL(new Module {
+      class MyBundle[T <: Data](n: Int, gen: T) extends Bundle {
+        val foo = new Bundle {
+          val x = Input(Vec(n, gen))
+        }
+        val bar = Output(Option(new { def mkBundle = new Bundle { val x = Vec(n, gen) } }).get.mkBundle)
+      }
+      val io = IO(new MyBundle(4, UInt(8.W)))
+      val myWire = WireInit(io.foo)
+      val myWire2 = WireInit(io.bar)
+      io.bar.x := io.foo.x
+    })
+  }
+}
diff --git a/src/test/scala-2/chiselTests/ProbeSpec.scala b/src/test/scala-2/chiselTests/ProbeSpec.scala
index e1c289da75f..6cae1e4c893 100644
--- a/src/test/scala-2/chiselTests/ProbeSpec.scala
+++ b/src/test/scala-2/chiselTests/ProbeSpec.scala
@@ -12,7 +12,6 @@ import chisel3.testing.scalatest.FileCheck
 import circt.stage.ChiselStage
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
-import scala.reflect.Selectable.reflectiveSelectable
 
 class ProbeSpec extends AnyFlatSpec with Matchers with FileCheck with ChiselSim {
   // Strip SourceInfos and split into lines
diff --git a/src/test/scala/chisel3/util/BitPatSpec.scala b/src/test/scala/chisel3/util/BitPatSpec.scala
deleted file mode 100644
index b5287337999..00000000000
--- a/src/test/scala/chisel3/util/BitPatSpec.scala
+++ /dev/null
@@ -1,132 +0,0 @@
-// // SPDX-License-Identifier: Apache-2.0
-
-// package chisel3.util
-
-// import chisel3._
-// import chisel3.util.BitPat
-// import _root_.circt.stage.ChiselStage
-// import org.scalatest.flatspec.AnyFlatSpec
-// import org.scalatest.matchers.should.Matchers
-
-// object EnumExample extends ChiselEnum {
-//   val VAL1, VAL2, VAL3 = Value
-// }
-
-// class BitPatSpec extends AnyFlatSpec with Matchers {
-//   behavior.of(classOf[BitPat].toString)
-
-//   it should "convert a BitPat to readable form" in {
-//     val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
-//     BitPat("b" + testPattern).toString should be(s"BitPat($testPattern)")
-//   }
-
-//   it should "convert a BitPat to raw form" in {
-//     val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
-//     BitPat("b" + testPattern).rawString should be(testPattern)
-//   }
-
-//   it should "not fail if BitPat width is 0" in {
-//     intercept[IllegalArgumentException] { BitPat("b") }
-//   }
-
-//   it should "concat BitPat via ##" in {
-//     (BitPat.Y(4) ## BitPat.dontCare(3) ## BitPat.N(2)).toString should be(s"BitPat(1111???00)")
-//   }
-
-//   it should "throw when BitPat apply to a Hardware" in {
-//     intercept[java.lang.IllegalArgumentException] {
-//       ChiselStage.emitCHIRRTL(new chisel3.Module {
-//         BitPat(chisel3.Reg(chisel3.Bool()))
-//       })
-//     }
-//   }
-
-//   it should "index and return new BitPat" in {
-//     val b = BitPat("b1001???")
-//     b(0) should be(BitPat.dontCare(1))
-//     b(6) should be(BitPat.Y())
-//     b(5) should be(BitPat.N())
-//   }
-
-//   it should "slice and return new BitPat" in {
-//     val b = BitPat("b1001???")
-//     b(2, 0) should be(BitPat("b???"))
-//     b(4, 3) should be(BitPat("b01"))
-//     b(6, 6) should be(BitPat("b1"))
-//   }
-
-//   it should "parse UInt literals correctly" in {
-//     BitPat(0.U) should be(new BitPat(0, 1, 1))
-//     // Note that this parses as 1-bit width, there are other APIs that don't support zero-width UInts correctly
-//     BitPat(0.U(0.W)) should be(new BitPat(0, 1, 1))
-//     BitPat(1.U) should be(new BitPat(1, 1, 1))
-//     BitPat(2.U) should be(new BitPat(2, 3, 2))
-//     BitPat(0xdeadbeefL.U) should be(new BitPat(BigInt("deadbeef", 16), BigInt("ffffffff", 16), 32))
-//   }
-
-//   it should "support .hasDontCares" in {
-//     BitPat("b?").hasDontCares should be(true)
-//     BitPat("b??").hasDontCares should be(true)
-//     BitPat("b0?").hasDontCares should be(true)
-//     BitPat("b?1").hasDontCares should be(true)
-//     BitPat("b0").hasDontCares should be(false)
-//     BitPat("b10").hasDontCares should be(false)
-//     BitPat("b01").hasDontCares should be(false)
-//     BitPat(0xdeadbeefL.U).hasDontCares should be(false)
-//     // Zero-width not supported yet
-//     intercept[IllegalArgumentException] { BitPat("b").hasDontCares should be(false) }
-//   }
-
-//   it should "support .allZeros" in {
-//     BitPat("b?").allZeros should be(false)
-//     BitPat("b??").allZeros should be(false)
-//     BitPat("b0?").allZeros should be(false)
-//     BitPat("b?1").allZeros should be(false)
-//     BitPat("b0").allZeros should be(true)
-//     BitPat("b10").allZeros should be(false)
-//     BitPat("b01").allZeros should be(false)
-//     BitPat(0.U(128.W)).allZeros should be(true)
-//     BitPat.N(23).allZeros should be(true)
-//     BitPat(0xdeadbeefL.U).allZeros should be(false)
-//     // Zero-width not supported yet
-//     intercept[IllegalArgumentException] { BitPat("b").allZeros should be(true) }
-//   }
-
-//   it should "support .allOnes" in {
-//     BitPat("b?").allOnes should be(false)
-//     BitPat("b??").allOnes should be(false)
-//     BitPat("b0?").allOnes should be(false)
-//     BitPat("b?1").allOnes should be(false)
-//     BitPat("b0").allOnes should be(false)
-//     BitPat("b10").allOnes should be(false)
-//     BitPat("b01").allOnes should be(false)
-//     BitPat("b1").allOnes should be(true)
-//     BitPat("b" + ("1" * 128)).allOnes should be(true)
-//     BitPat.Y(23).allOnes should be(true)
-//     BitPat(0xdeadbeefL.U).allOnes should be(false)
-//     // Zero-width not supported yet
-//     intercept[IllegalArgumentException] { BitPat("b").allOnes should be(true) }
-//   }
-
-//   it should "support .allDontCares" in {
-//     BitPat("b?").allDontCares should be(true)
-//     BitPat("b??").allDontCares should be(true)
-//     BitPat("b0?").allDontCares should be(false)
-//     BitPat("b?1").allDontCares should be(false)
-//     BitPat("b0").allDontCares should be(false)
-//     BitPat("b10").allDontCares should be(false)
-//     BitPat("b1").allDontCares should be(false)
-//     BitPat("b" + ("1" * 128)).allDontCares should be(false)
-//     BitPat.dontCare(23).allDontCares should be(true)
-//     BitPat(0xdeadbeefL.U).allDontCares should be(false)
-//     // Zero-width not supported yet
-//     intercept[IllegalArgumentException] { BitPat("b").allDontCares should be(true) }
-//   }
-
-//   it should "convert to BitPat from ChiselEnum" in {
-//     val b = BitPat(EnumExample.VAL1)
-//     val c = BitPat(EnumExample.VAL3)
-//     b should be(BitPat("b00"))
-//     c should be(BitPat("b10"))
-//   }
-// }
diff --git a/src/test/scala/chiselTests/AutoNestedCloneSpec.scala b/src/test/scala/chiselTests/AutoNestedCloneSpec.scala
deleted file mode 100644
index 6a263e83790..00000000000
--- a/src/test/scala/chiselTests/AutoNestedCloneSpec.scala
+++ /dev/null
@@ -1,144 +0,0 @@
-// // SPDX-License-Identifier: Apache-2.0
-
-// package chiselTests
-
-// import chisel3._
-// import circt.stage.ChiselStage.emitCHIRRTL
-// import org.scalatest.flatspec.AnyFlatSpec
-// import org.scalatest.matchers.should.Matchers
-
-// class BundleWithAnonymousInner(val w: Int) extends Bundle {
-//   val inner = new Bundle {
-//     val foo = Input(UInt(w.W))
-//   }
-// }
-
-// class AutoNestedCloneSpec extends AnyFlatSpec with Matchers {
-
-//   behavior.of("autoCloneType of inner Bundle in Chisel3")
-
-//   it should "clone a doubly-nested inner bundle successfully" in {
-//     emitCHIRRTL {
-//       class Outer(val w: Int) extends Module {
-//         class Middle(val w: Int) {
-//           class InnerIOType extends Bundle {
-//             val in = Input(UInt(w.W))
-//           }
-//           def getIO: InnerIOType = new InnerIOType
-//         }
-//         val io = IO(new Bundle {})
-//         val myWire = Wire((new Middle(w)).getIO)
-//       }
-//       new Outer(2)
-//     }
-//   }
-
-//   it should "clone an anonymous inner bundle successfully" in {
-//     emitCHIRRTL {
-//       class TestTop(val w: Int) extends Module {
-//         val io = IO(new Bundle {})
-//         val myWire = Wire(new Bundle { val a = UInt(w.W) })
-//       }
-//       new TestTop(2)
-//     }
-//   }
-
-//   it should "pick the correct $outer instance for an anonymous inner bundle" in {
-//     emitCHIRRTL {
-//       class Inner(val w: Int) extends Module {
-//         val io = IO(new Bundle {
-//           val in = Input(UInt(w.W))
-//           val out = Output(UInt(w.W))
-//         })
-//       }
-//       class Outer(val w: Int) extends Module {
-//         val io = IO(new Bundle {
-//           val in = Input(UInt(w.W))
-//           val out = Output(UInt(w.W))
-//         })
-//         val i = Module(new Inner(w))
-//         val iw = Wire(chiselTypeOf(i.io))
-//         iw <> io
-//         i.io <> iw
-//       }
-//       new Outer(2)
-//     }
-//   }
-
-//   it should "clone an anonymous, bound, inner bundle of another bundle successfully" in {
-//     emitCHIRRTL {
-//       class TestModule(w: Int) extends Module {
-//         val io = IO(new BundleWithAnonymousInner(w))
-//         val w0 = WireDefault(io)
-//         val w1 = WireDefault(io.inner)
-//       }
-//       new TestModule(8)
-//     }
-//   }
-
-//   it should "clone an anonymous, inner bundle of a Module, bound to another bundle successfully" in {
-//     emitCHIRRTL {
-//       class TestModule(w: Int) extends Module {
-//         val bun = new Bundle {
-//           val foo = UInt(w.W)
-//         }
-//         val io = IO(new Bundle {
-//           val inner = Input(bun)
-//         })
-//         val w0 = WireDefault(io)
-//         val w1 = WireDefault(io.inner)
-//       }
-//       new TestModule(8)
-//     }
-//   }
-
-//   it should "clone a double-nested anonymous Bundle" in {
-//     emitCHIRRTL {
-//       class TestModule() extends Module {
-//         val io = IO(new Bundle {
-//           val inner = Input(new Bundle {
-//             val x = UInt(8.W)
-//           })
-//         })
-//       }
-//       new TestModule()
-//     }
-//   }
-
-//   it should "support an anonymous doubly-nested inner bundle" in {
-//     emitCHIRRTL {
-//       class Outer(val w: Int) extends Module {
-//         class Middle(val w: Int) {
-//           def getIO: Bundle = new Bundle {
-//             val in = Input(UInt(w.W))
-//           }
-//         }
-//         val io = IO(new Bundle {})
-//         val myWire = Wire((new Middle(w)).getIO)
-//       }
-//       new Outer(2)
-//     }
-//   }
-
-//   it should "support anonymous Inner bundles that capture type parameters from outer Bundles" in {
-//     emitCHIRRTL(new Module {
-//       class MyBundle[T <: Data](n: Int, gen: T) extends Bundle {
-//         val foo = new Bundle {
-//           val x = Input(Vec(n, gen))
-//         }
-//         trait HasMkBundle { def mkBundle: Bundle }
-
-//         val mk: HasMkBundle =
-//           new HasMkBundle {
-//             def mkBundle: Bundle = new Bundle { val x = Vec(n, gen) }
-//           }
-//         val bar = Output(mk.mkBundle)
-//       }
-//       val io = IO(new MyBundle(4, UInt(8.W)))
-//       val myWire = WireInit(io.foo)
-//       val myWire2 = WireInit(io.bar)
-//       io.bar.x := io.foo.x
-
-//     })
-//   }
-// }
diff --git a/src/test/scala/chiselTests/BoolSpec.scala b/src/test/scala/chiselTests/BoolSpec.scala
index 721e59a9356..4294ef5b6a9 100644
--- a/src/test/scala/chiselTests/BoolSpec.scala
+++ b/src/test/scala/chiselTests/BoolSpec.scala
@@ -6,7 +6,6 @@ import chisel3._
 import chisel3.simulator.scalatest.ChiselSim
 import chisel3.simulator.stimulus.RunUntilFinished
 import org.scalatest.flatspec.AnyFlatSpec
-import scala.reflect.Selectable.reflectiveSelectable
 
 class BoolSpec extends AnyFlatSpec with ChiselSim {
 
diff --git a/src/test/scala/chiselTests/BulkConnectSpec.scala b/src/test/scala/chiselTests/BulkConnectSpec.scala
index 3188968f932..fc4d7da11c7 100644
--- a/src/test/scala/chiselTests/BulkConnectSpec.scala
+++ b/src/test/scala/chiselTests/BulkConnectSpec.scala
@@ -5,7 +5,6 @@ import chisel3.util.Decoupled
 import circt.stage.ChiselStage
 import org.scalatest.matchers.should.Matchers
 import org.scalatest.propspec.AnyPropSpec
-import scala.reflect.Selectable.reflectiveSelectable
 
 class BulkConnectSpec extends AnyPropSpec with Matchers {
   property("Chisel connects should emit FIRRTL bulk connects when possible") {
diff --git a/src/test/scala/chiselTests/ClockSpec.scala b/src/test/scala/chiselTests/ClockSpec.scala
index 2a40a01a1b6..ae54c51d7ea 100644
--- a/src/test/scala/chiselTests/ClockSpec.scala
+++ b/src/test/scala/chiselTests/ClockSpec.scala
@@ -8,7 +8,6 @@ import chisel3.simulator.stimulus.RunUntilFinished
 import circt.stage.ChiselStage
 import org.scalatest.propspec.AnyPropSpec
 import org.scalatest.matchers.should.Matchers
-import scala.reflect.Selectable.reflectiveSelectable
 
 class ClockAsUIntTester extends Module {
   assert(true.B.asClock.asUInt === 1.U)
diff --git a/src/test/scala/chiselTests/ExtModule.scala b/src/test/scala/chiselTests/ExtModule.scala
index 8a689adc83b..2b55a36e474 100644
--- a/src/test/scala/chiselTests/ExtModule.scala
+++ b/src/test/scala/chiselTests/ExtModule.scala
@@ -11,7 +11,6 @@ import chisel3.util.HasExtModuleResource
 import circt.stage.ChiselStage
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
-import scala.reflect.Selectable.reflectiveSelectable
 
 // Avoid collisions with regular BlackBox tests by putting ExtModule blackboxes
 // in their own scope.
diff --git a/src/test/scala/chiselTests/ModuleChoiceSpec.scala b/src/test/scala/chiselTests/ModuleChoiceSpec.scala
index e51a822db17..08db700f33f 100644
--- a/src/test/scala/chiselTests/ModuleChoiceSpec.scala
+++ b/src/test/scala/chiselTests/ModuleChoiceSpec.scala
@@ -9,7 +9,6 @@ import chisel3.testing.scalatest.FileCheck
 import circt.stage.ChiselStage
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
-import scala.reflect.Selectable.reflectiveSelectable
 
 object Platform extends Group {
   object FPGA extends Case
diff --git a/src/test/scala/chiselTests/ModuleSpec.scala b/src/test/scala/chiselTests/ModuleSpec.scala
index 477ecd4bd83..a88d0dcfa71 100644
--- a/src/test/scala/chiselTests/ModuleSpec.scala
+++ b/src/test/scala/chiselTests/ModuleSpec.scala
@@ -13,7 +13,6 @@ import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import org.scalatest.matchers.should.Matchers
 import org.scalatest.propspec.AnyPropSpec
 import scala.io.Source
-import scala.reflect.Selectable.reflectiveSelectable
 
 class SimpleIO extends Bundle {
   val in = Input(UInt(32.W))
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index e250e539b52..3bd6f619e69 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -326,8 +326,6 @@ class VecSpec extends AnyPropSpec with Matchers with LogUtils with FileCheck {
       }
       require(bundleWithZeroEntryVec.getWidth == 1)
 
-      import scala.reflect.Selectable.reflectiveSelectable
-
       val m = Module(new Module {
         val io = IO(Output(bundleWithZeroEntryVec))
         val zero = WireInit(0.U.asTypeOf(bundleWithZeroEntryVec))