From fbb2f4c77b08b4930344d038becc9645308251d2 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 8 Oct 2025 11:56:40 -0400 Subject: [PATCH 1/9] [svsim] Add -j, --build-jobs, and --verilate-jobs Add Verilator compilation-time options to the Verilator svsim backend. This is added to workaround an issue observed internally where Verilator can crash when running with full parallelism, i.e., the default `-j 0` that was previously hard-coded in the Verilator backend. The default behavior is preserved, but users can now set `-j` OR `--build-jobs`/`--verilate-jobs` individually. Signed-off-by: Schuyler Eldridge --- svsim/src/main/scala/verilator/Backend.scala | 35 +++++++++++-- svsim/src/test/scala/CommandLineSpec.scala | 54 ++++++++++++++++++++ 2 files changed, 86 insertions(+), 3 deletions(-) create mode 100644 svsim/src/test/scala/CommandLineSpec.scala diff --git a/svsim/src/main/scala/verilator/Backend.scala b/svsim/src/main/scala/verilator/Backend.scala index f4086f169fb..88a45c46528 100644 --- a/svsim/src/main/scala/verilator/Backend.scala +++ b/svsim/src/main/scala/verilator/Backend.scala @@ -22,7 +22,7 @@ object Backend { } /** FST tracing - * + * * @param traceThreads Enable FST waveform creation using `traceThreads` separate threads */ case class Fst(traceThreads: Option[Int] = None) extends Type { @@ -66,6 +66,30 @@ object Backend { case object TimingEnabled extends Type case object TimingDisabled extends Type } + + /** Control job parallelism in verilator */ + object Parallelism { + sealed trait Type { + def toCompileFlags: Seq[String] + } + + /** Apply uniform parallelism to Verilation. This maps to `-j`. */ + case class Uniform(num: Int) extends Type { + override def toCompileFlags = Seq("-j", num.toString) + } + + /** Apply non-uniform parallelism to Verilation. This allows control of + * `--build-jobs` and `--verilate-jobs` separately. + */ + case class Different(build: Option[Int] = None, verilate: Option[Int] = None) extends Type { + override def toCompileFlags: Seq[String] = { + val buildJobs: Seq[String] = build.map(num => Seq("--build-jobs", num.toString)).toSeq.flatten + val verilateJobs: Seq[String] = verilate.map(num => Seq("--verilate-jobs", num.toString)).toSeq.flatten + buildJobs ++ verilateJobs + } + } + } + } case class CompilationSettings( @@ -75,7 +99,8 @@ object Backend { disabledWarnings: Seq[String] = Seq(), disableFatalExitOnWarnings: Boolean = false, enableAllAssertions: Boolean = false, - timing: Option[CompilationSettings.Timing.Type] = None + timing: Option[CompilationSettings.Timing.Type] = None, + parallelism: Option[CompilationSettings.Parallelism.Type] = Some(CompilationSettings.Parallelism.Uniform(0)) ) extends svsim.Backend.Settings def initializeFromProcessEnvironment() = { @@ -114,13 +139,17 @@ final class Backend(executablePath: String) extends svsim.Backend { "--cc", "--exe", "--build", - "-j", "0", "-o", s"../$outputBinaryName", "--top-module", topModuleName, "--Mdir", "verilated-sources", "--assert" )) + backendSpecificSettings.parallelism match { + case Some(parallelism) => addArg(parallelism.toCompileFlags) + case None => + } + commonSettings.libraryExtensions.foreach { extensions => addArg(Seq((Seq("+libext") ++ extensions).mkString("+"))) } diff --git a/svsim/src/test/scala/CommandLineSpec.scala b/svsim/src/test/scala/CommandLineSpec.scala new file mode 100644 index 00000000000..c3366df9244 --- /dev/null +++ b/svsim/src/test/scala/CommandLineSpec.scala @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: Apache-2.0 + +package svsim.test + +import org.scalatest.flatspec.AnyFlatSpec +import org.scalatest.matchers.should.Matchers +import svsim.CommonCompilationSettings + +class CommandLineSpec extends AnyFlatSpec with Matchers { + + case class OptionTest(name: String, settings: svsim.verilator.Backend.CompilationSettings, string: Seq[String]) + + behavior of ("Verilator options") + + val verilatorBackend = new svsim.verilator.Backend(executablePath = "foo") + + val parallelismTests = { + import svsim.verilator.Backend.CompilationSettings + import svsim.verilator.Backend.CompilationSettings.Parallelism + Seq( + OptionTest("default", CompilationSettings(), Seq("-j", "0")), + OptionTest( + "uniform parallelism", + CompilationSettings(parallelism = Some(Parallelism.Uniform(2))), + Seq("-j", "2") + ), + OptionTest( + "only build parallelism", + CompilationSettings(parallelism = Some(Parallelism.Different(build = Some(4)))), + Seq("--build-jobs", "4") + ), + OptionTest( + "only verilate parallelism", + CompilationSettings(parallelism = Some(Parallelism.Different(verilate = Some(8)))), + Seq("--verilate-jobs", "8") + ), + OptionTest( + "different build and verilate parallelism", + CompilationSettings(parallelism = Some(Parallelism.Different(build = Some(16), verilate = Some(32)))), + Seq("--build-jobs", "16", "--verilate-jobs", "32") + ) + ) + } + + parallelismTests.foreach { case OptionTest(name, settings, expected) => + it should s"support $name behavior" in { + verilatorBackend + .generateParameters("bar", "baz", Seq.empty, CommonCompilationSettings(), settings) + .compilerInvocation + .arguments should contain inOrderElementsOf (expected) + } + } + +} From 0710e4790adde3326c5ef36b03105b23f4cd8a15 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 8 Oct 2025 23:13:40 -0400 Subject: [PATCH 2/9] fixup! [svsim] Add -j, --build-jobs, and --verilate-jobs --- .../chisel3/simulator/scalatest/Cli.scala | 4 +- svsim/src/main/scala/verilator/Backend.scala | 172 +++++++++++++++++- svsim/src/test/scala/BackendSpec.scala | 2 +- 3 files changed, 174 insertions(+), 4 deletions(-) diff --git a/src/main/scala/chisel3/simulator/scalatest/Cli.scala b/src/main/scala/chisel3/simulator/scalatest/Cli.scala index 2914eaeeb45..60c624465e5 100644 --- a/src/main/scala/chisel3/simulator/scalatest/Cli.scala +++ b/src/main/scala/chisel3/simulator/scalatest/Cli.scala @@ -129,8 +129,8 @@ object Cli { traceSettings = options.traceSettings.copy(enableVcd = true) ) case options: svsim.verilator.Backend.CompilationSettings => - options.copy( - traceStyle = options.traceStyle match { + options.withTraceStyle( + options.traceStyle match { case None => Some( svsim.verilator.Backend.CompilationSettings diff --git a/svsim/src/main/scala/verilator/Backend.scala b/svsim/src/main/scala/verilator/Backend.scala index 88a45c46528..30c96da2737 100644 --- a/svsim/src/main/scala/verilator/Backend.scala +++ b/svsim/src/main/scala/verilator/Backend.scala @@ -90,6 +90,49 @@ object Backend { } } + @deprecated("use newer CompilationSettings case class apply", "Chisel 7.1.0") + def apply( + traceStyle: Option[CompilationSettings.TraceStyle], + outputSplit: Option[Int], + outputSplitCFuncs: Option[Int], + disabledWarnings: Seq[String], + disableFatalExitOnWarnings: Boolean, + enableAllAssertions: Boolean, + timing: Option[CompilationSettings.Timing.Type] + ): CompilationSettings = CompilationSettings( + traceStyle, + outputSplit, + outputSplitCFuncs, + disabledWarnings, + disableFatalExitOnWarnings, + enableAllAssertions, + timing, + Some(CompilationSettings.Parallelism.Uniform(0)) + ) + + @deprecated("avoid use of unapply", "Chisel 7.1.0") + def unapply(compilationSettings: CompilationSettings): Option[ + ( + Option[CompilationSettings.TraceStyle], + Option[Int], + Option[Int], + Seq[String], + Boolean, + Boolean, + Option[CompilationSettings.Timing.Type] + ) + ] = Some( + ( + compilationSettings.traceStyle, + compilationSettings.outputSplit, + compilationSettings.outputSplitCFuncs, + compilationSettings.disabledWarnings, + compilationSettings.disableFatalExitOnWarnings, + compilationSettings.enableAllAssertions, + compilationSettings.timing + ) + ) + } case class CompilationSettings( @@ -101,7 +144,134 @@ object Backend { enableAllAssertions: Boolean = false, timing: Option[CompilationSettings.Timing.Type] = None, parallelism: Option[CompilationSettings.Parallelism.Type] = Some(CompilationSettings.Parallelism.Uniform(0)) - ) extends svsim.Backend.Settings + ) extends svsim.Backend.Settings { + def this( + traceStyle: Option[CompilationSettings.TraceStyle], + outputSplit: Option[Int], + outputSplitCFuncs: Option[Int], + disabledWarnings: Seq[String], + disableFatalExitOnWarnings: Boolean, + enableAllAssertions: Boolean, + timing: Option[CompilationSettings.Timing.Type] + ) = this( + traceStyle, + outputSplit, + outputSplitCFuncs, + disabledWarnings, + disableFatalExitOnWarnings, + enableAllAssertions, + timing, + Some(CompilationSettings.Parallelism.Uniform(0)) + ) + + @deprecated("don't use the copy method, use 'with' single setters", "Chisel 7.1.0") + def copy( + traceStyle: Option[CompilationSettings.TraceStyle] = this.traceStyle, + outputSplit: Option[Int] = this.outputSplit, + outputSplitCFuncs: Option[Int] = this.outputSplitCFuncs, + disabledWarnings: Seq[String] = this.disabledWarnings, + disableFatalExitOnWarnings: Boolean = this.disableFatalExitOnWarnings, + enableAllAssertions: Boolean = this.enableAllAssertions, + timing: Option[CompilationSettings.Timing.Type] = this.timing + ): CompilationSettings = CompilationSettings( + traceStyle = traceStyle, + outputSplit = outputSplit, + outputSplitCFuncs = outputSplitCFuncs, + disabledWarnings = disabledWarnings, + disableFatalExitOnWarnings = disableFatalExitOnWarnings, + enableAllAssertions = enableAllAssertions, + timing = timing, + parallelism = this.parallelism + ) + + def withTraceStyle(traceStyle: Option[CompilationSettings.TraceStyle]) = CompilationSettings( + traceStyle, + this.outputSplit, + this.outputSplitCFuncs, + this.disabledWarnings, + this.disableFatalExitOnWarnings, + this.enableAllAssertions, + this.timing, + this.parallelism + ) + + def withOutputSplit(outputSplit: Option[Int]) = CompilationSettings( + this.traceStyle, + this.outputSplit, + outputSplitCFuncs, + this.disabledWarnings, + this.disableFatalExitOnWarnings, + this.enableAllAssertions, + this.timing, + this.parallelism + ) + + def withOutputSplitCFuncs(outputSplitCFuncs: Option[Int]) = CompilationSettings( + this.traceStyle, + this.outputSplit, + outputSplitCFuncs, + this.disabledWarnings, + this.disableFatalExitOnWarnings, + this.enableAllAssertions, + this.timing, + this.parallelism + ) + + def withDisabledWarnings(disabledWarnings: Seq[String]) = CompilationSettings( + this.traceStyle, + this.outputSplit, + this.outputSplitCFuncs, + disabledWarnings, + this.disableFatalExitOnWarnings, + this.enableAllAssertions, + this.timing, + this.parallelism + ) + + def withDisableFatalExitOnWarnings(disableFatalExitOnWarnings: Boolean) = CompilationSettings( + this.traceStyle, + this.outputSplit, + this.outputSplitCFuncs, + this.disabledWarnings, + disableFatalExitOnWarnings, + this.enableAllAssertions, + this.timing, + this.parallelism + ) + + def withEnableAllAssertions(enableAllAssertions: Boolean) = CompilationSettings( + this.traceStyle, + this.outputSplit, + this.outputSplitCFuncs, + this.disabledWarnings, + this.disableFatalExitOnWarnings, + enableAllAssertions, + this.timing, + this.parallelism + ) + + def withTiming(timing: Option[CompilationSettings.Timing.Type]) = CompilationSettings( + this.traceStyle, + this.outputSplit, + this.outputSplitCFuncs, + this.disabledWarnings, + this.disableFatalExitOnWarnings, + this.enableAllAssertions, + timing, + this.parallelism + ) + + def withParallelism(parallelism: Option[CompilationSettings.Parallelism.Type]) = CompilationSettings( + this.traceStyle, + this.outputSplit, + this.outputSplitCFuncs, + this.disabledWarnings, + this.disableFatalExitOnWarnings, + this.enableAllAssertions, + this.timing, + parallelism + ) + } def initializeFromProcessEnvironment() = { val output = mutable.ArrayBuffer.empty[String] diff --git a/svsim/src/test/scala/BackendSpec.scala b/svsim/src/test/scala/BackendSpec.scala index db3d7620d6a..c1b1aaee55f 100644 --- a/svsim/src/test/scala/BackendSpec.scala +++ b/svsim/src/test/scala/BackendSpec.scala @@ -174,7 +174,7 @@ class VerilatorSpec extends BackendSpec { )( workingDirectoryTag = "verilator", commonSettings = CommonCompilationSettings(), - backendSpecificSettings = compilationSettings.copy(traceStyle = None), + backendSpecificSettings = compilationSettings.withTraceStyle(None), customSimulationWorkingDirectory = None, verbose = false ) From 24ee0e1147d4a5a8605d35413eb46541a366cc08 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Thu, 9 Oct 2025 01:00:13 -0400 Subject: [PATCH 3/9] fixup! [svsim] Add -j, --build-jobs, and --verilate-jobs --- svsim/src/main/scala/verilator/Backend.scala | 24 +++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/svsim/src/main/scala/verilator/Backend.scala b/svsim/src/main/scala/verilator/Backend.scala index 30c96da2737..350ce1974ef 100644 --- a/svsim/src/main/scala/verilator/Backend.scala +++ b/svsim/src/main/scala/verilator/Backend.scala @@ -135,7 +135,7 @@ object Backend { } - case class CompilationSettings( + case class CompilationSettings ( traceStyle: Option[CompilationSettings.TraceStyle] = None, outputSplit: Option[Int] = None, outputSplitCFuncs: Option[Int] = None, @@ -184,6 +184,28 @@ object Backend { parallelism = this.parallelism ) + // Suppress generation of private copy with default arguments by Scala 3 + private def copy( + traceStyle: Option[CompilationSettings.TraceStyle], + outputSplit: Option[Int], + outputSplitCFuncs: Option[Int], + disabledWarnings: Seq[String], + disableFatalExitOnWarnings: Boolean, + enableAllAssertions: Boolean, + timing: Option[CompilationSettings.Timing.Type], + parallelism: Option[CompilationSettings.Parallelism.Type] + ): CompilationSettings = CompilationSettings( + traceStyle = traceStyle, + outputSplit = outputSplit, + outputSplitCFuncs = outputSplitCFuncs, + disabledWarnings = disabledWarnings, + disableFatalExitOnWarnings = disableFatalExitOnWarnings, + enableAllAssertions = enableAllAssertions, + timing = timing, + parallelism = Some(CompilationSettings.Parallelism.Uniform(0)) + ) + + def withTraceStyle(traceStyle: Option[CompilationSettings.TraceStyle]) = CompilationSettings( traceStyle, this.outputSplit, From c633c5553dcb10b4720a7f363c4a0c2d591bbec5 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Thu, 9 Oct 2025 01:05:58 -0400 Subject: [PATCH 4/9] fixup! [svsim] Add -j, --build-jobs, and --verilate-jobs --- svsim/src/main/scala/verilator/Backend.scala | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/svsim/src/main/scala/verilator/Backend.scala b/svsim/src/main/scala/verilator/Backend.scala index 350ce1974ef..1825cef9605 100644 --- a/svsim/src/main/scala/verilator/Backend.scala +++ b/svsim/src/main/scala/verilator/Backend.scala @@ -135,7 +135,7 @@ object Backend { } - case class CompilationSettings ( + case class CompilationSettings( traceStyle: Option[CompilationSettings.TraceStyle] = None, outputSplit: Option[Int] = None, outputSplitCFuncs: Option[Int] = None, @@ -193,7 +193,7 @@ object Backend { disableFatalExitOnWarnings: Boolean, enableAllAssertions: Boolean, timing: Option[CompilationSettings.Timing.Type], - parallelism: Option[CompilationSettings.Parallelism.Type] + parallelism: Option[CompilationSettings.Parallelism.Type] ): CompilationSettings = CompilationSettings( traceStyle = traceStyle, outputSplit = outputSplit, @@ -205,7 +205,6 @@ object Backend { parallelism = Some(CompilationSettings.Parallelism.Uniform(0)) ) - def withTraceStyle(traceStyle: Option[CompilationSettings.TraceStyle]) = CompilationSettings( traceStyle, this.outputSplit, From 6decefdfdf012ff8c4415f390fb9646b4c5f3cf8 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Fri, 10 Oct 2025 00:08:27 -0400 Subject: [PATCH 5/9] fixup! [svsim] Add -j, --build-jobs, and --verilate-jobs --- svsim/src/main/scala/verilator/Backend.scala | 149 ++++++++----------- svsim/src/test/scala/CommandLineSpec.scala | 10 +- 2 files changed, 66 insertions(+), 93 deletions(-) diff --git a/svsim/src/main/scala/verilator/Backend.scala b/svsim/src/main/scala/verilator/Backend.scala index 1825cef9605..820ba95c141 100644 --- a/svsim/src/main/scala/verilator/Backend.scala +++ b/svsim/src/main/scala/verilator/Backend.scala @@ -74,19 +74,41 @@ object Backend { } /** Apply uniform parallelism to Verilation. This maps to `-j`. */ - case class Uniform(num: Int) extends Type { + class Uniform private (num: Int) extends Type { override def toCompileFlags = Seq("-j", num.toString) + + private def copy(num: Int): Uniform = new Uniform(num = num) + + def withNum(num: Int): Uniform = copy(num = num) + } + + object Uniform { + def default: Uniform = new Uniform(num = 0) } /** Apply non-uniform parallelism to Verilation. This allows control of * `--build-jobs` and `--verilate-jobs` separately. */ - case class Different(build: Option[Int] = None, verilate: Option[Int] = None) extends Type { + class Different private (build: Option[Int], verilate: Option[Int]) extends Type { override def toCompileFlags: Seq[String] = { val buildJobs: Seq[String] = build.map(num => Seq("--build-jobs", num.toString)).toSeq.flatten val verilateJobs: Seq[String] = verilate.map(num => Seq("--verilate-jobs", num.toString)).toSeq.flatten buildJobs ++ verilateJobs } + + private def copy(build: Option[Int] = this.build, verilate: Option[Int] = this.verilate): Different = + new Different( + build = build, + verilate = verilate + ) + + def withBuild(build: Option[Int]): Different = copy(build = build) + + def withVerilate(verilate: Option[Int]): Different = copy(verilate = verilate) + } + + object Different { + def default = new Different(build = None, verilate = None) } } @@ -107,7 +129,7 @@ object Backend { disableFatalExitOnWarnings, enableAllAssertions, timing, - Some(CompilationSettings.Parallelism.Uniform(0)) + Some(CompilationSettings.Parallelism.Uniform.default) ) @deprecated("avoid use of unapply", "Chisel 7.1.0") @@ -143,7 +165,7 @@ object Backend { disableFatalExitOnWarnings: Boolean = false, enableAllAssertions: Boolean = false, timing: Option[CompilationSettings.Timing.Type] = None, - parallelism: Option[CompilationSettings.Parallelism.Type] = Some(CompilationSettings.Parallelism.Uniform(0)) + parallelism: Option[CompilationSettings.Parallelism.Type] = Some(CompilationSettings.Parallelism.Uniform.default) ) extends svsim.Backend.Settings { def this( traceStyle: Option[CompilationSettings.TraceStyle], @@ -161,7 +183,27 @@ object Backend { disableFatalExitOnWarnings, enableAllAssertions, timing, - Some(CompilationSettings.Parallelism.Uniform(0)) + Some(CompilationSettings.Parallelism.Uniform.default) + ) + + def _copy( + traceStyle: Option[CompilationSettings.TraceStyle] = this.traceStyle, + outputSplit: Option[Int] = this.outputSplit, + outputSplitCFuncs: Option[Int] = this.outputSplitCFuncs, + disabledWarnings: Seq[String] = this.disabledWarnings, + disableFatalExitOnWarnings: Boolean = this.disableFatalExitOnWarnings, + enableAllAssertions: Boolean = this.enableAllAssertions, + timing: Option[CompilationSettings.Timing.Type] = this.timing, + parallelism: Option[CompilationSettings.Parallelism.Type] = this.parallelism + ): CompilationSettings = CompilationSettings( + traceStyle = traceStyle, + outputSplit = outputSplit, + outputSplitCFuncs = outputSplitCFuncs, + disabledWarnings = disabledWarnings, + disableFatalExitOnWarnings = disableFatalExitOnWarnings, + enableAllAssertions = enableAllAssertions, + timing = timing, + parallelism = parallelism ) @deprecated("don't use the copy method, use 'with' single setters", "Chisel 7.1.0") @@ -173,7 +215,7 @@ object Backend { disableFatalExitOnWarnings: Boolean = this.disableFatalExitOnWarnings, enableAllAssertions: Boolean = this.enableAllAssertions, timing: Option[CompilationSettings.Timing.Type] = this.timing - ): CompilationSettings = CompilationSettings( + ): CompilationSettings = _copy( traceStyle = traceStyle, outputSplit = outputSplit, outputSplitCFuncs = outputSplitCFuncs, @@ -194,7 +236,7 @@ object Backend { enableAllAssertions: Boolean, timing: Option[CompilationSettings.Timing.Type], parallelism: Option[CompilationSettings.Parallelism.Type] - ): CompilationSettings = CompilationSettings( + ): CompilationSettings = _copy( traceStyle = traceStyle, outputSplit = outputSplit, outputSplitCFuncs = outputSplitCFuncs, @@ -202,96 +244,25 @@ object Backend { disableFatalExitOnWarnings = disableFatalExitOnWarnings, enableAllAssertions = enableAllAssertions, timing = timing, - parallelism = Some(CompilationSettings.Parallelism.Uniform(0)) + parallelism = Some(CompilationSettings.Parallelism.Uniform.default) ) - def withTraceStyle(traceStyle: Option[CompilationSettings.TraceStyle]) = CompilationSettings( - traceStyle, - this.outputSplit, - this.outputSplitCFuncs, - this.disabledWarnings, - this.disableFatalExitOnWarnings, - this.enableAllAssertions, - this.timing, - this.parallelism - ) + def withTraceStyle(traceStyle: Option[CompilationSettings.TraceStyle]) = _copy(traceStyle = traceStyle) - def withOutputSplit(outputSplit: Option[Int]) = CompilationSettings( - this.traceStyle, - this.outputSplit, - outputSplitCFuncs, - this.disabledWarnings, - this.disableFatalExitOnWarnings, - this.enableAllAssertions, - this.timing, - this.parallelism - ) + def withOutputSplit(outputSplit: Option[Int]) = _copy(outputSplit = outputSplit) - def withOutputSplitCFuncs(outputSplitCFuncs: Option[Int]) = CompilationSettings( - this.traceStyle, - this.outputSplit, - outputSplitCFuncs, - this.disabledWarnings, - this.disableFatalExitOnWarnings, - this.enableAllAssertions, - this.timing, - this.parallelism - ) + def withOutputSplitCFuncs(outputSplitCFuncs: Option[Int]) = _copy(outputSplitCFuncs = outputSplitCFuncs) - def withDisabledWarnings(disabledWarnings: Seq[String]) = CompilationSettings( - this.traceStyle, - this.outputSplit, - this.outputSplitCFuncs, - disabledWarnings, - this.disableFatalExitOnWarnings, - this.enableAllAssertions, - this.timing, - this.parallelism - ) + def withDisabledWarnings(disabledWarnings: Seq[String]) = _copy(disabledWarnings = disabledWarnings) - def withDisableFatalExitOnWarnings(disableFatalExitOnWarnings: Boolean) = CompilationSettings( - this.traceStyle, - this.outputSplit, - this.outputSplitCFuncs, - this.disabledWarnings, - disableFatalExitOnWarnings, - this.enableAllAssertions, - this.timing, - this.parallelism - ) + def withDisableFatalExitOnWarnings(disableFatalExitOnWarnings: Boolean) = + _copy(disableFatalExitOnWarnings = disableFatalExitOnWarnings) - def withEnableAllAssertions(enableAllAssertions: Boolean) = CompilationSettings( - this.traceStyle, - this.outputSplit, - this.outputSplitCFuncs, - this.disabledWarnings, - this.disableFatalExitOnWarnings, - enableAllAssertions, - this.timing, - this.parallelism - ) + def withEnableAllAssertions(enableAllAssertions: Boolean) = _copy(enableAllAssertions = enableAllAssertions) - def withTiming(timing: Option[CompilationSettings.Timing.Type]) = CompilationSettings( - this.traceStyle, - this.outputSplit, - this.outputSplitCFuncs, - this.disabledWarnings, - this.disableFatalExitOnWarnings, - this.enableAllAssertions, - timing, - this.parallelism - ) + def withTiming(timing: Option[CompilationSettings.Timing.Type]) = _copy(timing = timing) - def withParallelism(parallelism: Option[CompilationSettings.Parallelism.Type]) = CompilationSettings( - this.traceStyle, - this.outputSplit, - this.outputSplitCFuncs, - this.disabledWarnings, - this.disableFatalExitOnWarnings, - this.enableAllAssertions, - this.timing, - parallelism - ) + def withParallelism(parallelism: Option[CompilationSettings.Parallelism.Type]) = _copy(parallelism = parallelism) } def initializeFromProcessEnvironment() = { @@ -338,7 +309,7 @@ final class Backend(executablePath: String) extends svsim.Backend { backendSpecificSettings.parallelism match { case Some(parallelism) => addArg(parallelism.toCompileFlags) - case None => + case None => () } commonSettings.libraryExtensions.foreach { extensions => diff --git a/svsim/src/test/scala/CommandLineSpec.scala b/svsim/src/test/scala/CommandLineSpec.scala index c3366df9244..038f2807a9e 100644 --- a/svsim/src/test/scala/CommandLineSpec.scala +++ b/svsim/src/test/scala/CommandLineSpec.scala @@ -21,22 +21,24 @@ class CommandLineSpec extends AnyFlatSpec with Matchers { OptionTest("default", CompilationSettings(), Seq("-j", "0")), OptionTest( "uniform parallelism", - CompilationSettings(parallelism = Some(Parallelism.Uniform(2))), + CompilationSettings(parallelism = Some(Parallelism.Uniform.default.withNum(2))), Seq("-j", "2") ), OptionTest( "only build parallelism", - CompilationSettings(parallelism = Some(Parallelism.Different(build = Some(4)))), + CompilationSettings(parallelism = Some(Parallelism.Different.default.withBuild(Some(4)))), Seq("--build-jobs", "4") ), OptionTest( "only verilate parallelism", - CompilationSettings(parallelism = Some(Parallelism.Different(verilate = Some(8)))), + CompilationSettings(parallelism = Some(Parallelism.Different.default.withVerilate(Some(8)))), Seq("--verilate-jobs", "8") ), OptionTest( "different build and verilate parallelism", - CompilationSettings(parallelism = Some(Parallelism.Different(build = Some(16), verilate = Some(32)))), + CompilationSettings(parallelism = + Some(Parallelism.Different.default.withBuild(Some(16)).withVerilate(Some(32))) + ), Seq("--build-jobs", "16", "--verilate-jobs", "32") ) ) From f8ed3bb1dafbc8c90194207f541980e51c677f32 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Fri, 10 Oct 2025 00:17:26 -0400 Subject: [PATCH 6/9] fixup! [svsim] Add -j, --build-jobs, and --verilate-jobs --- src/main/scala/chisel3/simulator/HasSimulator.scala | 3 ++- src/test/scala-2/chiselTests/MultiClockSpec.scala | 4 +++- .../chiselTests/simulator/HasSimulatorSpec.scala | 2 +- .../chiselTests/simulator/SimulatorSpec.scala | 2 +- .../simulator/scalatest/ChiselSimSpec.scala | 8 ++++---- svsim/src/main/scala/verilator/Backend.scala | 13 ++++++++++++- svsim/src/test/scala/BackendSpec.scala | 8 ++++---- svsim/src/test/scala/CommandLineSpec.scala | 10 +++++----- 8 files changed, 32 insertions(+), 18 deletions(-) diff --git a/src/main/scala/chisel3/simulator/HasSimulator.scala b/src/main/scala/chisel3/simulator/HasSimulator.scala index d7458481eb4..bc1dde1b996 100644 --- a/src/main/scala/chisel3/simulator/HasSimulator.scala +++ b/src/main/scala/chisel3/simulator/HasSimulator.scala @@ -42,7 +42,8 @@ object HasSimulator { /** A [[HasSimulator]] implementation for a Verilator simulator. */ def verilator( compilationSettings: svsim.CommonCompilationSettings = svsim.CommonCompilationSettings(), - verilatorSettings: svsim.verilator.Backend.CompilationSettings = svsim.verilator.Backend.CompilationSettings() + verilatorSettings: svsim.verilator.Backend.CompilationSettings = + svsim.verilator.Backend.CompilationSettings.default ): HasSimulator = new HasSimulator { override def getSimulator(implicit testingDirectory: HasTestingDirectory): Simulator[svsim.verilator.Backend] = new Simulator[svsim.verilator.Backend] { diff --git a/src/test/scala-2/chiselTests/MultiClockSpec.scala b/src/test/scala-2/chiselTests/MultiClockSpec.scala index 914e8252210..52023239d2f 100644 --- a/src/test/scala-2/chiselTests/MultiClockSpec.scala +++ b/src/test/scala-2/chiselTests/MultiClockSpec.scala @@ -125,7 +125,9 @@ class MultiClockSpec extends AnyFlatSpec with Matchers with LogUtils with Chisel it should "scope ports of memories" in { implicit val verilator = simulators - .verilator(verilatorSettings = svsim.verilator.Backend.CompilationSettings(disabledWarnings = Seq("MULTIDRIVEN"))) + .verilator(verilatorSettings = + svsim.verilator.Backend.CompilationSettings.default.withDisabledWarnings(Seq("MULTIDRIVEN")) + ) simulate(new MultiClockMemTest)(RunUntilFinished(21)) } diff --git a/src/test/scala-2/chiselTests/simulator/HasSimulatorSpec.scala b/src/test/scala-2/chiselTests/simulator/HasSimulatorSpec.scala index d45255f1b81..cd16eda43a2 100644 --- a/src/test/scala-2/chiselTests/simulator/HasSimulatorSpec.scala +++ b/src/test/scala-2/chiselTests/simulator/HasSimulatorSpec.scala @@ -28,7 +28,7 @@ class HasSimulatorSpec extends AnyFunSpec with Matchers { override val backend = svsim.verilator.Backend.initializeFromProcessEnvironment() override val tag = "still-verilator" override val commonCompilationSettings = svsim.CommonCompilationSettings() - override val backendSpecificCompilationSettings = svsim.verilator.Backend.CompilationSettings() + override val backendSpecificCompilationSettings = svsim.verilator.Backend.CompilationSettings.default override val workspacePath = "" } } diff --git a/src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala b/src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala index d5849cfe22e..f4f0d78e66f 100644 --- a/src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala +++ b/src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala @@ -14,7 +14,7 @@ class VerilatorSimulator(val workspacePath: String) extends Simulator[verilator. val backend = verilator.Backend.initializeFromProcessEnvironment() val tag = "verilator" val commonCompilationSettings = CommonCompilationSettings() - val backendSpecificCompilationSettings = verilator.Backend.CompilationSettings() + val backendSpecificCompilationSettings = verilator.Backend.CompilationSettings.default } class SimulatorSpec extends AnyFunSpec with Matchers { diff --git a/src/test/scala-2/chiselTests/simulator/scalatest/ChiselSimSpec.scala b/src/test/scala-2/chiselTests/simulator/scalatest/ChiselSimSpec.scala index ddee38b004b..90fc75d8d2a 100644 --- a/src/test/scala-2/chiselTests/simulator/scalatest/ChiselSimSpec.scala +++ b/src/test/scala-2/chiselTests/simulator/scalatest/ChiselSimSpec.scala @@ -212,8 +212,8 @@ class ChiselSimSpec extends AnyFunSpec with Matchers with ChiselSim with FileChe // Return a Verilator `HasSimulator` that will dump waves to `trace.vcd`. def verilatorWithVcd = HasSimulator.simulators .verilator(verilatorSettings = - svsim.verilator.Backend.CompilationSettings( - traceStyle = Some( + svsim.verilator.Backend.CompilationSettings.default.withTraceStyle( + Some( svsim.verilator.Backend.CompilationSettings .TraceStyle( svsim.verilator.Backend.CompilationSettings.TraceKind.Vcd, @@ -229,8 +229,8 @@ class ChiselSimSpec extends AnyFunSpec with Matchers with ChiselSim with FileChe // Return a Verilator `HasSimulator` that will dump waves to `trace.fst`. def verilatorWithFst = HasSimulator.simulators .verilator(verilatorSettings = - svsim.verilator.Backend.CompilationSettings( - traceStyle = Some( + svsim.verilator.Backend.CompilationSettings.default.withTraceStyle( + Some( svsim.verilator.Backend.CompilationSettings .TraceStyle( svsim.verilator.Backend.CompilationSettings.TraceKind.Fst(Some(2)), diff --git a/svsim/src/main/scala/verilator/Backend.scala b/svsim/src/main/scala/verilator/Backend.scala index 820ba95c141..f83af06aee2 100644 --- a/svsim/src/main/scala/verilator/Backend.scala +++ b/svsim/src/main/scala/verilator/Backend.scala @@ -155,9 +155,20 @@ object Backend { ) ) + def default: CompilationSettings = new CompilationSettings( + traceStyle = None, + outputSplit = None, + outputSplitCFuncs = None, + disabledWarnings = Seq(), + disableFatalExitOnWarnings = false, + enableAllAssertions = false, + timing = None, + parallelism = Some(CompilationSettings.Parallelism.Uniform.default) + ) + } - case class CompilationSettings( + case class CompilationSettings private ( traceStyle: Option[CompilationSettings.TraceStyle] = None, outputSplit: Option[Int] = None, outputSplitCFuncs: Option[Int] = None, diff --git a/svsim/src/test/scala/BackendSpec.scala b/svsim/src/test/scala/BackendSpec.scala index c1b1aaee55f..df92f484b0c 100644 --- a/svsim/src/test/scala/BackendSpec.scala +++ b/svsim/src/test/scala/BackendSpec.scala @@ -155,8 +155,8 @@ class VerilatorSpec extends BackendSpec { import verilator.Backend.CompilationSettings._ val backend = CustomVerilatorBackend(verilator.Backend.initializeFromProcessEnvironment()) - val compilationSettings = verilator.Backend.CompilationSettings( - traceStyle = Some(TraceStyle(TraceKind.Vcd, traceUnderscore = false)) + val compilationSettings = verilator.Backend.CompilationSettings.default.withTraceStyle( + Some(TraceStyle(TraceKind.Vcd, traceUnderscore = false)) ) test("verilator", backend)(compilationSettings) @@ -197,8 +197,8 @@ class VerilatorFstTraceSpec extends BackendSpec { import verilator.Backend.CompilationSettings._ val backend = CustomVerilatorBackend(verilator.Backend.initializeFromProcessEnvironment()) - val compilationSettings = verilator.Backend.CompilationSettings( - traceStyle = Some(TraceStyle(TraceKind.Fst(), traceUnderscore = true)) + val compilationSettings = verilator.Backend.CompilationSettings.default.withTraceStyle( + Some(TraceStyle(TraceKind.Fst(), traceUnderscore = true)) ) test("verilator", backend)(compilationSettings) diff --git a/svsim/src/test/scala/CommandLineSpec.scala b/svsim/src/test/scala/CommandLineSpec.scala index 038f2807a9e..daae7b20b97 100644 --- a/svsim/src/test/scala/CommandLineSpec.scala +++ b/svsim/src/test/scala/CommandLineSpec.scala @@ -18,25 +18,25 @@ class CommandLineSpec extends AnyFlatSpec with Matchers { import svsim.verilator.Backend.CompilationSettings import svsim.verilator.Backend.CompilationSettings.Parallelism Seq( - OptionTest("default", CompilationSettings(), Seq("-j", "0")), + OptionTest("default", CompilationSettings.default, Seq("-j", "0")), OptionTest( "uniform parallelism", - CompilationSettings(parallelism = Some(Parallelism.Uniform.default.withNum(2))), + CompilationSettings.default.withParallelism(Some(Parallelism.Uniform.default.withNum(2))), Seq("-j", "2") ), OptionTest( "only build parallelism", - CompilationSettings(parallelism = Some(Parallelism.Different.default.withBuild(Some(4)))), + CompilationSettings.default.withParallelism(Some(Parallelism.Different.default.withBuild(Some(4)))), Seq("--build-jobs", "4") ), OptionTest( "only verilate parallelism", - CompilationSettings(parallelism = Some(Parallelism.Different.default.withVerilate(Some(8)))), + CompilationSettings.default.withParallelism(Some(Parallelism.Different.default.withVerilate(Some(8)))), Seq("--verilate-jobs", "8") ), OptionTest( "different build and verilate parallelism", - CompilationSettings(parallelism = + CompilationSettings.default.withParallelism( Some(Parallelism.Different.default.withBuild(Some(16)).withVerilate(Some(32))) ), Seq("--build-jobs", "16", "--verilate-jobs", "32") From fa1e718dbed9302f7f20b08c700e0d14f392bef0 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Fri, 10 Oct 2025 00:21:34 -0400 Subject: [PATCH 7/9] fixup! [svsim] Add -j, --build-jobs, and --verilate-jobs --- svsim/src/main/scala/verilator/Backend.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/svsim/src/main/scala/verilator/Backend.scala b/svsim/src/main/scala/verilator/Backend.scala index f83af06aee2..2632c85308e 100644 --- a/svsim/src/main/scala/verilator/Backend.scala +++ b/svsim/src/main/scala/verilator/Backend.scala @@ -168,7 +168,7 @@ object Backend { } - case class CompilationSettings private ( + case class CompilationSettings ( traceStyle: Option[CompilationSettings.TraceStyle] = None, outputSplit: Option[Int] = None, outputSplitCFuncs: Option[Int] = None, From 10d3e57c7570b682a3f54631ccc4d9904469ecfa Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Fri, 10 Oct 2025 01:16:04 -0400 Subject: [PATCH 8/9] fixup! [svsim] Add -j, --build-jobs, and --verilate-jobs --- svsim/src/main/scala/verilator/Backend.scala | 32 ++++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/svsim/src/main/scala/verilator/Backend.scala b/svsim/src/main/scala/verilator/Backend.scala index 2632c85308e..0ff32a5ec6f 100644 --- a/svsim/src/main/scala/verilator/Backend.scala +++ b/svsim/src/main/scala/verilator/Backend.scala @@ -114,13 +114,13 @@ object Backend { @deprecated("use newer CompilationSettings case class apply", "Chisel 7.1.0") def apply( - traceStyle: Option[CompilationSettings.TraceStyle], - outputSplit: Option[Int], - outputSplitCFuncs: Option[Int], - disabledWarnings: Seq[String], - disableFatalExitOnWarnings: Boolean, - enableAllAssertions: Boolean, - timing: Option[CompilationSettings.Timing.Type] + traceStyle: Option[CompilationSettings.TraceStyle] = None, + outputSplit: Option[Int] = None, + outputSplitCFuncs: Option[Int] = None, + disabledWarnings: Seq[String] = Seq(), + disableFatalExitOnWarnings: Boolean = false, + enableAllAssertions: Boolean = false, + timing: Option[CompilationSettings.Timing.Type] = None ): CompilationSettings = CompilationSettings( traceStyle, outputSplit, @@ -168,15 +168,15 @@ object Backend { } - case class CompilationSettings ( - traceStyle: Option[CompilationSettings.TraceStyle] = None, - outputSplit: Option[Int] = None, - outputSplitCFuncs: Option[Int] = None, - disabledWarnings: Seq[String] = Seq(), - disableFatalExitOnWarnings: Boolean = false, - enableAllAssertions: Boolean = false, - timing: Option[CompilationSettings.Timing.Type] = None, - parallelism: Option[CompilationSettings.Parallelism.Type] = Some(CompilationSettings.Parallelism.Uniform.default) + case class CompilationSettings private ( + traceStyle: Option[CompilationSettings.TraceStyle], + outputSplit: Option[Int], + outputSplitCFuncs: Option[Int], + disabledWarnings: Seq[String], + disableFatalExitOnWarnings: Boolean, + enableAllAssertions: Boolean, + timing: Option[CompilationSettings.Timing.Type], + parallelism: Option[CompilationSettings.Parallelism.Type] ) extends svsim.Backend.Settings { def this( traceStyle: Option[CompilationSettings.TraceStyle], From 6fe9612803c196189ef874ae3ccd7ac3bd2c908c Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Fri, 10 Oct 2025 01:24:52 -0400 Subject: [PATCH 9/9] fixup! [svsim] Add -j, --build-jobs, and --verilate-jobs --- svsim/src/main/scala/verilator/Backend.scala | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/svsim/src/main/scala/verilator/Backend.scala b/svsim/src/main/scala/verilator/Backend.scala index 0ff32a5ec6f..1332b088862 100644 --- a/svsim/src/main/scala/verilator/Backend.scala +++ b/svsim/src/main/scala/verilator/Backend.scala @@ -112,7 +112,7 @@ object Backend { } } - @deprecated("use newer CompilationSettings case class apply", "Chisel 7.1.0") + @deprecated("use 'CompilationSettings.default' and 'with' helpers", "Chisel 7.1.0") def apply( traceStyle: Option[CompilationSettings.TraceStyle] = None, outputSplit: Option[Int] = None, @@ -178,14 +178,16 @@ object Backend { timing: Option[CompilationSettings.Timing.Type], parallelism: Option[CompilationSettings.Parallelism.Type] ) extends svsim.Backend.Settings { + + @deprecated("use 'CompilationSettings.default' and 'with' helpers", "Chisel 7.1.0") def this( - traceStyle: Option[CompilationSettings.TraceStyle], - outputSplit: Option[Int], - outputSplitCFuncs: Option[Int], - disabledWarnings: Seq[String], - disableFatalExitOnWarnings: Boolean, - enableAllAssertions: Boolean, - timing: Option[CompilationSettings.Timing.Type] + traceStyle: Option[CompilationSettings.TraceStyle] = None, + outputSplit: Option[Int] = None, + outputSplitCFuncs: Option[Int] = None, + disabledWarnings: Seq[String] = Seq(), + disableFatalExitOnWarnings: Boolean = false, + enableAllAssertions: Boolean = false, + timing: Option[CompilationSettings.Timing.Type] = None ) = this( traceStyle, outputSplit,