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Commit d629ae9

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author
Figueroa
committed
work in progress, adds eeprom_direct lcov
1 parent 66416e2 commit d629ae9

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+82
-16
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+82
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unit-test-coverage/modules/eeprom_direct/coveragetest-eeprom_direct.c

+82-16
Original file line numberDiff line numberDiff line change
@@ -43,31 +43,96 @@
4343
#include "cfe_psp_config.h"
4444
#include "cfe_psp_module.h"
4545

46+
#define UT_RAMBLOCK_SIZE 32
47+
48+
static union
49+
{
50+
uint8 u8[UT_RAMBLOCK_SIZE];
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uint16 u16[UT_RAMBLOCK_SIZE / sizeof(uint16)];
52+
uint32 u32[UT_RAMBLOCK_SIZE / sizeof(uint32)];
53+
} UT_RAM_BLOCK;
54+
4655
extern void eeprom_direct_Init(uint32 PspModuleId);
4756

57+
/*
58+
* --------------------------------------------
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* TEST FUNCTIONS
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* --------------------------------------------
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*/
62+
63+
/* ********************************
64+
* eeprom_direct_Init
65+
* ********************************/
4866
void Test_eeprom_direct_Init(void)
4967
{
50-
/*
51-
void eeprom_direct_Init(uint32 PspModuleId)
52-
*/
53-
68+
/* Test For:
69+
* void eeprom_direct_Init(uint32 PspModuleId)
70+
*/
5471
UtAssert_VOIDCALL(eeprom_direct_Init(1));
5572
}
5673

57-
void Test_CFE_PSP_EepromWrite32(void)
74+
/* ********************************
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* CFE_PSP_EepromWrite32
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* ********************************/
77+
void Test_CFE_PSP_EepromWrite32_Nominal(void)
5878
{
59-
/*
60-
int32 CFE_PSP_EepromWrite32(cpuaddr MemoryAddress, uint32 uint32Value)
61-
*/
62-
UtAssert_INT32_EQ(CFE_PSP_EepromWrite32(0, 1), CFE_PSP_SUCCESS);
79+
/* Arrange */
80+
cpuaddr UtAddress;
81+
uint32 writevalue;
82+
83+
UtAddress = (cpuaddr)&UT_RAM_BLOCK.u32[0] + 1;
84+
writevalue = 0x12345678;
85+
86+
/* Act */
87+
UtAssert_INT32_EQ(CFE_PSP_EepromWrite32(UtAddress, writevalue), CFE_PSP_SUCCESS);
88+
89+
/* Assert */
90+
UtAssert_INT32_EQ(*((uint32 *)UtAddress), writevalue);
6391
}
6492

65-
void Test_CFE_PSP_EepromWrite16(void)
93+
void Test_CFE_PSP_EepromWrite32_AddressMisaligned(void)
6694
{
67-
/*
68-
int32 CFE_PSP_EepromWrite16(cpuaddr MemoryAddress, uint16 uint16Value)
69-
*/
70-
UtAssert_INT32_EQ(CFE_PSP_EepromWrite16(0, 1), CFE_PSP_SUCCESS);
95+
/* Arrange */
96+
cpuaddr UtAddress;
97+
uint32 writevalue;
98+
99+
UtAddress = (cpuaddr)&UT_RAM_BLOCK.u32[1];
100+
writevalue = 0x12345678;
101+
102+
/* Act */
103+
UtAssert_INT32_EQ(CFE_PSP_EepromWrite32(UtAddress, writevalue), CFE_PSP_ERROR_ADDRESS_MISALIGNED);
104+
}
105+
106+
/* ********************************
107+
* CFE_PSP_EepromWrite16
108+
* ********************************/
109+
void Test_CFE_PSP_EepromWrite16_Nominal(void)
110+
{
111+
/* Arrange */
112+
cpuaddr UtAddress;
113+
uint32 writevalue;
114+
115+
UtAddress = (cpuaddr)&UT_RAM_BLOCK.u16[4];
116+
writevalue = 0x12345678;
117+
118+
/* Act */
119+
UtAssert_INT32_EQ(CFE_PSP_EepromWrite16(UtAddress, writevalue), CFE_PSP_SUCCESS);
120+
121+
/* Assert */
122+
UtAssert_INT32_EQ(*((uint32 *)UtAddress), writevalue);
123+
}
124+
125+
void Test_CFE_PSP_EepromWrite16_AddressMisaligned(void)
126+
{
127+
/* Arrange */
128+
cpuaddr UtAddress;
129+
uint32 writevalue;
130+
131+
UtAddress = (cpuaddr)&UT_RAM_BLOCK.u16[5] + 2; // Add 2 bytes to make the 2nd LSB equal to 1
132+
writevalue = 0x12345678;
133+
134+
/* Act */
135+
UtAssert_INT32_EQ(CFE_PSP_EepromWrite16(UtAddress, writevalue), CFE_PSP_ERROR_ADDRESS_MISALIGNED);
71136
}
72137

73138
void Test_CFE_PSP_EepromWrite8(void)
@@ -121,8 +186,9 @@ void Test_CFE_PSP_EepromPowerDown(void)
121186
void UtTest_Setup(void)
122187
{
123188
ADD_TEST(Test_eeprom_direct_Init);
124-
ADD_TEST(Test_CFE_PSP_EepromWrite32);
125-
ADD_TEST(Test_CFE_PSP_EepromWrite16);
189+
ADD_TEST(Test_CFE_PSP_EepromWrite32_Nominal);
190+
ADD_TEST(Test_CFE_PSP_EepromWrite32_AddressMisaligned);
191+
ADD_TEST(Test_CFE_PSP_EepromWrite16_Nominal);
126192
ADD_TEST(Test_CFE_PSP_EepromWrite8);
127193
ADD_TEST(Test_CFE_PSP_EepromWriteEnable);
128194
ADD_TEST(Test_CFE_PSP_EepromWriteDisable);

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