bump

Author: sequencer

build.sbt

@@ -27,7 +27,7 @@ lazy val chiselv = (project in file("."))
 
 // Default library versions
 val defaultVersions = Map(
-  "chisel3"          -> "3.5.0-RC1",
+  "chisel3"          -> "3.5.0-RC2",
   "chiseltest"       -> "0.5-SNAPSHOT",
   "scalatest"        -> "3.2.10",
   "organize-imports" -> "0.5.0",

src/main/scala/MemoryIOManager.scala

@@ -91,7 +91,7 @@ class MemoryIOManager(bitWidth: Int = 32, clockFreq: Long, sizeBytes: Long = 102
     // Dummy output - (0x0000_1000)
     when(readAddress(11, 0) === 0x0L.U)(dataOut := 0xbaad_cafeL.U)
     // Clock frequency - (0x0000_1008)
-    when(readAddress(11, 0) === 0x8L.U)(dataOut := clockFreq.asUInt())
+    when(readAddress(11, 0) === 0x8L.U)(dataOut := clockFreq.asUInt)
     // Has UART0 - (0x0000_1010)
     when(readAddress(11, 0) === 0x10L.U)(dataOut := 1.U)
     // Has GPIO0 - (0x0000_1018)
@@ -101,7 +101,7 @@ class MemoryIOManager(bitWidth: Int = 32, clockFreq: Long, sizeBytes: Long = 102
     // Has Timer0 - (0x0000_1024)
     when(readAddress(11, 0) === 0x24L.U)(dataOut := 1.U)
     // Num GPIOs in GPIO0 - (0x0000_1028)
-    when(readAddress(11, 0) === 0x28L.U)(dataOut := numGPIO0.asUInt())
+    when(readAddress(11, 0) === 0x28L.U)(dataOut := numGPIO0.asUInt)
 
   }