diff --git a/arch/MOS65XX/MOS65XXDisassembler.c b/arch/MOS65XX/MOS65XXDisassembler.c
index f9a5cf9cf7..8a0568c788 100644
--- a/arch/MOS65XX/MOS65XXDisassembler.c
+++ b/arch/MOS65XX/MOS65XXDisassembler.c
@@ -203,7 +203,7 @@ static void fillDetails(MCInst *MI, struct OpInfo opinfo, int cpu_type)
 			break;
 		case MOS65XX_AM_IMM:
 			detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_IMM;
-			detail->mos65xx.operands[detail->mos65xx.op_count].mem = MI->Operands[0].ImmVal;
+			detail->mos65xx.operands[detail->mos65xx.op_count].imm = MI->Operands[0].ImmVal;
 			detail->mos65xx.op_count++;
 			break;
 		case MOS65XX_AM_ACC:
@@ -211,7 +211,27 @@ static void fillDetails(MCInst *MI, struct OpInfo opinfo, int cpu_type)
 			detail->mos65xx.operands[detail->mos65xx.op_count].reg = MOS65XX_REG_ACC;
 			detail->mos65xx.op_count++;
 			break;
-
+		case MOS65XX_AM_REL: {
+			int value = MI->Operands[0].ImmVal;
+			if (MI->op1_size == 1)
+				value = 2 + (signed char)value;
+			else
+				value = 3 + (signed short)value;
+			detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM;
+			detail->mos65xx.operands[detail->mos65xx.op_count].mem = (MI->address + value) & 0xffff;
+			detail->mos65xx.op_count++;
+			break;
+		}
+		case MOS65XX_AM_ZP_REL: {
+			int value =	3 + (signed char)MI->Operands[1].ImmVal;
+			/* BBR0, zp, rel  and BBS0, zp, rel */
+			detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM;
+			detail->mos65xx.operands[detail->mos65xx.op_count].mem = MI->Operands[0].ImmVal;
+			detail->mos65xx.operands[detail->mos65xx.op_count+1].type = MOS65XX_OP_MEM;
+			detail->mos65xx.operands[detail->mos65xx.op_count+1].mem = (MI->address + value) & 0xffff;
+			detail->mos65xx.op_count+=2;
+			break;
+		}
 		default:
 			for (i = 0; i < MI->size; ++i) {
 				detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM;
diff --git a/include/capstone/mos65xx.h b/include/capstone/mos65xx.h
index ebdb3439a8..13c2788a3e 100644
--- a/include/capstone/mos65xx.h
+++ b/include/capstone/mos65xx.h
@@ -182,7 +182,7 @@ typedef struct cs_mos65xx_op {
 	union {
 		mos65xx_reg reg;	///< register value for REG operand
 		uint16_t imm;		///< immediate value for IMM operand
-		uint32_t mem;		///< base/index/scale/disp value for MEM operand
+		uint32_t mem;		///< address for MEM operand
 	};
 } cs_mos65xx_op;
 
diff --git a/tests/test_mos65xx.c b/tests/test_mos65xx.c
index cc31de8034..6053c81c1f 100644
--- a/tests/test_mos65xx.c
+++ b/tests/test_mos65xx.c
@@ -135,7 +135,7 @@ static void test()
 
 #define MW65C02_CODE \
 	"\x07\x12\x27\x12\x47\x12\x67\x12\x87\x12\xa7\x12\xc7\x12\xe7\x12" \
-	"\x0f\x12\xfd\x4f\x12\xfd\x8f\x12\xfd\xcf\x12\xfd"
+	"\x10\xfe\x0f\x12\xfd\x4f\x12\xfd\x8f\x12\xfd\xcf\x12\xfd"
 
 #define M65816_CODE \
 	"\xa9\x34\x12" "\xad\x34\x12" "\xbd\x34\x12" "\xb9\x34\x12" \