From c180bc7f2beb0de0141d491469fda8fbfa11f820 Mon Sep 17 00:00:00 2001
From: Eric Kilmer <eric.d.kilmer@gmail.com>
Date: Fri, 8 May 2020 16:08:52 -0400
Subject: [PATCH 1/3] Fix #1627

---
 arch/AArch64/AArch64GenAsmWriter.inc  | 72 +++++++++++++++++++++++++++
 arch/AArch64/AArch64MappingInsnOp.inc |  4 +-
 2 files changed, 74 insertions(+), 2 deletions(-)

diff --git a/arch/AArch64/AArch64GenAsmWriter.inc b/arch/AArch64/AArch64GenAsmWriter.inc
index 15633f7e30..b976446ee0 100644
--- a/arch/AArch64/AArch64GenAsmWriter.inc
+++ b/arch/AArch64/AArch64GenAsmWriter.inc
@@ -14993,6 +14993,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 64 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR)
@@ -15006,6 +15008,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR)
@@ -15019,6 +15023,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 64 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR)
@@ -15032,6 +15038,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR)
@@ -15045,6 +15053,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR)
@@ -15058,6 +15068,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 64 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR)
@@ -15071,6 +15083,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR)
@@ -15084,6 +15098,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 64 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR)
@@ -15145,6 +15161,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR)
@@ -15158,6 +15176,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR)
@@ -15171,6 +15191,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR)
@@ -15184,6 +15206,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR)
@@ -15197,6 +15221,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR)
@@ -15210,6 +15236,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR)
@@ -15223,6 +15251,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR)
@@ -15236,6 +15266,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR)
@@ -15769,6 +15801,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 48 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR)
@@ -15782,6 +15816,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 24 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR)
@@ -15795,6 +15831,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 48 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR)
@@ -15808,6 +15846,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 24 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR)
@@ -15821,6 +15861,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 24 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR)
@@ -15834,6 +15876,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 48 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR)
@@ -15847,6 +15891,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 24 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR)
@@ -15860,6 +15906,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 48 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR)
@@ -15873,6 +15921,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR)
@@ -15886,6 +15936,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR)
@@ -15899,6 +15951,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR)
@@ -15912,6 +15966,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR)
@@ -15925,6 +15981,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR)
@@ -15938,6 +15996,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR)
@@ -15951,6 +16011,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR)
@@ -15964,6 +16026,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR)
@@ -16009,6 +16073,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2 &&
         MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR)
@@ -16022,6 +16088,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4 &&
         MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR)
@@ -16035,6 +16103,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8 &&
         MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR)
@@ -16048,6 +16118,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 &&
         MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR)
diff --git a/arch/AArch64/AArch64MappingInsnOp.inc b/arch/AArch64/AArch64MappingInsnOp.inc
index 49449a406f..c7579a8e1c 100644
--- a/arch/AArch64/AArch64MappingInsnOp.inc
+++ b/arch/AArch64/AArch64MappingInsnOp.inc
@@ -8495,7 +8495,7 @@
 
 {	/* AArch64_LD1Fourv1d, AArch64_INS_LD1: ld1 */
 	0,
-	{ CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ,  0 }
+	{ CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 }
 },
 
 {	/* AArch64_LD1Fourv1d_POST, AArch64_INS_LD1: ld1 */
@@ -8620,7 +8620,7 @@
 
 {	/* AArch64_LD1Onev2d_POST, AArch64_INS_LD1: ld1 */
 	0,
-	{ CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ }
+	{ CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 }
 },
 
 {	/* AArch64_LD1Onev2s, AArch64_INS_LD1: ld1 */

From aa4b8c060d2962f1d361e94cfadcfc421ddf3c3b Mon Sep 17 00:00:00 2001
From: Eric Kilmer <eric.d.kilmer@gmail.com>
Date: Sat, 9 May 2020 18:19:47 -0400
Subject: [PATCH 2/3] Revert "Fix #1627"

This reverts commit c180bc7f2beb0de0141d491469fda8fbfa11f820.
---
 arch/AArch64/AArch64GenAsmWriter.inc  | 72 ---------------------------
 arch/AArch64/AArch64MappingInsnOp.inc |  4 +-
 2 files changed, 2 insertions(+), 74 deletions(-)

diff --git a/arch/AArch64/AArch64GenAsmWriter.inc b/arch/AArch64/AArch64GenAsmWriter.inc
index b976446ee0..15633f7e30 100644
--- a/arch/AArch64/AArch64GenAsmWriter.inc
+++ b/arch/AArch64/AArch64GenAsmWriter.inc
@@ -14993,8 +14993,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 64 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR)
@@ -15008,8 +15006,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR)
@@ -15023,8 +15019,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 64 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR)
@@ -15038,8 +15032,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR)
@@ -15053,8 +15045,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR)
@@ -15068,8 +15058,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 64 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR)
@@ -15083,8 +15071,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR)
@@ -15098,8 +15084,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 64 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR)
@@ -15161,8 +15145,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR)
@@ -15176,8 +15158,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR)
@@ -15191,8 +15171,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR)
@@ -15206,8 +15184,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR)
@@ -15221,8 +15197,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR)
@@ -15236,8 +15210,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR)
@@ -15251,8 +15223,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR)
@@ -15266,8 +15236,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR)
@@ -15801,8 +15769,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 48 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR)
@@ -15816,8 +15782,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 24 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR)
@@ -15831,8 +15795,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 48 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR)
@@ -15846,8 +15808,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 24 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR)
@@ -15861,8 +15821,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 24 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR)
@@ -15876,8 +15834,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 48 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR)
@@ -15891,8 +15847,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 24 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR)
@@ -15906,8 +15860,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 48 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR)
@@ -15921,8 +15873,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR)
@@ -15936,8 +15886,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR)
@@ -15951,8 +15899,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR)
@@ -15966,8 +15912,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR)
@@ -15981,8 +15925,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR)
@@ -15996,8 +15938,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR)
@@ -16011,8 +15951,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR)
@@ -16026,8 +15964,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32 &&
         MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR)
@@ -16073,8 +16009,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2 &&
         MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR)
@@ -16088,8 +16022,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4 &&
         MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR)
@@ -16103,8 +16035,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8 &&
         MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR)
@@ -16118,8 +16048,6 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
         GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
         MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
         GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
-        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 &&
         MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR &&
         AArch64_getFeatureBits(AArch64_FeatureNEON)) {
       // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR)
diff --git a/arch/AArch64/AArch64MappingInsnOp.inc b/arch/AArch64/AArch64MappingInsnOp.inc
index c7579a8e1c..49449a406f 100644
--- a/arch/AArch64/AArch64MappingInsnOp.inc
+++ b/arch/AArch64/AArch64MappingInsnOp.inc
@@ -8495,7 +8495,7 @@
 
 {	/* AArch64_LD1Fourv1d, AArch64_INS_LD1: ld1 */
 	0,
-	{ CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 }
+	{ CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ,  0 }
 },
 
 {	/* AArch64_LD1Fourv1d_POST, AArch64_INS_LD1: ld1 */
@@ -8620,7 +8620,7 @@
 
 {	/* AArch64_LD1Onev2d_POST, AArch64_INS_LD1: ld1 */
 	0,
-	{ CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 }
+	{ CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ }
 },
 
 {	/* AArch64_LD1Onev2s, AArch64_INS_LD1: ld1 */

From b180fab2d562e04cddac17b039c333a7135c8d26 Mon Sep 17 00:00:00 2001
From: Eric Kilmer <eric.d.kilmer@gmail.com>
Date: Sat, 9 May 2020 18:18:54 -0400
Subject: [PATCH 3/3] Add more cases for LD1 instruction immediate fixups

---
 arch/AArch64/AArch64InstPrinter.c | 42 +++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c
index 0965e2782a..0dc399a776 100644
--- a/arch/AArch64/AArch64InstPrinter.c
+++ b/arch/AArch64/AArch64InstPrinter.c
@@ -638,18 +638,60 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
 
 		switch(MCInst_getOpcode(MI)) {
 			default: break;
+			case AArch64_LD1i8_POST:
+				 arm64_op_addImm(MI, 1);
+				 break;
+			case AArch64_LD1i16_POST:
+				 arm64_op_addImm(MI, 2);
+				 break;
+			case AArch64_LD1i32_POST:
+				 arm64_op_addImm(MI, 4);
+				 break;
 			case AArch64_LD1Onev1d_POST:
 			case AArch64_LD1Onev2s_POST:
 			case AArch64_LD1Onev4h_POST:
 			case AArch64_LD1Onev8b_POST:
+			case AArch64_LD1i64_POST:
 				 arm64_op_addImm(MI, 8);
 				 break;
 			case AArch64_LD1Onev16b_POST:
 			case AArch64_LD1Onev2d_POST:
 			case AArch64_LD1Onev4s_POST:
 			case AArch64_LD1Onev8h_POST:
+			case AArch64_LD1Twov1d_POST:
+			case AArch64_LD1Twov2s_POST:
+			case AArch64_LD1Twov4h_POST:
+			case AArch64_LD1Twov8b_POST:
 				 arm64_op_addImm(MI, 16);
 				 break;
+			case AArch64_LD1Threev1d_POST:
+			case AArch64_LD1Threev2s_POST:
+			case AArch64_LD1Threev4h_POST:
+			case AArch64_LD1Threev8b_POST:
+				 arm64_op_addImm(MI, 24);
+				 break;
+			case AArch64_LD1Fourv1d_POST:
+			case AArch64_LD1Fourv2s_POST:
+			case AArch64_LD1Fourv4h_POST:
+			case AArch64_LD1Fourv8b_POST:
+			case AArch64_LD1Twov16b_POST:
+			case AArch64_LD1Twov2d_POST:
+			case AArch64_LD1Twov4s_POST:
+			case AArch64_LD1Twov8h_POST:
+				 arm64_op_addImm(MI, 32);
+				 break;
+			case AArch64_LD1Threev16b_POST:
+			case AArch64_LD1Threev2d_POST:
+			case AArch64_LD1Threev4s_POST:
+			case AArch64_LD1Threev8h_POST:
+				 arm64_op_addImm(MI, 48);
+				 break;
+			case AArch64_LD1Fourv16b_POST:
+			case AArch64_LD1Fourv2d_POST:
+			case AArch64_LD1Fourv4s_POST:
+			case AArch64_LD1Fourv8h_POST:
+				 arm64_op_addImm(MI, 64);
+				 break;
 			case AArch64_UMOVvi64:
 				 arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D);
 				 break;