From 548cc2330d0355e4797113e51eb63c3ec4ef877e Mon Sep 17 00:00:00 2001
From: elp0t0r1c0 <elpotorico@protonmail.com>
Date: Mon, 30 Mar 2020 17:36:20 +0200
Subject: [PATCH] ARM64: Populate implicitly used/modified registers and map
 ARM64_GRP_CALL to BL*

This commit adds some registers to the list of implicit used registers and
implicit modified registers for several AArch64 instructions.

This commit also maps the `ARM64_GRP_CALL` group to the BL* instruction family.
It should fix issue #1606.
---
 arch/AArch64/AArch64MappingInsn.inc | 52 ++++++++++++++---------------
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/arch/AArch64/AArch64MappingInsn.inc b/arch/AArch64/AArch64MappingInsn.inc
index 9a3f6dc3a1..f9e599d52b 100644
--- a/arch/AArch64/AArch64MappingInsn.inc
+++ b/arch/AArch64/AArch64MappingInsn.inc
@@ -1042,21 +1042,21 @@
 {
 	AArch64_AUTIA1716, ARM64_INS_AUTIA1716,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
+	{ ARM64_REG_X16, ARM64_REG_X17, 0 }, { ARM64_REG_X17, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
 {
 	AArch64_AUTIASP, ARM64_INS_AUTIASP,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
+	{ ARM64_REG_LR, ARM64_REG_SP, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
 {
 	AArch64_AUTIAZ, ARM64_INS_AUTIAZ,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
+	{ ARM64_REG_LR, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
@@ -1070,21 +1070,21 @@
 {
 	AArch64_AUTIB1716, ARM64_INS_AUTIB1716,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
+	{ ARM64_REG_X16, ARM64_REG_X17, 0 }, { ARM64_REG_X17, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
 {
 	AArch64_AUTIBSP, ARM64_INS_AUTIBSP,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
+	{ ARM64_REG_LR, ARM64_REG_SP, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
 {
 	AArch64_AUTIBZ, ARM64_INS_AUTIBZ,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
+	{ ARM64_REG_LR, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
@@ -1280,42 +1280,42 @@
 {
 	AArch64_BL, ARM64_INS_BL,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
+	{ 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
 #endif
 },
 
 {
 	AArch64_BLR, ARM64_INS_BLR,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 1
+	{ 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 1
 #endif
 },
 
 {
 	AArch64_BLRAA, ARM64_INS_BLRAA,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0
+	{ 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
 {
 	AArch64_BLRAAZ, ARM64_INS_BLRAAZ,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0
+	{ 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
 {
 	AArch64_BLRAB, ARM64_INS_BLRAB,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0
+	{ 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
 {
 	AArch64_BLRABZ, ARM64_INS_BLRABZ,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0
+	{ 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
@@ -1637,28 +1637,28 @@
 {
 	AArch64_CBNZW, ARM64_INS_CBNZ,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
+	{ ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
 #endif
 },
 
 {
 	AArch64_CBNZX, ARM64_INS_CBNZ,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
+	{ ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
 #endif
 },
 
 {
 	AArch64_CBZW, ARM64_INS_CBZ,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
+	{ ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
 #endif
 },
 
 {
 	AArch64_CBZX, ARM64_INS_CBZ,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
+	{ ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
 #endif
 },
 
@@ -4255,14 +4255,14 @@
 {
 	AArch64_ERETAA, ARM64_INS_ERETAA,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
+	{ ARM64_REG_LR, ARM64_REG_SP, 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
 {
 	AArch64_ERETAB, ARM64_INS_ERETAB,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
+	{ ARM64_REG_LR, ARM64_REG_SP, 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
@@ -17464,21 +17464,21 @@
 {
 	AArch64_PACIA1716, ARM64_INS_PACIA1716,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
+	{ ARM64_REG_X17, 0 }, { ARM64_REG_X16, ARM64_REG_X17, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
 {
 	AArch64_PACIASP, ARM64_INS_PACIASP,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
+	{ ARM64_REG_LR, 0 }, { ARM64_REG_LR, ARM64_REG_SP, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
 {
 	AArch64_PACIAZ, ARM64_INS_PACIAZ,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
+	{ ARM64_REG_LR, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
@@ -17492,21 +17492,21 @@
 {
 	AArch64_PACIB1716, ARM64_INS_PACIB1716,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
+	{ ARM64_REG_X17, 0 }, { ARM64_REG_X16, ARM64_REG_X17, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
 {
 	AArch64_PACIBSP, ARM64_INS_PACIBSP,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
+	{ ARM64_REG_LR, 0 }, { ARM64_REG_LR, ARM64_REG_SP, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
 {
 	AArch64_PACIBZ, ARM64_INS_PACIBZ,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
+	{ ARM64_REG_LR, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0
 #endif
 },
 
@@ -18108,14 +18108,14 @@
 {
 	AArch64_RETAA, ARM64_INS_RETAA,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, ARM64_GRP_RET, 0 }, 0, 0
+	{ ARM64_REG_LR, ARM64_REG_SP, 0 }, { 0 }, { ARM64_GRP_PAC, ARM64_GRP_RET, 0 }, 0, 0
 #endif
 },
 
 {
 	AArch64_RETAB, ARM64_INS_RETAB,
 #ifndef CAPSTONE_DIET
-	{ 0 }, { 0 }, { ARM64_GRP_PAC, ARM64_GRP_RET,0 }, 0, 0
+	{ ARM64_REG_LR, ARM64_REG_SP, 0 }, { 0 }, { ARM64_GRP_PAC, ARM64_GRP_RET, 0 }, 0, 0
 #endif
 },