From 9c0cf3e801bc78a1e637bc2ec4b066cc0e8f8d79 Mon Sep 17 00:00:00 2001 From: billow Date: Sun, 19 Nov 2023 12:48:45 -0800 Subject: [PATCH] Fix tricore UB --- arch/TriCore/TriCoreInstPrinter.c | 189 ++++++++++++++++------------ bindings/python/capstone/tricore.py | 4 +- bindings/python/test_tricore.py | 6 +- cstool/cstool_tricore.c | 7 +- include/capstone/tricore.h | 4 +- suite/MC/TriCore/tc110.s.cs | 2 +- suite/MC/TriCore/tc120.s.cs | 2 +- suite/MC/TriCore/tc130.s.cs | 2 +- suite/MC/TriCore/tc131.s.cs | 2 +- suite/MC/TriCore/tc160.s.cs | 2 +- suite/MC/TriCore/tc161.s.cs | 2 +- suite/MC/TriCore/tc162.s.cs | 2 +- suite/cstest/src/capstone_test.c | 5 + tests/test_tricore.c | 9 +- 14 files changed, 135 insertions(+), 103 deletions(-) diff --git a/arch/TriCore/TriCoreInstPrinter.c b/arch/TriCore/TriCoreInstPrinter.c index 679ca709c1..ee4418b765 100644 --- a/arch/TriCore/TriCoreInstPrinter.c +++ b/arch/TriCore/TriCoreInstPrinter.c @@ -17,16 +17,11 @@ #ifdef CAPSTONE_HAS_TRICORE #include -#include -#include -#include #include "../../MCInst.h" -#include "../../MCRegisterInfo.h" #include "../../Mapping.h" #include "../../MathExtras.h" -#include "../../SStream.h" -#include "../../utils.h" + #include "TriCoreMapping.h" #include "TriCoreLinkage.h" @@ -44,9 +39,41 @@ static void printOperand(MCInst *MI, int OpNum, SStream *O); #include "TriCoreGenRegisterInfo.inc" -static bool fill_mem(MCInst *MI, unsigned int reg, int32_t disp); +static uint32_t to_u32(int64_t x) +{ + if (x > UINT32_MAX || x < -(int64_t)(UINT32_MAX)) { + abort(); + } + return (uint32_t)x; +} + +static inline unsigned int get_msb(uint64_t value) +{ + unsigned int msb = 0; + while (value > 0) { + value >>= 1; // Shift bits to the right + msb++; // Increment the position of the MSB + } + return msb; +} + +static inline int64_t sign_ext64(int64_t imm, unsigned n) +{ + n = get_msb(imm) > n ? get_msb(imm) : n; + int64_t mask = 1 << (n - 1); + return (imm ^ mask) - mask; +} + +static inline int32_t sign_ext32(int32_t imm, unsigned n) +{ + n = get_msb(imm) > n ? get_msb(imm) : n; + int32_t mask = 1 << (n - 1); + return (imm ^ mask) - mask; +} + +static bool fill_mem(MCInst *MI, unsigned int reg, int64_t disp); -static inline void set_mem(cs_tricore_op *op, uint8_t base, int32_t disp) +static inline void set_mem(cs_tricore_op *op, uint8_t base, int64_t disp) { op->type |= TRICORE_OP_MEM; op->mem.base = base; @@ -63,7 +90,7 @@ static inline void fill_reg(MCInst *MI, uint32_t reg) TriCore_inc_op_count(MI); } -static inline void fill_imm(MCInst *MI, int32_t imm) +static inline void fill_imm(MCInst *MI, int64_t imm) { if (!detail_is_set(MI)) return; @@ -80,7 +107,7 @@ static inline void fill_imm(MCInst *MI, int32_t imm) tricore->op_count++; } -static bool fill_mem(MCInst *MI, unsigned int reg, int32_t disp) +static bool fill_mem(MCInst *MI, unsigned int reg, int64_t disp) { if (!detail_is_set(MI)) return false; @@ -166,42 +193,24 @@ static void printOperand(MCInst *MI, int OpNum, SStream *O) fill_reg(MI, reg); } else if (MCOperand_isImm(Op)) { int64_t Imm = MCOperand_getImm(Op); - printInt64Bang(O, Imm); - fill_imm(MI, (int32_t)Imm); + printUInt32Bang(O, to_u32(Imm)); + fill_imm(MI, Imm); } } -static inline unsigned int get_msb(unsigned int value) -{ - unsigned int msb = 0; - while (value > 0) { - value >>= 1; // Shift bits to the right - msb++; // Increment the position of the MSB - } - return msb; -} - -static inline int32_t sign_ext_n(int32_t imm, unsigned n) -{ - n = get_msb(imm) > n ? get_msb(imm) : n; - int32_t mask = 1 << (n - 1); - int32_t sign_extended = (imm ^ mask) - mask; - return sign_extended; -} - static void print_sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) { MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { - int32_t imm = (int32_t)MCOperand_getImm(MO); - imm = sign_ext_n(imm, n); - printInt32Bang(O, imm); - fill_imm(MI, imm); + int64_t imm = MCOperand_getImm(MO); + int32_t res = sign_ext32(to_u32(imm), n); + printInt32Bang(O, res); + fill_imm(MI, res); } else printOperand(MI, OpNum, O); } -static void off4_fixup(MCInst *MI, uint64_t *off4) +static void off4_fixup(MCInst *MI, int64_t *off4) { switch (MCInst_getOpcode(MI)) { case TRICORE_LD_A_slro: @@ -212,27 +221,27 @@ static void off4_fixup(MCInst *MI, uint64_t *off4) case TRICORE_ST_A_ssro: case TRICORE_ST_W_sro: case TRICORE_ST_W_ssro: { - *off4 *= 4; + *off4 = *off4 * 4; break; } case TRICORE_LD_H_sro: case TRICORE_LD_H_slro: case TRICORE_ST_H_sro: case TRICORE_ST_H_ssro: { - *off4 *= 2; + *off4 = *off4 * 2; break; } } } -static void const8_fixup(MCInst *MI, uint64_t *const8) +static void const8_fixup(MCInst *MI, int64_t *const8) { switch (MCInst_getOpcode(MI)) { case TRICORE_LD_A_sc: case TRICORE_ST_A_sc: case TRICORE_ST_W_sc: case TRICORE_LD_W_sc: { - *const8 *= 4; + *const8 = *const8 * 4; break; } } @@ -242,9 +251,9 @@ static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) { MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { - uint64_t imm = MCOperand_getImm(MO); + int64_t imm = MCOperand_getImm(MO); for (unsigned i = n + 1; i < 32; ++i) { - imm &= ~(1 << i); + imm &= ~(1LL << i); } if (n == 4) { off4_fixup(MI, &imm); @@ -253,7 +262,7 @@ static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) const8_fixup(MI, &imm); } - printInt64Bang(O, imm); + printUInt32Bang(O, to_u32(imm)); fill_imm(MI, imm); } else printOperand(MI, OpNum, O); @@ -263,23 +272,29 @@ static void printOff18Imm(MCInst *MI, int OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { - uint32_t imm = (uint32_t)MCOperand_getImm(MO); - imm = ((imm & 0x3C000) << 14) | (imm & 0x3fff); - printUInt32Bang(O, imm); - fill_imm(MI, (int32_t)imm); + int64_t imm = MCOperand_getImm(MO); + imm = ((to_u32(imm) & 0x3C000) << 14) | (to_u32(imm) & 0x3fff); + printUInt32Bang(O, to_u32(imm)); + fill_imm(MI, imm); } else printOperand(MI, OpNum, O); } +// PC + sext(2 * disp) +#define DISP1(N) ((int64_t)(MI->address) + sign_ext64(disp * 2, N)) +// PC + sext(disp) * 2 +#define DISP2(N) ((int64_t)(MI->address) + sign_ext64(disp, N) * 2) + static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { - uint32_t disp = MCOperand_getImm(MO); + int64_t disp = MCOperand_getImm(MO); + int64_t res = 0; switch (MCInst_getOpcode(MI)) { case TRICORE_CALL_b: case TRICORE_FCALL_b: { - disp = (int32_t)MI->address + sign_ext_n(disp * 2, 24); + res = DISP1(24); break; } case TRICORE_CALLA_b: @@ -287,17 +302,17 @@ static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O) case TRICORE_JA_b: case TRICORE_JLA_b: // = {disp24[23:20], 7’b0000000, disp24[19:0], 1’b0}; - disp = ((disp & 0xf00000) << 28) | - ((disp & 0xfffff) << 1); + res = ((to_u32(disp) & 0xf00000) << 28) | + ((to_u32(disp) & 0xfffff) << 1); break; case TRICORE_J_b: case TRICORE_JL_b: - disp = (int32_t)MI->address + sign_ext_n(disp, 24) * 2; + res = DISP2(24); break; } - printUInt32Bang(O, disp); - fill_imm(MI, disp); + printUInt32Bang(O, to_u32(res)); + fill_imm(MI, res); } else printOperand(MI, OpNum, O); } @@ -306,8 +321,13 @@ static void printDisp15Imm(MCInst *MI, int OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { - uint32_t disp = MCOperand_getImm(MO); + int64_t disp = MCOperand_getImm(MO); + int64_t res = 0; switch (MCInst_getOpcode(MI)) { + case TRICORE_LOOP_brr: + case TRICORE_LOOPU_brr: + res = DISP1(15); + break; case TRICORE_JEQ_brc: case TRICORE_JEQ_brr: case TRICORE_JEQ_A_brr: @@ -330,19 +350,15 @@ static void printDisp15Imm(MCInst *MI, int OpNum, SStream *O) case TRICORE_JNZ_T_brn: case TRICORE_JZ_A_brr: case TRICORE_JZ_T_brn: - disp = (int32_t)MI->address + sign_ext_n(disp, 15) * 2; - break; - case TRICORE_LOOP_brr: - case TRICORE_LOOPU_brr: - disp = (int32_t)MI->address + sign_ext_n(disp * 2, 15); + res = DISP2(15); break; default: // handle other cases, if any break; } - printUInt32Bang(O, disp); - fill_imm(MI, disp); + printUInt32Bang(O, to_u32(res)); + fill_imm(MI, res); } else printOperand(MI, OpNum, O); } @@ -351,23 +367,24 @@ static void printDisp8Imm(MCInst *MI, int OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { - uint32_t disp = MCOperand_getImm(MO); + int64_t disp = MCOperand_getImm(MO); + int64_t res = 0; switch (MCInst_getOpcode(MI)) { case TRICORE_CALL_sb: - disp = (int32_t)MI->address + sign_ext_n(2 * disp, 8); + disp = DISP1(8); break; case TRICORE_J_sb: case TRICORE_JNZ_sb: case TRICORE_JZ_sb: - disp = (int32_t)MI->address + sign_ext_n(disp, 8) * 2; + res = DISP2(8); break; default: // handle other cases, if any break; } - printUInt32Bang(O, disp); - fill_imm(MI, disp); + printUInt32Bang(O, to_u32(res)); + fill_imm(MI, res); } else printOperand(MI, OpNum, O); } @@ -376,7 +393,8 @@ static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { - uint32_t disp = MCOperand_getImm(MO); + int64_t disp = MCOperand_getImm(MO); + int64_t res = 0; switch (MCInst_getOpcode(MI)) { case TRICORE_JEQ_sbc1: case TRICORE_JEQ_sbr1: @@ -392,27 +410,29 @@ static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O) case TRICORE_JZ_sbr: case TRICORE_JZ_A_sbr: case TRICORE_JZ_T_sbrn: - disp = (int32_t)MI->address + disp * 2; + // PC + zero_ext(disp4) * 2; + res = (int64_t)(MI->address) + disp * 2; break; case TRICORE_JEQ_sbc2: case TRICORE_JEQ_sbr2: case TRICORE_JNE_sbc2: case TRICORE_JNE_sbr2: - disp = (int32_t)MI->address + (disp + 16) * 2; + // PC + zero_ext(disp4 + 16) * 2; + res = (int64_t)(MI->address) + ((disp + 16) * 2); break; case TRICORE_LOOP_sbr: - // {27b’111111111111111111111111111, disp4, 0}; - disp = (int32_t)MI->address + - ((0b111111111111111111111111111 << 5) | - (disp << 1)); + // PC + {27b’111111111111111111111111111, disp4, 0}; + res = (int64_t)(MI->address) + + ((0b111111111111111111111111111LL << 5) | + (to_u32(disp) << 1)); break; default: // handle other cases, if any break; } - printUInt32Bang(O, disp); - fill_imm(MI, disp); + printUInt32Bang(O, to_u32(res)); + fill_imm(MI, res); } else printOperand(MI, OpNum, O); } @@ -432,14 +452,21 @@ static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O) // clang-format off printSExtImm_(16) + printSExtImm_(10) + printSExtImm_(9) + printSExtImm_(4) printZExtImm_(16) + printZExtImm_(9) + printZExtImm_(8) + printZExtImm_(4) + printZExtImm_(2); // clang-format on @@ -448,12 +475,12 @@ static void printOExtImm_4(MCInst *MI, int OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { - uint32_t imm = MCOperand_getImm(MO); - // {27b’111111111111111111111111111, disp4, 0}; - imm = 0b11111111111111111111111111100000 | (imm << 1); - - printInt32Bang(O, imm); - fill_imm(MI, imm); + int64_t disp = MCOperand_getImm(MO); + int64_t res = (int64_t)(MI->address) + + ((0b111111111111111111111111111 << 5) | + (to_u32(disp) << 1)); + printUInt32Bang(O, to_u32(res)); + fill_imm(MI, res); } else printOperand(MI, OpNum, O); } diff --git a/bindings/python/capstone/tricore.py b/bindings/python/capstone/tricore.py index 9a48a9f795..79b02a6963 100644 --- a/bindings/python/capstone/tricore.py +++ b/bindings/python/capstone/tricore.py @@ -7,14 +7,14 @@ class TriCoreOpMem(ctypes.Structure): _fields_ = ( ('base', ctypes.c_uint8), - ('disp', ctypes.c_int32), + ('disp', ctypes.c_int64), ) class TriCoreOpValue(ctypes.Union): _fields_ = ( ('reg', ctypes.c_uint), - ('imm', ctypes.c_int32), + ('imm', ctypes.c_int64), ('mem', TriCoreOpMem), ) diff --git a/bindings/python/test_tricore.py b/bindings/python/test_tricore.py index a247b325cb..eace8759a7 100755 --- a/bindings/python/test_tricore.py +++ b/bindings/python/test_tricore.py @@ -5,7 +5,7 @@ from __future__ import print_function from capstone import * from capstone.tricore import * -from xprint import to_x_32, to_hex +from xprint import to_hex, to_x TRICORE_CODE = b"\x09\xcf\xbc\xf5\x09\xf4\x01\x00\x89\xfb\x8f\x74\x89\xfe\x48\x01\x29\x00\x19\x25\x29\x03\x09\xf4\x85\xf9\x68\x0f\x16\x01" @@ -29,7 +29,7 @@ def print_insn_detail(insn): if i.type == TRICORE_OP_REG: print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) if i.type == TRICORE_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm))) + print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) if i.type == TRICORE_OP_MEM: print("\t\toperands[%u].type: MEM" % c) if i.mem.base != 0: @@ -37,7 +37,7 @@ def print_insn_detail(insn): % (c, insn.reg_name(i.mem.base))) if i.mem.disp != 0: print("\t\t\toperands[%u].mem.disp: 0x%s" \ - % (c, to_x_32(i.mem.disp))) + % (c, to_x(i.mem.disp))) c += 1 print() diff --git a/cstool/cstool_tricore.c b/cstool/cstool_tricore.c index 28446e7a98..6a7a3face6 100644 --- a/cstool/cstool_tricore.c +++ b/cstool/cstool_tricore.c @@ -1,5 +1,4 @@ #include -#include #include #include "cstool.h" @@ -30,13 +29,13 @@ void print_insn_detail_tricore(csh handle, cs_insn *ins) cs_reg_name(handle, op->reg)); break; case TRICORE_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%x\n", i, - op->imm); + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", + i, op->imm); break; case TRICORE_OP_MEM: printf("\t\toperands[%u].type: MEM\n" "\t\t\t.mem.base: REG = %s\n" - "\t\t\t.mem.disp: 0x%x\n", + "\t\t\t.mem.disp: 0x%" PRIx64 "\n", i, cs_reg_name(handle, op->mem.base), op->mem.disp); break; diff --git a/include/capstone/tricore.h b/include/capstone/tricore.h index aec5da0251..4cf22f59d3 100644 --- a/include/capstone/tricore.h +++ b/include/capstone/tricore.h @@ -31,7 +31,7 @@ typedef enum tricore_op_type { /// This is associated with TRICORE_OP_MEM operand type above typedef struct tricore_op_mem { uint8_t base; ///< base register - int32_t disp; ///< displacement/offset value + int64_t disp; ///< displacement/offset value } tricore_op_mem; /// Instruction operand @@ -39,7 +39,7 @@ typedef struct cs_tricore_op { tricore_op_type type; ///< operand type union { unsigned int reg; ///< register value for REG operand - int32_t imm; ///< immediate value for IMM operand + int64_t imm; ///< immediate value for IMM operand tricore_op_mem mem; ///< base/disp value for MEM operand }; /// This field is combined of cs_ac_type. diff --git a/suite/MC/TriCore/tc110.s.cs b/suite/MC/TriCore/tc110.s.cs index 67ed452d74..3a0d20dbba 100644 --- a/suite/MC/TriCore/tc110.s.cs +++ b/suite/MC/TriCore/tc110.s.cs @@ -293,7 +293,7 @@ 0xc5, 0x00, 0x00, 0x00 = lea a0, #0 0xd9, 0x00, 0x00, 0x00 = lea a0, [a0]#0 0x49, 0x00, 0x00, 0x0a = lea a0, [a0]#0 -0xfc, 0x00 = loop a0, #-0x20 +0xfc, 0x00 = loop a0, #0xffffffe0 0xfd, 0x00, 0x00, 0x00 = loop a0, #0 0x7a, 0x00 = lt d15, d0, d0 0xfa, 0x00 = lt d15, d0, #0 diff --git a/suite/MC/TriCore/tc120.s.cs b/suite/MC/TriCore/tc120.s.cs index f750aad247..f121f74753 100644 --- a/suite/MC/TriCore/tc120.s.cs +++ b/suite/MC/TriCore/tc120.s.cs @@ -291,7 +291,7 @@ 0xc5, 0x00, 0x00, 0x00 = lea a0, #0 0xd9, 0x00, 0x00, 0x00 = lea a0, [a0]#0 0x49, 0x00, 0x00, 0x0a = lea a0, [a0]#0 -0xfc, 0x00 = loop a0, #-0x20 +0xfc, 0x00 = loop a0, #0xffffffe0 0xfd, 0x00, 0x00, 0x00 = loop a0, #0 0xfd, 0x00, 0x00, 0x80 = loopu #0 0x7a, 0x00 = lt d15, d0, d0 diff --git a/suite/MC/TriCore/tc130.s.cs b/suite/MC/TriCore/tc130.s.cs index 936c3e2b4b..adace40f2f 100644 --- a/suite/MC/TriCore/tc130.s.cs +++ b/suite/MC/TriCore/tc130.s.cs @@ -303,7 +303,7 @@ 0xc5, 0x00, 0x00, 0x00 = lea a0, #0 0xd9, 0x00, 0x00, 0x00 = lea a0, [a0]#0 0x49, 0x00, 0x00, 0x0a = lea a0, [a0]#0 -0xfc, 0x00 = loop a0, #-0x20 +0xfc, 0x00 = loop a0, #0xffffffe0 0xfd, 0x00, 0x00, 0x00 = loop a0, #0 0xfd, 0x00, 0x00, 0x80 = loopu #0 0x7a, 0x00 = lt d15, d0, d0 diff --git a/suite/MC/TriCore/tc131.s.cs b/suite/MC/TriCore/tc131.s.cs index 7ec6369dec..b8454e771a 100644 --- a/suite/MC/TriCore/tc131.s.cs +++ b/suite/MC/TriCore/tc131.s.cs @@ -312,7 +312,7 @@ 0xc5, 0x00, 0x00, 0x00 = lea a0, #0 0xd9, 0x00, 0x00, 0x00 = lea a0, [a0]#0 0x49, 0x00, 0x00, 0x0a = lea a0, [a0]#0 -0xfc, 0x00 = loop a0, #-0x20 +0xfc, 0x00 = loop a0, #0xffffffe0 0xfd, 0x00, 0x00, 0x00 = loop a0, #0 0xfd, 0x00, 0x00, 0x80 = loopu #0 0x7a, 0x00 = lt d15, d0, d0 diff --git a/suite/MC/TriCore/tc160.s.cs b/suite/MC/TriCore/tc160.s.cs index 14fe1ccfea..fb3eee902c 100644 --- a/suite/MC/TriCore/tc160.s.cs +++ b/suite/MC/TriCore/tc160.s.cs @@ -331,7 +331,7 @@ 0xc5, 0x00, 0x00, 0x00 = lea a0, #0 0xd9, 0x00, 0x00, 0x00 = lea a0, [a0]#0 0x49, 0x00, 0x00, 0x0a = lea a0, [a0]#0 -0xfc, 0x00 = loop a0, #-0x20 +0xfc, 0x00 = loop a0, #0xffffffe0 0xfd, 0x00, 0x00, 0x00 = loop a0, #0 0xfd, 0x00, 0x00, 0x80 = loopu #0 0x7a, 0x00 = lt d15, d0, d0 diff --git a/suite/MC/TriCore/tc161.s.cs b/suite/MC/TriCore/tc161.s.cs index b75a0d8abf..30574e7ac0 100644 --- a/suite/MC/TriCore/tc161.s.cs +++ b/suite/MC/TriCore/tc161.s.cs @@ -337,7 +337,7 @@ 0xc5, 0x00, 0x00, 0x00 = lea a0, #0 0xd9, 0x00, 0x00, 0x00 = lea a0, [a0]#0 0x49, 0x00, 0x00, 0x0a = lea a0, [a0]#0 -0xfc, 0x00 = loop a0, #-0x20 +0xfc, 0x00 = loop a0, #0xffffffe0 0xfd, 0x00, 0x00, 0x00 = loop a0, #0 0xfd, 0x00, 0x00, 0x80 = loopu #0 0x7a, 0x00 = lt d15, d0, d0 diff --git a/suite/MC/TriCore/tc162.s.cs b/suite/MC/TriCore/tc162.s.cs index 823227d625..baed4ba335 100644 --- a/suite/MC/TriCore/tc162.s.cs +++ b/suite/MC/TriCore/tc162.s.cs @@ -343,7 +343,7 @@ 0xd9, 0x00, 0x00, 0x00 = lea a0, [a0]#0 0x49, 0x00, 0x00, 0x0a = lea a0, [a0]#0 0xc5, 0x00, 0x00, 0x04 = lha a0, #0 -0xfc, 0x00 = loop a0, #-0x20 +0xfc, 0x00 = loop a0, #0xffffffe0 0xfd, 0x00, 0x00, 0x00 = loop a0, #0 0xfd, 0x00, 0x00, 0x80 = loopu #0 0x7a, 0x00 = lt d15, d0, d0 diff --git a/suite/cstest/src/capstone_test.c b/suite/cstest/src/capstone_test.c index e282756e83..c407547ac6 100644 --- a/suite/cstest/src/capstone_test.c +++ b/suite/cstest/src/capstone_test.c @@ -21,6 +21,11 @@ void test_single_MC(csh *handle, int mc_mode, char *line) char *p; list_part = split(line, " = ", &size_part); + if (size_part <= 1) { + free_strs(list_part, size_part); + return; + } + offset_opcode = split(list_part[0], ": ", &size_offset_opcode); if (size_offset_opcode > 1) { offset = (unsigned int)strtol(offset_opcode[0], NULL, 16); diff --git a/tests/test_tricore.c b/tests/test_tricore.c index c423d72d25..38e71ba6e8 100644 --- a/tests/test_tricore.c +++ b/tests/test_tricore.c @@ -51,8 +51,8 @@ static void print_insn_detail(cs_insn *ins) cs_reg_name(handle, op->reg)); break; case TRICORE_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%x\n", i, - op->imm); + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", + i, op->imm); break; case TRICORE_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); @@ -60,8 +60,9 @@ static void print_insn_detail(cs_insn *ins) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, - op->mem.disp); + printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 + "\n", + i, op->mem.disp); break; }