Rename all modules to cve2 (openhwgroup#25)

* rename files and modules to cve2

Signed-off-by: Szymon Bieganski <[email protected]>

* updated tb files

Signed-off-by: Szymon Bieganski <[email protected]>

* remaining references to ibex: gitignore, examples, etc.

Signed-off-by: Szymon Bieganski <[email protected]>

Signed-off-by: Szymon Bieganski <[email protected]>
Co-authored-by: Szymon Bieganski <[email protected]>

Author: christian-herber-nxp

.gitignore

@@ -19,18 +19,18 @@ ibex_simple_system_pcount.csv
 __pycache__
 
 # This is generated by VCS when running DV simulations with WAVE=1.
-/dv/uvm/core_ibex/ucli.key
+/dv/uvm/core_cve2/ucli.key
 
 # This is generated by UVM when running simulations and doesn't seem
 # to be something you can disable.
-/dv/uvm/core_ibex/tr_db.log
+/dv/uvm/core_cve2/tr_db.log
 
-# This is the default output directory in dv/uvm/core_ibex and
+# This is the default output directory in dv/uvm/core_cve2 and
 # contains auto-generated files from building and running tests.
-/dv/uvm/core_ibex/out
+/dv/uvm/core_cve2/out
 
 # This is generated by Questa tool when running DV simulations
 modelsim.ini
 
 # This is generated by Xcelium when running DV simulations, even with WAVE=0
-/dv/uvm/core_ibex/waves.shm
+/dv/uvm/core_cve2/waves.shm

Makefile

@@ -1,6 +1,6 @@
-IBEX_CONFIG ?= small
+CVE2_CONFIG ?= small
 
-FUSESOC_CONFIG_OPTS = $(shell ./util/ibex_config.py $(IBEX_CONFIG) fusesoc_opts)
+FUSESOC_CONFIG_OPTS = $(shell ./util/cve2_config.py $(CVE2_CONFIG) fusesoc_opts)
 
 all: help
 
@@ -19,7 +19,7 @@ build-all: build-riscv-compliance build-simple-system build-arty-100 \
 .PHONY: build-riscv-compliance
 build-riscv-compliance:
 	fusesoc --cores-root=. run --target=sim --setup --build \
-		lowrisc:ibex:ibex_riscv_compliance \
+		lowrisc:cve2:cve2_riscv_compliance \
 		$(FUSESOC_CONFIG_OPTS)
 
 
@@ -30,7 +30,7 @@ build-riscv-compliance:
 .PHONY: build-simple-system
 build-simple-system:
 	fusesoc --cores-root=. run --target=sim --setup --build \
-		lowrisc:ibex:ibex_simple_system \
+		lowrisc:cve2:cve2_simple_system \
 		$(FUSESOC_CONFIG_OPTS)
 
 simple-system-program = examples/sw/simple_system/hello_test/hello_test.vmem
@@ -40,15 +40,15 @@ sw-simple-hello: $(simple-system-program)
 $(simple-system-program):
 	cd examples/sw/simple_system/hello_test && $(MAKE)
 
-Vibex_simple_system = \
-      build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system
-$(Vibex_simple_system):
+Vcve2_simple_system = \
+      build/lowrisc_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system
+$(Vcve2_simple_system):
 	@echo "$@ not found"
 	@echo "Run \"make build-simple-system\" to create the dependency"
 	@false
 
-run-simple-system: sw-simple-hello | $(Vibex_simple_system)
-	build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system \
+run-simple-system: sw-simple-hello | $(Vcve2_simple_system)
+	build/lowrisc_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system \
 		--raminit=$(simple-system-program)
 
 
@@ -67,23 +67,23 @@ $(arty-sw-program):
 .PHONY: build-arty-35
 build-arty-35: sw-led
 	fusesoc --cores-root=. run --target=synth --setup --build \
-		lowrisc:ibex:top_artya7 --part xc7a35ticsg324-1L
+		lowrisc:cve2:top_artya7 --part xc7a35ticsg324-1L
 
 .PHONY: build-arty-100
 build-arty-100: sw-led
 	fusesoc --cores-root=. run --target=synth --setup --build \
-		lowrisc:ibex:top_artya7 --part xc7a100tcsg324-1
+		lowrisc:cve2:top_artya7 --part xc7a100tcsg324-1
 
 .PHONY: program-arty
 program-arty:
 	fusesoc --cores-root=. run --target=synth --run \
-		lowrisc:ibex:top_artya7
+		lowrisc:cve2:top_artya7
 
 
 # Lint check
 .PHONY: lint-core-tracing
 lint-core-tracing:
-	fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core_tracing \
+	fusesoc --cores-root . run --target=lint lowrisc:cve2:cve2_core_tracing \
 		$(FUSESOC_CONFIG_OPTS)
 
 
@@ -94,9 +94,9 @@ lint-core-tracing:
 .PHONY: build-csr-test
 build-csr-test:
 	fusesoc --cores-root=. run --target=sim --setup --build \
-	      --tool=verilator lowrisc:ibex:tb_cs_registers
+	      --tool=verilator lowrisc:cve2:tb_cs_registers
 Vtb_cs_registers = \
-      build/lowrisc_ibex_tb_cs_registers_0/sim-verilator/Vtb_cs_registers
+      build/lowrisc_cve2_tb_cs_registers_0/sim-verilator/Vtb_cs_registers
 $(Vtb_cs_registers):
 	@echo "$@ not found"
 	@echo "Run \"make build-csr-test\" to create the dependency"
@@ -105,9 +105,9 @@ $(Vtb_cs_registers):
 .PHONY: run-csr-test
 run-csr-test: | $(Vtb_cs_registers)
 	fusesoc --cores-root=. run --target=sim --run \
-	      --tool=verilator lowrisc:ibex:tb_cs_registers
+	      --tool=verilator lowrisc:cve2:tb_cs_registers
 
-# Echo the parameters passed to fusesoc for the chosen IBEX_CONFIG
+# Echo the parameters passed to fusesoc for the chosen CVE2_CONFIG
 .PHONY: test-cfg
 test-cfg:
 	@echo $(FUSESOC_CONFIG_OPTS)

azure-pipelines.yml

@@ -49,10 +49,10 @@ jobs:
   # Verible format is experimental so only run on default config for now,
   # will eventually become part of the per-config CI
   - bash: |
-      fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_top_tracing
+      fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:cve2:cve2_top_tracing
       if [ $? != 0 ]; then
         echo -n "##vso[task.logissue type=error]"
-        echo "Verilog format with Verible failed. Run 'fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_top_tracing' to check and fix all errors."
+        echo "Verilog format with Verible failed. Run 'fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:cve2:cve2_top_tracing' to check and fix all errors."
         echo "This flow is currently experimental and failures can be ignored."
       fi
       # Show diff of what verilog_format would have changed, and then revert.
@@ -78,7 +78,7 @@ jobs:
   - bash: |
       # Build and run CSR testbench, chosen Ibex configuration does not effect
       # this so doesn't need to be part of per-config CI
-      fusesoc --cores-root=. run --target=sim --tool=verilator lowrisc:ibex:tb_cs_registers
+      fusesoc --cores-root=. run --target=sim --tool=verilator lowrisc:cve2:tb_cs_registers
     displayName: Build and run CSR testbench with Verilator
 
   - bash: |
@@ -96,7 +96,7 @@ jobs:
   # Run Ibex RTL CI per supported configuration
   - template : ci/ibex-rtl-ci-steps.yml
     parameters:
-      ibex_configs:
+      cve2_configs:
         # Note: Try to keep the list of configurations in sync with the one used
         # in Private CI.
         - small
@@ -107,19 +107,19 @@ jobs:
 
   # Run lint on simple system
   - bash: |
-      fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_simple_system
+      fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:cve2:cve2_simple_system
       if [ $? != 0 ]; then
         echo -n "##vso[task.logissue type=error]"
-        echo "Verilog lint with Verilator failed. Run 'fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_simple_system' to check and fix all errors."
+        echo "Verilog lint with Verilator failed. Run 'fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:cve2:cve2_simple_system' to check and fix all errors."
         exit 1
       fi
     displayName: Run Verilator lint on simple system
 
   - bash: |
-      fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_simple_system
+      fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:cve2:cve2_simple_system
       if [ $? != 0 ]; then
         echo -n "##vso[task.logissue type=error]"
-        echo "Verilog lint with Verible failed. Run 'fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_simple_system' to check and fix all errors."
+        echo "Verilog lint with Verible failed. Run 'fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:cve2:cve2_simple_system' to check and fix all errors."
         exit 1
       fi
     displayName: Run Verible lint on simple system

ci/ibex-rtl-ci-steps.yml ci/cve2-rtl-ci-steps.yml

@@ -1,47 +1,47 @@
 parameters:
-  ibex_configs: []
+  cve2_configs: []
 
 steps:
-  - ${{ each config in parameters.ibex_configs }}:
-    # ibex_config.py will exit with error code 1 on any error which will cause
+  - ${{ each config in parameters.cve2_configs }}:
+    # cve2_config.py will exit with error code 1 on any error which will cause
     # the CI to fail if there's an issue with the configuration file or an
     # incorrect configuration name being used
     - bash: |
         set -e
-        IBEX_CONFIG_OPTS=`./util/ibex_config.py ${{ config }} fusesoc_opts`
-        echo $IBEX_CONFIG_OPTS
-        echo "##vso[task.setvariable variable=ibex_config_opts]" $IBEX_CONFIG_OPTS
+        CVE2_CONFIG_OPTS=`./util/cve2_config.py ${{ config }} fusesoc_opts`
+        echo $CVE2_CONFIG_OPTS
+        echo "##vso[task.setvariable variable=cve2_config_opts]" $CVE2_CONFIG_OPTS
       displayName: Test and display fusesoc config for ${{ config }}
 
     - bash: |
-        fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_top_tracing $IBEX_CONFIG_OPTS
+        fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:cve2:cve2_top_tracing $CVE2_CONFIG_OPTS
         if [ $? != 0 ]; then
           echo -n "##vso[task.logissue type=error]"
-          echo "Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_top_tracing $IBEX_CONFIG_OPTS' to check and fix all errors."
+          echo "Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:cve2:cve2_top_tracing $CVE2_CONFIG_OPTS' to check and fix all errors."
           exit 1
         fi
       displayName: Lint Verilog source files with Verilator for ${{ config }}
 
     - bash: |
-        fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_top_tracing $IBEX_CONFIG_OPTS
+        fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:cve2:cve2_top_tracing $CVE2_CONFIG_OPTS
         if [ $? != 0 ]; then
           echo -n "##vso[task.logissue type=error]"
-          echo "Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_top_tracing $IBEX_CONFIG_OPTS' to check and fix all errors."
+          echo "Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:cve2:cve2_top_tracing $CVE2_CONFIG_OPTS' to check and fix all errors."
           exit 1
         fi
       displayName: Lint Verilog source files with Verible Verilog Lint for ${{ config }}
 
     - bash: |
         # Build simulation model of Ibex
-        fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_riscv_compliance $IBEX_CONFIG_OPTS
+        fusesoc --cores-root=. run --target=sim --setup --build lowrisc:cve2:cve2_riscv_compliance $CVE2_CONFIG_OPTS
         if [ $? != 0 ]; then
           echo -n "##vso[task.logissue type=error]"
           echo "Unable to build Verilator model of Ibex for compliance testing."
           exit 1
         fi
 
         # Run compliance test suite
-        export TARGET_SIM=$PWD/build/lowrisc_ibex_ibex_riscv_compliance_0.1/sim-verilator/Vibex_riscv_compliance
+        export TARGET_SIM=$PWD/build/lowrisc_cve2_cve2_riscv_compliance_0.1/sim-verilator/Vcve2_riscv_compliance
         export RISCV_PREFIX=riscv32-unknown-elf-
         export RISCV_TARGET=ibex
         export RISCV_DEVICE=rv32imc
@@ -68,18 +68,18 @@ steps:
 
     - bash: |
         # Setup environment to use cosim with Simple System
-        export IBEX_COSIM_ISS_ROOT=/opt/spike-cosim
+        export CVE2_COSIM_ISS_ROOT=/opt/spike-cosim
         export LD_LIBRARY_PATH=/opt/spike-cosim/lib:$LD_LIBRARY_PATH
 
         # Build simple system with co-simulation
-        fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system_cosim $IBEX_CONFIG_OPTS
+        fusesoc --cores-root=. run --target=sim --setup --build lowrisc:cve2:cve2_simple_system_cosim $CVE2_CONFIG_OPTS
 
         if [ $? != 0 ]; then
           echo -n "##vso[task.logissue type=error]"
-          echo "Build Simple System with co-simulation failed. Run fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system_cosim $IBEX_CONFIG_OPTS to check and fix all errors."
+          echo "Build Simple System with co-simulation failed. Run fusesoc --cores-root=. run --target=sim --setup --build lowrisc:cve2:cve2_simple_system_cosim $CVE2_CONFIG_OPTS to check and fix all errors."
         fi
 
-        build/lowrisc_ibex_ibex_simple_system_cosim_0/sim-verilator/Vibex_simple_system --meminit=ram,examples/sw/benchmarks/coremark/coremark.elf
+        build/lowrisc_cve2_cve2_simple_system_cosim_0/sim-verilator/Vcve2_simple_system --meminit=ram,examples/sw/benchmarks/coremark/coremark.elf
         if [ $? != 0 ]; then
           echo -n "##vso[task.logissue type=error]"
           echo "Running CoreMark failed co-simulation testing"

cv32e20_manifest.flist

@@ -33,37 +33,37 @@
 +incdir+${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl
 +incdir+${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/dv/sv/dv_utils
 
-${DESIGN_RTL_DIR}/ibex_pkg.sv
-${DESIGN_RTL_DIR}/ibex_tracer_pkg.sv
+${DESIGN_RTL_DIR}/cve2_pkg.sv
+${DESIGN_RTL_DIR}/cve2_tracer_pkg.sv
 ${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv
 ${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv
-${DESIGN_RTL_DIR}/ibex_alu.sv
-${DESIGN_RTL_DIR}/ibex_branch_predict.sv
-${DESIGN_RTL_DIR}/ibex_compressed_decoder.sv
-${DESIGN_RTL_DIR}/ibex_controller.sv
-${DESIGN_RTL_DIR}/ibex_cs_registers.sv
-${DESIGN_RTL_DIR}/ibex_csr.sv
-${DESIGN_RTL_DIR}/ibex_counter.sv
-${DESIGN_RTL_DIR}/ibex_decoder.sv
-${DESIGN_RTL_DIR}/ibex_ex_block.sv
-${DESIGN_RTL_DIR}/ibex_fetch_fifo.sv
-${DESIGN_RTL_DIR}/ibex_id_stage.sv
-${DESIGN_RTL_DIR}/ibex_if_stage.sv
-${DESIGN_RTL_DIR}/ibex_load_store_unit.sv
-${DESIGN_RTL_DIR}/ibex_multdiv_fast.sv
-${DESIGN_RTL_DIR}/ibex_multdiv_slow.sv
-${DESIGN_RTL_DIR}/ibex_prefetch_buffer.sv
-${DESIGN_RTL_DIR}/ibex_pmp.sv
-${DESIGN_RTL_DIR}/ibex_register_file_ff.sv
-${DESIGN_RTL_DIR}/ibex_wb_stage.sv
-${DESIGN_RTL_DIR}/ibex_dummy_instr.sv
-${DESIGN_RTL_DIR}/ibex_core.sv
-${DESIGN_RTL_DIR}/ibex_top.sv
-${DESIGN_RTL_DIR}/ibex_top_tracing.sv
-${DESIGN_RTL_DIR}/ibex_tracer.sv
+${DESIGN_RTL_DIR}/cve2_alu.sv
+${DESIGN_RTL_DIR}/cve2_branch_predict.sv
+${DESIGN_RTL_DIR}/cve2_compressed_decoder.sv
+${DESIGN_RTL_DIR}/cve2_controller.sv
+${DESIGN_RTL_DIR}/cve2_cs_registers.sv
+${DESIGN_RTL_DIR}/cve2_csr.sv
+${DESIGN_RTL_DIR}/cve2_counter.sv
+${DESIGN_RTL_DIR}/cve2_decoder.sv
+${DESIGN_RTL_DIR}/cve2_ex_block.sv
+${DESIGN_RTL_DIR}/cve2_fetch_fifo.sv
+${DESIGN_RTL_DIR}/cve2_id_stage.sv
+${DESIGN_RTL_DIR}/cve2_if_stage.sv
+${DESIGN_RTL_DIR}/cve2_load_store_unit.sv
+${DESIGN_RTL_DIR}/cve2_multdiv_fast.sv
+${DESIGN_RTL_DIR}/cve2_multdiv_slow.sv
+${DESIGN_RTL_DIR}/cve2_prefetch_buffer.sv
+${DESIGN_RTL_DIR}/cve2_pmp.sv
+${DESIGN_RTL_DIR}/cve2_register_file_ff.sv
+${DESIGN_RTL_DIR}/cve2_wb_stage.sv
+${DESIGN_RTL_DIR}/cve2_dummy_instr.sv
+${DESIGN_RTL_DIR}/cve2_core.sv
+${DESIGN_RTL_DIR}/cve2_top.sv
+${DESIGN_RTL_DIR}/cve2_top_tracing.sv
+${DESIGN_RTL_DIR}/cve2_tracer.sv
 
 ${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv
 ${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv
-${DESIGN_RTL_DIR}/../dv/uvm/core_ibex/common/prim/prim_pkg.sv
-${DESIGN_RTL_DIR}/../dv/uvm/core_ibex/common/prim/prim_clock_gating.sv
-${DESIGN_RTL_DIR}/../dv/uvm/core_ibex/common/prim/prim_buf.sv
+${DESIGN_RTL_DIR}/../dv/uvm/core_cve2/common/prim/prim_pkg.sv
+${DESIGN_RTL_DIR}/../dv/uvm/core_cve2/common/prim/prim_clock_gating.sv
+${DESIGN_RTL_DIR}/../dv/uvm/core_cve2/common/prim/prim_buf.sv