diff --git a/.travis.yml b/.travis.yml index cc9bbc6..de8af0e 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,9 +1,12 @@ language: go go: - 1.4.3 - - 1.5.3 - - 1.6.1 - - 1.7.3 + - 1.5.4 + - 1.6.4 + - 1.7.6 + - 1.8.7 + - 1.9.7 + - 1.10.8 - tip sudo: false before_install: diff --git a/README.md b/README.md index 90f354d..a7bfc03 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ gapstone Gapstone is a Go binding for the Capstone disassembly library. -## CURRENT UPSTREAM VERSION: 3.0.4 +## CURRENT UPSTREAM VERSION: 4.0.1 [![Build Status](https://travis-ci.org/bnagy/gapstone.svg?branch=master)](https://travis-ci.org/bnagy/gapstone) (head over to the next branch for the newest stuff) diff --git a/arm.SPEC b/arm.SPEC index 998d7ce..534f0c5 100644 --- a/arm.SPEC +++ b/arm.SPEC @@ -1,272 +1,480 @@ **************** Platform: ARM -Code:0xed 0xff 0xff 0xeb 0x04 0xe0 0x2d 0xe5 0x00 0x00 0x00 0x00 0xe0 0x83 0x22 0xe5 0xf1 0x02 0x03 0x0e 0x00 0x00 0xa0 0xe3 0x02 0x30 0xc1 0xe7 0x00 0x00 0x53 0xe3 0x00 0x02 0x01 0xf1 0x05 0x40 0xd0 0xe8 0xf4 0x80 0x00 0x00 +Code:0x86 0x48 0x60 0xf4 0x4d 0x0f 0xe2 0xf4 0xed 0xff 0xff 0xeb 0x04 0xe0 0x2d 0xe5 0x00 0x00 0x00 0x00 0xe0 0x83 0x22 0xe5 0xf1 0x02 0x03 0x0e 0x00 0x00 0xa0 0xe3 0x02 0x30 0xc1 0xe7 0x00 0x00 0x53 0xe3 0x00 0x02 0x01 0xf1 0x05 0x40 0xd0 0xe8 0xf4 0x80 0x00 0x00 Disasm: -0x1000: bl #0xfbc +0x80001000: vld2.32 {d20, d21}, [r0], r6 + op_count: 4 + operands[0].type: REG = d20 + operands[0].access: WRITE + operands[1].type: REG = d21 + operands[1].access: WRITE + operands[2].type: MEM + operands[2].mem.base: REG = r0 + operands[2].access: READ + operands[3].type: REG = r6 + operands[3].access: READ + Vector-size: 32 + Registers read: r0 r6 + Registers modified: d20 d21 + +0x80001004: vld4.16 {d16[], d17[], d18[], d19[]}, [r2]! + op_count: 5 + operands[0].type: REG = d16 + operands[0].access: WRITE + operands[1].type: REG = d17 + operands[1].access: WRITE + operands[2].type: REG = d18 + operands[2].access: WRITE + operands[3].type: REG = d19 + operands[3].access: WRITE + operands[4].type: MEM + operands[4].mem.base: REG = r2 + operands[4].access: READ + Write-back: True + Vector-size: 16 + Registers read: r2 + Registers modified: d16 d17 d18 d19 r2 + +0x80001008: bl #0x80000fc4 op_count: 1 - operands[0].type: IMM = 0xfbc + operands[0].type: IMM = 0x80000fc4 + Registers read: pc + Registers modified: lr pc -0x1004: str lr, [sp, #-4]! +0x8000100c: str lr, [sp, #-4]! op_count: 2 operands[0].type: REG = lr + operands[0].access: READ operands[1].type: MEM operands[1].mem.base: REG = sp operands[1].mem.disp: 0xfffffffc + operands[1].access: WRITE Write-back: True + Registers read: lr sp + Registers modified: sp -0x1008: andeq r0, r0, r0 +0x80001010: andeq r0, r0, r0 op_count: 3 operands[0].type: REG = r0 + operands[0].access: WRITE operands[1].type: REG = r0 + operands[1].access: READ operands[2].type: REG = r0 + operands[2].access: READ Code condition: 1 + Registers read: r0 + Registers modified: r0 -0x100c: str r8, [r2, #-0x3e0]! +0x80001014: str r8, [r2, #-0x3e0]! op_count: 2 operands[0].type: REG = r8 + operands[0].access: READ operands[1].type: MEM operands[1].mem.base: REG = r2 operands[1].mem.disp: 0xfffffc20 + operands[1].access: WRITE Write-back: True + Registers read: r8 r2 + Registers modified: r2 -0x1010: mcreq p2, #0, r0, c3, c1, #7 +0x80001018: mcreq p2, #0, r0, c3, c1, #7 op_count: 6 operands[0].type: P-IMM = 2 operands[1].type: IMM = 0x0 operands[2].type: REG = r0 + operands[2].access: READ operands[3].type: C-IMM = 3 operands[4].type: C-IMM = 1 operands[5].type: IMM = 0x7 Code condition: 1 + Registers read: r0 -0x1014: mov r0, #0 +0x8000101c: mov r0, #0 op_count: 2 operands[0].type: REG = r0 + operands[0].access: WRITE operands[1].type: IMM = 0x0 + Registers modified: r0 -0x1018: strb r3, [r1, r2] +0x80001020: strb r3, [r1, r2] op_count: 2 operands[0].type: REG = r3 + operands[0].access: READ operands[1].type: MEM operands[1].mem.base: REG = r1 operands[1].mem.index: REG = r2 + operands[1].access: WRITE + Registers read: r3 r1 r2 -0x101c: cmp r3, #0 +0x80001024: cmp r3, #0 op_count: 2 operands[0].type: REG = r3 + operands[0].access: READ operands[1].type: IMM = 0x0 Update-flags: True + Registers read: r3 + Registers modified: cpsr -0x1020: setend be +0x80001028: setend be op_count: 1 operands[0].type: SETEND = be -0x1024: ldm r0, {r0, r2, lr} ^ +0x8000102c: ldm r0, {r0, r2, lr} ^ op_count: 4 operands[0].type: REG = r0 + operands[0].access: READ operands[1].type: REG = r0 + operands[1].access: WRITE operands[2].type: REG = r2 + operands[2].access: WRITE operands[3].type: REG = lr + operands[3].access: WRITE User-mode: True + Registers read: r0 + Registers modified: r0 r2 lr -0x1028: strdeq r8, sb, [r0], -r4 +0x80001030: strdeq r8, sb, [r0], -r4 op_count: 4 operands[0].type: REG = r8 + operands[0].access: READ operands[1].type: REG = sb + operands[1].access: READ operands[2].type: MEM operands[2].mem.base: REG = r0 + operands[2].access: READ operands[3].type: REG = r4 + operands[3].access: READ Subtracted: True Code condition: 1 Write-back: True + Registers read: r8 sb r0 r4 + Registers modified: r0 -0x102c: +0x80001034: **************** Platform: Thumb -Code:0x70 0x47 0xeb 0x46 0x83 0xb0 0xc9 0x68 0x1f 0xb1 0x30 0xbf 0xaf 0xf3 0x20 0x84 +Code:0x60 0xf9 0x1f 0x04 0xe0 0xf9 0x4f 0x07 0x70 0x47 0x00 0xf0 0x10 0xe8 0xeb 0x46 0x83 0xb0 0xc9 0x68 0x1f 0xb1 0x30 0xbf 0xaf 0xf3 0x20 0x84 0x52 0xf8 0x23 0xf0 Disasm: -0x1000: bx lr +0x80001000: vld3.8 {d16, d17, d18}, [r0:0x40] + op_count: 4 + operands[0].type: REG = d16 + operands[0].access: WRITE + operands[1].type: REG = d17 + operands[1].access: WRITE + operands[2].type: REG = d18 + operands[2].access: WRITE + operands[3].type: MEM + operands[3].mem.base: REG = r0 + operands[3].mem.disp: 0x40 + operands[3].access: READ + Vector-size: 8 + Registers read: r0 + Registers modified: d16 d17 d18 + +0x80001004: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] + op_count: 5 + operands[0].type: REG = d16 + operands[0].neon_lane = 1 + operands[0].access: WRITE + operands[1].type: REG = d17 + operands[1].neon_lane = 1 + operands[1].access: WRITE + operands[2].type: REG = d18 + operands[2].neon_lane = 1 + operands[2].access: WRITE + operands[3].type: REG = d19 + operands[3].neon_lane = 1 + operands[3].access: WRITE + operands[4].type: MEM + operands[4].mem.base: REG = r0 + operands[4].access: READ + Vector-size: 16 + Registers read: r0 + Registers modified: d16 d17 d18 d19 + +0x80001008: bx lr op_count: 1 operands[0].type: REG = lr + operands[0].access: READ + Registers read: lr + Registers modified: pc + +0x8000100a: blx #0x8000102c + op_count: 1 + operands[0].type: IMM = 0x8000102c + Registers read: pc + Registers modified: lr pc -0x1002: mov fp, sp +0x8000100e: mov fp, sp op_count: 2 operands[0].type: REG = fp + operands[0].access: WRITE operands[1].type: REG = sp + operands[1].access: READ + Registers read: sp + Registers modified: fp -0x1004: sub sp, #0xc +0x80001010: sub sp, #0xc op_count: 2 operands[0].type: REG = sp + operands[0].access: READ | WRITE operands[1].type: IMM = 0xc + Registers read: sp + Registers modified: sp -0x1006: ldr r1, [r1, #0xc] +0x80001012: ldr r1, [r1, #0xc] op_count: 2 operands[0].type: REG = r1 + operands[0].access: WRITE operands[1].type: MEM operands[1].mem.base: REG = r1 operands[1].mem.disp: 0xc + operands[1].access: READ + Registers read: r1 + Registers modified: r1 -0x1008: cbz r7, #0x1012 +0x80001014: cbz r7, #0x8000101e op_count: 2 operands[0].type: REG = r7 - operands[1].type: IMM = 0x1012 + operands[0].access: READ + operands[1].type: IMM = 0x8000101e + Registers read: r7 -0x100a: wfi +0x80001016: wfi -0x100c: cpsie.w f +0x80001018: cpsie.w f CPSI-mode: 2 CPSI-flag: 1 -0x1010: +0x8000101c: ldr.w pc, [r2, r3, lsl #2] + op_count: 2 + operands[0].type: REG = pc + operands[0].access: WRITE + operands[1].type: MEM + operands[1].mem.base: REG = r2 + operands[1].mem.index: REG = r3 + operands[1].access: READ + Shift: 2 = 2 + Registers read: r2 r3 + Registers modified: pc + +0x80001020: **************** Platform: Thumb-mixed Code:0xd1 0xe8 0x00 0xf0 0xf0 0x24 0x04 0x07 0x1f 0x3c 0xf2 0xc0 0x00 0x00 0x4f 0xf0 0x00 0x01 0x46 0x6c Disasm: -0x1000: tbb [r1, r0] +0x80001000: tbb [r1, r0] op_count: 1 operands[0].type: MEM operands[0].mem.base: REG = r1 operands[0].mem.index: REG = r0 + operands[0].access: READ + Registers read: r1 r0 -0x1004: movs r4, #0xf0 +0x80001004: movs r4, #0xf0 op_count: 2 operands[0].type: REG = r4 + operands[0].access: WRITE operands[1].type: IMM = 0xf0 Update-flags: True + Registers modified: r4 -0x1006: lsls r4, r0, #0x1c +0x80001006: lsls r4, r0, #0x1c op_count: 3 operands[0].type: REG = r4 + operands[0].access: WRITE operands[1].type: REG = r0 + operands[1].access: READ operands[2].type: IMM = 0x1c Update-flags: True + Registers read: r0 + Registers modified: r4 -0x1008: subs r4, #0x1f +0x80001008: subs r4, #0x1f op_count: 2 operands[0].type: REG = r4 + operands[0].access: READ | WRITE operands[1].type: IMM = 0x1f Update-flags: True + Registers read: r4 + Registers modified: r4 -0x100a: stm r0!, {r1, r4, r5, r6, r7} +0x8000100a: stm r0!, {r1, r4, r5, r6, r7} op_count: 6 operands[0].type: REG = r0 + operands[0].access: READ | WRITE operands[1].type: REG = r1 + operands[1].access: READ operands[2].type: REG = r4 + operands[2].access: READ operands[3].type: REG = r5 + operands[3].access: READ operands[4].type: REG = r6 + operands[4].access: READ operands[5].type: REG = r7 + operands[5].access: READ Write-back: True + Registers read: r0 r1 r4 r5 r6 r7 + Registers modified: r0 -0x100c: movs r0, r0 +0x8000100c: movs r0, r0 op_count: 2 operands[0].type: REG = r0 + operands[0].access: WRITE operands[1].type: REG = r0 + operands[1].access: READ Update-flags: True + Registers read: r0 + Registers modified: cpsr r0 -0x100e: mov.w r1, #0 +0x8000100e: mov.w r1, #0 op_count: 2 operands[0].type: REG = r1 + operands[0].access: WRITE operands[1].type: IMM = 0x0 + Registers modified: r1 -0x1012: ldr r6, [r0, #0x44] +0x80001012: ldr r6, [r0, #0x44] op_count: 2 operands[0].type: REG = r6 + operands[0].access: WRITE operands[1].type: MEM operands[1].mem.base: REG = r0 operands[1].mem.disp: 0x44 + operands[1].access: READ + Registers read: r0 + Registers modified: r6 -0x1014: +0x80001014: **************** Platform: Thumb-2 & register named with numbers Code:0x4f 0xf0 0x00 0x01 0xbd 0xe8 0x00 0x88 0xd1 0xe8 0x00 0xf0 0x18 0xbf 0xad 0xbf 0xf3 0xff 0x0b 0x0c 0x86 0xf3 0x00 0x89 0x80 0xf3 0x00 0x8c 0x4f 0xfa 0x99 0xf6 0xd0 0xff 0xa2 0x01 Disasm: -0x1000: mov.w r1, #0 +0x80001000: mov.w r1, #0 op_count: 2 operands[0].type: REG = r1 + operands[0].access: WRITE operands[1].type: IMM = 0x0 + Registers modified: r1 -0x1004: pop.w {r11, pc} +0x80001004: pop.w {r11, pc} op_count: 2 operands[0].type: REG = r11 + operands[0].access: WRITE operands[1].type: REG = pc + operands[1].access: WRITE + Registers read: sp + Registers modified: sp r11 pc -0x1008: tbb [r1, r0] +0x80001008: tbb [r1, r0] op_count: 1 operands[0].type: MEM operands[0].mem.base: REG = r1 operands[0].mem.index: REG = r0 + operands[0].access: READ + Registers read: r1 r0 -0x100c: it ne +0x8000100c: it ne Code condition: 2 + Registers modified: itstate -0x100e: iteet ge +0x8000100e: iteet ge Code condition: 11 + Registers modified: itstate -0x1010: vdupne.8 d16, d11[1] +0x80001010: vdupne.8 d16, d11[1] op_count: 2 operands[0].type: REG = d16 + operands[0].access: WRITE operands[1].type: REG = d11 + operands[1].access: READ operands[1].vector_index = 1 Code condition: 2 Vector-size: 8 + Registers read: d11 + Registers modified: d16 -0x1014: msr cpsr_fc, r6 +0x80001014: msr cpsr_fc, r6 op_count: 2 operands[0].type: SYSREG = 144 operands[1].type: REG = r6 + operands[1].access: READ + Registers read: r6 -0x1018: msr apsr_nzcvqg, r0 +0x80001018: msr apsr_nzcvqg, r0 op_count: 2 operands[0].type: SYSREG = 259 operands[1].type: REG = r0 + operands[1].access: READ + Registers read: r0 -0x101c: sxtb.w r6, r9, ror #8 +0x8000101c: sxtb.w r6, r9, ror #8 op_count: 2 operands[0].type: REG = r6 + operands[0].access: WRITE operands[1].type: REG = r9 + operands[1].access: READ Shift: 4 = 8 + Registers read: r9 + Registers modified: r6 -0x1020: vaddw.u16 q8, q8, d18 +0x80001020: vaddw.u16 q8, q8, d18 op_count: 3 operands[0].type: REG = q8 + operands[0].access: WRITE operands[1].type: REG = q8 + operands[1].access: READ operands[2].type: REG = d18 + operands[2].access: READ Vector-data: 10 + Registers read: q8 d18 + Registers modified: q8 -0x1024: +0x80001024: **************** Platform: Thumb-MClass Code:0xef 0xf3 0x02 0x80 Disasm: -0x1000: mrs r0, eapsr +0x80001000: mrs r0, eapsr op_count: 2 operands[0].type: REG = r0 - operands[1].type: SYSREG = 263 + operands[0].access: WRITE + operands[1].type: SYSREG = 264 + Registers modified: r0 -0x1004: +0x80001004: **************** Platform: Arm-V8 Code:0xe0 0x3b 0xb2 0xee 0x42 0x00 0x01 0xe1 0x51 0xf0 0x7f 0xf5 Disasm: -0x1000: vcvtt.f64.f16 d3, s1 +0x80001000: vcvtt.f64.f16 d3, s1 op_count: 2 operands[0].type: REG = d3 + operands[0].access: WRITE operands[1].type: REG = s1 + operands[1].access: READ Vector-data: 17 + Registers read: s1 + Registers modified: d3 -0x1004: crc32b r0, r1, r2 +0x80001004: crc32b r0, r1, r2 op_count: 3 operands[0].type: REG = r0 + operands[0].access: WRITE operands[1].type: REG = r1 + operands[1].access: READ operands[2].type: REG = r2 + operands[2].access: READ + Registers read: r1 r2 + Registers modified: r0 -0x1008: dmb oshld +0x80001008: dmb oshld Memory-barrier: 2 -0x100c: +0x8000100c: diff --git a/arm64.SPEC b/arm64.SPEC index aaebd36..0031131 100644 --- a/arm64.SPEC +++ b/arm64.SPEC @@ -5,112 +5,177 @@ Disasm: 0x2c: mrs x9, midr_el1 op_count: 2 operands[0].type: REG = x9 + operands[0].access: READ | WRITE operands[1].type: REG_MRS = 0xc000 + operands[1].access: READ | WRITE + Registers read: x9 + Registers modified: x9 0x30: msr spsel, #0 op_count: 2 operands[0].type: PSTATE = 0x5 + operands[0].access: READ | WRITE operands[1].type: IMM = 0x0 + operands[1].access: READ Update-flags: True + Registers modified: nzcv 0x34: msr dbgdtrtx_el0, x12 op_count: 2 operands[0].type: REG_MSR = 0x9828 + operands[0].access: READ | WRITE operands[1].type: REG = x12 + operands[1].access: READ | WRITE + Registers read: x12 + Registers modified: x12 0x38: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b op_count: 5 operands[0].type: REG = v0 + operands[0].access: READ | WRITE Vector Arrangement Specifier: 0x1 operands[1].type: REG = v1 + operands[1].access: READ Vector Arrangement Specifier: 0x2 operands[2].type: REG = v2 + operands[2].access: READ Vector Arrangement Specifier: 0x2 operands[3].type: REG = v3 + operands[3].access: READ Vector Arrangement Specifier: 0x2 operands[4].type: REG = v2 Vector Arrangement Specifier: 0x1 + Registers read: v0 v1 v2 v3 + Registers modified: v0 0x3c: scvtf v0.2s, v1.2s, #3 op_count: 3 operands[0].type: REG = v0 + operands[0].access: WRITE Vector Arrangement Specifier: 0x5 operands[1].type: REG = v1 + operands[1].access: READ Vector Arrangement Specifier: 0x5 operands[2].type: IMM = 0x3 + operands[2].access: READ + Registers read: v1 + Registers modified: v0 0x40: fmla s0, s0, v0.s[3] op_count: 3 operands[0].type: REG = s0 + operands[0].access: READ | WRITE operands[1].type: REG = s0 + operands[1].access: READ operands[2].type: REG = v0 + operands[2].access: READ Vector Element Size Specifier: 3 Vector Index: 3 + Registers read: s0 v0 + Registers modified: s0 0x44: fmov x2, v5.d[1] op_count: 2 operands[0].type: REG = x2 + operands[0].access: WRITE operands[1].type: REG = v5 + operands[1].access: READ Vector Element Size Specifier: 4 Vector Index: 1 + Registers read: v5 + Registers modified: x2 0x48: dsb nsh op_count: 1 operands[0].type: BARRIER = 0x7 + operands[0].access: READ 0x4c: dmb osh op_count: 1 operands[0].type: BARRIER = 0x3 + operands[0].access: READ 0x50: isb 0x54: mul x1, x1, x2 op_count: 3 operands[0].type: REG = x1 + operands[0].access: WRITE operands[1].type: REG = x1 + operands[1].access: READ operands[2].type: REG = x2 + operands[2].access: READ + Registers read: x1 x2 + Registers modified: x1 0x58: lsr w1, w1, #0 op_count: 3 operands[0].type: REG = w1 + operands[0].access: READ | WRITE operands[1].type: REG = w1 + operands[1].access: READ operands[2].type: IMM = 0x0 + operands[2].access: READ + Registers read: w1 + Registers modified: w1 0x5c: sub w0, w0, w1, uxtw op_count: 3 operands[0].type: REG = w0 + operands[0].access: WRITE operands[1].type: REG = w0 + operands[1].access: READ operands[2].type: REG = w1 + operands[2].access: READ Ext: 3 + Registers read: w0 w1 + Registers modified: w0 0x60: ldr w1, [sp, #8] op_count: 2 operands[0].type: REG = w1 + operands[0].access: WRITE operands[1].type: MEM operands[1].mem.base: REG = sp operands[1].mem.disp: 0x8 + operands[1].access: READ + Registers read: sp + Registers modified: w1 0x64: cneg x0, x1, ne op_count: 2 operands[0].type: REG = x0 + operands[0].access: WRITE operands[1].type: REG = x1 + operands[1].access: READ Code-condition: 2 + Registers read: nzcv x1 + Registers modified: x0 0x68: add x0, x1, x2, lsl #2 op_count: 3 operands[0].type: REG = x0 + operands[0].access: WRITE operands[1].type: REG = x1 + operands[1].access: READ operands[2].type: REG = x2 + operands[2].access: READ Shift: type = 1, value = 2 + Registers read: x1 x2 + Registers modified: x0 0x6c: ldr q16, [x24, w8, uxtw #4] op_count: 2 operands[0].type: REG = q16 + operands[0].access: WRITE operands[1].type: MEM operands[1].mem.base: REG = x24 operands[1].mem.index: REG = w8 + operands[1].access: READ Shift: type = 1, value = 4 Ext: 3 + Registers read: x24 w8 + Registers modified: q16 0x70: diff --git a/arm64_constants.go b/arm64_constants.go index fe0cf61..182b865 100644 --- a/arm64_constants.go +++ b/arm64_constants.go @@ -8,8 +8,8 @@ try reading the *_test.go files. (c) 2013 COSEINC. All Rights Reserved. THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT! - Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/ - 2016-04-13T12:04:37+09:30 + Command: ./genconst /Users/scottknight/work/capstone/bindings/python/capstone/ + 2019-02-02T13:26:27-05:00 */ @@ -1068,6 +1068,8 @@ const ( ARM64_INS_DC = C.ARM64_INS_DC ARM64_INS_AT = C.ARM64_INS_AT ARM64_INS_TLBI = C.ARM64_INS_TLBI + ARM64_INS_NEGS = C.ARM64_INS_NEGS + ARM64_INS_NGCS = C.ARM64_INS_NGCS ARM64_INS_ENDING = C.ARM64_INS_ENDING ) @@ -1078,7 +1080,12 @@ const ( // Generic groups const ( - ARM64_GRP_JUMP = C.ARM64_GRP_JUMP + ARM64_GRP_JUMP = C.ARM64_GRP_JUMP + ARM64_GRP_CALL = C.ARM64_GRP_CALL + ARM64_GRP_RET = C.ARM64_GRP_RET + ARM64_GRP_INT = C.ARM64_GRP_INT + ARM64_GRP_PRIVILEGE = C.ARM64_GRP_PRIVILEGE + ARM64_GRP_BRANCH_RELATIVE = C.ARM64_GRP_BRANCH_RELATIVE ) // Architecture-specific groups diff --git a/arm64_decomposer.go b/arm64_decomposer.go index e5955fc..2e5d310 100644 --- a/arm64_decomposer.go +++ b/arm64_decomposer.go @@ -51,6 +51,7 @@ type Arm64Operand struct { Sys uint Prefetch int Barrier int + Access uint } type Arm64MemoryOperand struct { @@ -109,6 +110,7 @@ func fillArm64Header(raw C.cs_insn, insn *Instruction) { VectorIndex: int(cop.vector_index), Vas: int(cop.vas), Vess: int(cop.vess), + Access: uint(cop.access), } switch cop._type { @@ -142,11 +144,11 @@ func fillArm64Header(raw C.cs_insn, insn *Instruction) { insn.Arm64 = &arm64 } -func decomposeArm64(raws []C.cs_insn) []Instruction { +func decomposeArm64(e *Engine, raws []C.cs_insn) []Instruction { decomposed := []Instruction{} for _, raw := range raws { decomp := new(Instruction) - fillGenericHeader(raw, decomp) + fillGenericHeader(e, raw, decomp) fillArm64Header(raw, decomp) decomposed = append(decomposed, *decomp) } diff --git a/arm64_decomposer_test.go b/arm64_decomposer_test.go index 6ddd586..091e4f6 100644 --- a/arm64_decomposer_test.go +++ b/arm64_decomposer_test.go @@ -60,6 +60,15 @@ func arm64InsnDetail(insn Instruction, engine *Engine, buf *bytes.Buffer) { fmt.Fprintf(buf, "\t\toperands[%v].type: BARRIER = 0x%x\n", i, op.Barrier) } + switch op.Access { + case CS_AC_READ: + fmt.Fprintf(buf, "\t\toperands[%v].access: READ\n", i) + case CS_AC_WRITE: + fmt.Fprintf(buf, "\t\toperands[%v].access: WRITE\n", i) + case CS_AC_READ | CS_AC_WRITE: + fmt.Fprintf(buf, "\t\toperands[%v].access: READ | WRITE\n", i) + } + if op.Shift.Type != ARM64_SFT_INVALID && op.Shift.Value != 0 { // shift with constant value fmt.Fprintf(buf, "\t\t\tShift: type = %v, value = %v\n", op.Shift.Type, op.Shift.Value) @@ -87,6 +96,23 @@ func arm64InsnDetail(insn Instruction, engine *Engine, buf *bytes.Buffer) { if insn.Arm64.CC != ARM64_CC_AL && insn.Arm64.CC != ARM64_CC_INVALID { fmt.Fprintf(buf, "\tCode-condition: %v\n", insn.Arm64.CC) } + + if len(insn.AllRegistersRead) > 0 { + fmt.Fprintf(buf, "\tRegisters read:") + for _, reg := range insn.AllRegistersRead { + fmt.Fprintf(buf, " %s", engine.RegName(reg)) + } + fmt.Fprintf(buf, "\n") + } + + if len(insn.AllRegistersWritten) > 0 { + fmt.Fprintf(buf, "\tRegisters modified:") + for _, reg := range insn.AllRegistersWritten { + fmt.Fprintf(buf, " %s", engine.RegName(reg)) + } + fmt.Fprintf(buf, "\n") + } + fmt.Fprintf(buf, "\n") } diff --git a/arm_constants.go b/arm_constants.go index ac81044..e4330ac 100644 --- a/arm_constants.go +++ b/arm_constants.go @@ -8,8 +8,8 @@ try reading the *_test.go files. (c) 2013 COSEINC. All Rights Reserved. THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT! - Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/ - 2016-04-13T12:04:37+09:30 + Command: ./genconst /Users/scottknight/work/capstone/bindings/python/capstone/ + 2019-02-02T13:26:27-05:00 */ @@ -76,12 +76,15 @@ const ( ARM_SYSREG_IAPSR = C.ARM_SYSREG_IAPSR ARM_SYSREG_IAPSR_G = C.ARM_SYSREG_IAPSR_G ARM_SYSREG_IAPSR_NZCVQG = C.ARM_SYSREG_IAPSR_NZCVQG + ARM_SYSREG_IAPSR_NZCVQ = C.ARM_SYSREG_IAPSR_NZCVQ ARM_SYSREG_EAPSR = C.ARM_SYSREG_EAPSR ARM_SYSREG_EAPSR_G = C.ARM_SYSREG_EAPSR_G ARM_SYSREG_EAPSR_NZCVQG = C.ARM_SYSREG_EAPSR_NZCVQG + ARM_SYSREG_EAPSR_NZCVQ = C.ARM_SYSREG_EAPSR_NZCVQ ARM_SYSREG_XPSR = C.ARM_SYSREG_XPSR ARM_SYSREG_XPSR_G = C.ARM_SYSREG_XPSR_G ARM_SYSREG_XPSR_NZCVQG = C.ARM_SYSREG_XPSR_NZCVQG + ARM_SYSREG_XPSR_NZCVQ = C.ARM_SYSREG_XPSR_NZCVQ ARM_SYSREG_IPSR = C.ARM_SYSREG_IPSR ARM_SYSREG_EPSR = C.ARM_SYSREG_EPSR ARM_SYSREG_IEPSR = C.ARM_SYSREG_IEPSR @@ -92,6 +95,39 @@ const ( ARM_SYSREG_BASEPRI_MAX = C.ARM_SYSREG_BASEPRI_MAX ARM_SYSREG_FAULTMASK = C.ARM_SYSREG_FAULTMASK ARM_SYSREG_CONTROL = C.ARM_SYSREG_CONTROL + ARM_SYSREG_R8_USR = C.ARM_SYSREG_R8_USR + ARM_SYSREG_R9_USR = C.ARM_SYSREG_R9_USR + ARM_SYSREG_R10_USR = C.ARM_SYSREG_R10_USR + ARM_SYSREG_R11_USR = C.ARM_SYSREG_R11_USR + ARM_SYSREG_R12_USR = C.ARM_SYSREG_R12_USR + ARM_SYSREG_SP_USR = C.ARM_SYSREG_SP_USR + ARM_SYSREG_LR_USR = C.ARM_SYSREG_LR_USR + ARM_SYSREG_R8_FIQ = C.ARM_SYSREG_R8_FIQ + ARM_SYSREG_R9_FIQ = C.ARM_SYSREG_R9_FIQ + ARM_SYSREG_R10_FIQ = C.ARM_SYSREG_R10_FIQ + ARM_SYSREG_R11_FIQ = C.ARM_SYSREG_R11_FIQ + ARM_SYSREG_R12_FIQ = C.ARM_SYSREG_R12_FIQ + ARM_SYSREG_SP_FIQ = C.ARM_SYSREG_SP_FIQ + ARM_SYSREG_LR_FIQ = C.ARM_SYSREG_LR_FIQ + ARM_SYSREG_LR_IRQ = C.ARM_SYSREG_LR_IRQ + ARM_SYSREG_SP_IRQ = C.ARM_SYSREG_SP_IRQ + ARM_SYSREG_LR_SVC = C.ARM_SYSREG_LR_SVC + ARM_SYSREG_SP_SVC = C.ARM_SYSREG_SP_SVC + ARM_SYSREG_LR_ABT = C.ARM_SYSREG_LR_ABT + ARM_SYSREG_SP_ABT = C.ARM_SYSREG_SP_ABT + ARM_SYSREG_LR_UND = C.ARM_SYSREG_LR_UND + ARM_SYSREG_SP_UND = C.ARM_SYSREG_SP_UND + ARM_SYSREG_LR_MON = C.ARM_SYSREG_LR_MON + ARM_SYSREG_SP_MON = C.ARM_SYSREG_SP_MON + ARM_SYSREG_ELR_HYP = C.ARM_SYSREG_ELR_HYP + ARM_SYSREG_SP_HYP = C.ARM_SYSREG_SP_HYP + ARM_SYSREG_SPSR_FIQ = C.ARM_SYSREG_SPSR_FIQ + ARM_SYSREG_SPSR_IRQ = C.ARM_SYSREG_SPSR_IRQ + ARM_SYSREG_SPSR_SVC = C.ARM_SYSREG_SPSR_SVC + ARM_SYSREG_SPSR_ABT = C.ARM_SYSREG_SPSR_ABT + ARM_SYSREG_SPSR_UND = C.ARM_SYSREG_SPSR_UND + ARM_SYSREG_SPSR_MON = C.ARM_SYSREG_SPSR_MON + ARM_SYSREG_SPSR_HYP = C.ARM_SYSREG_SPSR_HYP ) // The memory barrier constants map directly to the 4-bit encoding of @@ -357,6 +393,7 @@ const ( ARM_INS_DMB = C.ARM_INS_DMB ARM_INS_DSB = C.ARM_INS_DSB ARM_INS_EOR = C.ARM_INS_EOR + ARM_INS_ERET = C.ARM_INS_ERET ARM_INS_VMOV = C.ARM_INS_VMOV ARM_INS_FLDMDBX = C.ARM_INS_FLDMDBX ARM_INS_FLDMIAX = C.ARM_INS_FLDMIAX @@ -365,6 +402,7 @@ const ( ARM_INS_FSTMIAX = C.ARM_INS_FSTMIAX ARM_INS_HINT = C.ARM_INS_HINT ARM_INS_HLT = C.ARM_INS_HLT + ARM_INS_HVC = C.ARM_INS_HVC ARM_INS_ISB = C.ARM_INS_ISB ARM_INS_LDA = C.ARM_INS_LDA ARM_INS_LDAB = C.ARM_INS_LDAB @@ -735,18 +773,14 @@ const ( ARM_INS_IT = C.ARM_INS_IT ARM_INS_LSL = C.ARM_INS_LSL ARM_INS_LSR = C.ARM_INS_LSR - ARM_INS_ASRS = C.ARM_INS_ASRS - ARM_INS_LSRS = C.ARM_INS_LSRS ARM_INS_ORN = C.ARM_INS_ORN ARM_INS_ROR = C.ARM_INS_ROR ARM_INS_RRX = C.ARM_INS_RRX - ARM_INS_SUBS = C.ARM_INS_SUBS ARM_INS_SUBW = C.ARM_INS_SUBW ARM_INS_TBB = C.ARM_INS_TBB ARM_INS_TBH = C.ARM_INS_TBH ARM_INS_CBNZ = C.ARM_INS_CBNZ ARM_INS_CBZ = C.ARM_INS_CBZ - ARM_INS_MOVS = C.ARM_INS_MOVS ARM_INS_POP = C.ARM_INS_POP ARM_INS_PUSH = C.ARM_INS_PUSH ARM_INS_NOP = C.ARM_INS_NOP @@ -767,41 +801,46 @@ const ( // Generic groups const ( - ARM_GRP_JUMP = C.ARM_GRP_JUMP + ARM_GRP_JUMP = C.ARM_GRP_JUMP + ARM_GRP_CALL = C.ARM_GRP_CALL + ARM_GRP_INT = C.ARM_GRP_INT + ARM_GRP_PRIVILEGE = C.ARM_GRP_PRIVILEGE + ARM_GRP_BRANCH_RELATIVE = C.ARM_GRP_BRANCH_RELATIVE ) // Architecture-specific groups const ( - ARM_GRP_CRYPTO = C.ARM_GRP_CRYPTO - ARM_GRP_DATABARRIER = C.ARM_GRP_DATABARRIER - ARM_GRP_DIVIDE = C.ARM_GRP_DIVIDE - ARM_GRP_FPARMV8 = C.ARM_GRP_FPARMV8 - ARM_GRP_MULTPRO = C.ARM_GRP_MULTPRO - ARM_GRP_NEON = C.ARM_GRP_NEON - ARM_GRP_T2EXTRACTPACK = C.ARM_GRP_T2EXTRACTPACK - ARM_GRP_THUMB2DSP = C.ARM_GRP_THUMB2DSP - ARM_GRP_TRUSTZONE = C.ARM_GRP_TRUSTZONE - ARM_GRP_V4T = C.ARM_GRP_V4T - ARM_GRP_V5T = C.ARM_GRP_V5T - ARM_GRP_V5TE = C.ARM_GRP_V5TE - ARM_GRP_V6 = C.ARM_GRP_V6 - ARM_GRP_V6T2 = C.ARM_GRP_V6T2 - ARM_GRP_V7 = C.ARM_GRP_V7 - ARM_GRP_V8 = C.ARM_GRP_V8 - ARM_GRP_VFP2 = C.ARM_GRP_VFP2 - ARM_GRP_VFP3 = C.ARM_GRP_VFP3 - ARM_GRP_VFP4 = C.ARM_GRP_VFP4 - ARM_GRP_ARM = C.ARM_GRP_ARM - ARM_GRP_MCLASS = C.ARM_GRP_MCLASS - ARM_GRP_NOTMCLASS = C.ARM_GRP_NOTMCLASS - ARM_GRP_THUMB = C.ARM_GRP_THUMB - ARM_GRP_THUMB1ONLY = C.ARM_GRP_THUMB1ONLY - ARM_GRP_THUMB2 = C.ARM_GRP_THUMB2 - ARM_GRP_PREV8 = C.ARM_GRP_PREV8 - ARM_GRP_FPVMLX = C.ARM_GRP_FPVMLX - ARM_GRP_MULOPS = C.ARM_GRP_MULOPS - ARM_GRP_CRC = C.ARM_GRP_CRC - ARM_GRP_DPVFP = C.ARM_GRP_DPVFP - ARM_GRP_V6M = C.ARM_GRP_V6M - ARM_GRP_ENDING = C.ARM_GRP_ENDING + ARM_GRP_CRYPTO = C.ARM_GRP_CRYPTO + ARM_GRP_DATABARRIER = C.ARM_GRP_DATABARRIER + ARM_GRP_DIVIDE = C.ARM_GRP_DIVIDE + ARM_GRP_FPARMV8 = C.ARM_GRP_FPARMV8 + ARM_GRP_MULTPRO = C.ARM_GRP_MULTPRO + ARM_GRP_NEON = C.ARM_GRP_NEON + ARM_GRP_T2EXTRACTPACK = C.ARM_GRP_T2EXTRACTPACK + ARM_GRP_THUMB2DSP = C.ARM_GRP_THUMB2DSP + ARM_GRP_TRUSTZONE = C.ARM_GRP_TRUSTZONE + ARM_GRP_V4T = C.ARM_GRP_V4T + ARM_GRP_V5T = C.ARM_GRP_V5T + ARM_GRP_V5TE = C.ARM_GRP_V5TE + ARM_GRP_V6 = C.ARM_GRP_V6 + ARM_GRP_V6T2 = C.ARM_GRP_V6T2 + ARM_GRP_V7 = C.ARM_GRP_V7 + ARM_GRP_V8 = C.ARM_GRP_V8 + ARM_GRP_VFP2 = C.ARM_GRP_VFP2 + ARM_GRP_VFP3 = C.ARM_GRP_VFP3 + ARM_GRP_VFP4 = C.ARM_GRP_VFP4 + ARM_GRP_ARM = C.ARM_GRP_ARM + ARM_GRP_MCLASS = C.ARM_GRP_MCLASS + ARM_GRP_NOTMCLASS = C.ARM_GRP_NOTMCLASS + ARM_GRP_THUMB = C.ARM_GRP_THUMB + ARM_GRP_THUMB1ONLY = C.ARM_GRP_THUMB1ONLY + ARM_GRP_THUMB2 = C.ARM_GRP_THUMB2 + ARM_GRP_PREV8 = C.ARM_GRP_PREV8 + ARM_GRP_FPVMLX = C.ARM_GRP_FPVMLX + ARM_GRP_MULOPS = C.ARM_GRP_MULOPS + ARM_GRP_CRC = C.ARM_GRP_CRC + ARM_GRP_DPVFP = C.ARM_GRP_DPVFP + ARM_GRP_V6M = C.ARM_GRP_V6M + ARM_GRP_VIRTUALIZATION = C.ARM_GRP_VIRTUALIZATION + ARM_GRP_ENDING = C.ARM_GRP_ENDING ) diff --git a/arm_decomposer.go b/arm_decomposer.go index 4069782..1b27527 100644 --- a/arm_decomposer.go +++ b/arm_decomposer.go @@ -51,13 +51,16 @@ type ArmOperand struct { Mem ArmMemoryOperand Setend int Subtracted bool + Access uint + NeonLane int } type ArmMemoryOperand struct { - Base uint - Index uint - Scale int - Disp int + Base uint + Index uint + Scale int + Disp int + LShift int } // Number of Operands of a given ARM_OP_* type @@ -112,6 +115,8 @@ func fillArmHeader(raw C.cs_insn, insn *Instruction) { Type: uint(cop._type), VectorIndex: int(cop.vector_index), Subtracted: bool(cop.subtracted), + Access: uint(cop.access), + NeonLane: int(cop.neon_lane), } switch cop._type { // fake a union by setting only the correct struct member @@ -124,10 +129,11 @@ func fillArmHeader(raw C.cs_insn, insn *Instruction) { case ARM_OP_MEM: cmop := (*C.arm_op_mem)(unsafe.Pointer(&cop.anon0[0])) gop.Mem = ArmMemoryOperand{ - Base: uint(cmop.base), - Index: uint(cmop.index), - Scale: int(cmop.scale), - Disp: int(cmop.disp), + Base: uint(cmop.base), + Index: uint(cmop.index), + Scale: int(cmop.scale), + Disp: int(cmop.disp), + LShift: int(cmop.lshift), } case ARM_OP_SETEND: gop.Setend = int(*(*C.int)(unsafe.Pointer(&cop.anon0[0]))) @@ -137,11 +143,11 @@ func fillArmHeader(raw C.cs_insn, insn *Instruction) { insn.Arm = &arm } -func decomposeArm(raws []C.cs_insn) []Instruction { +func decomposeArm(e *Engine, raws []C.cs_insn) []Instruction { decomposed := []Instruction{} for _, raw := range raws { decomp := new(Instruction) - fillGenericHeader(raw, decomp) + fillGenericHeader(e, raw, decomp) fillArmHeader(raw, decomp) decomposed = append(decomposed, *decomp) } diff --git a/arm_decomposer_test.go b/arm_decomposer_test.go index 1072f42..e0757da 100644 --- a/arm_decomposer_test.go +++ b/arm_decomposer_test.go @@ -27,7 +27,7 @@ func armInsnDetail(insn Instruction, engine *Engine, buf *bytes.Buffer) { case ARM_OP_REG: fmt.Fprintf(buf, "\t\toperands[%v].type: REG = %v\n", i, engine.RegName(op.Reg)) case ARM_OP_IMM: - fmt.Fprintf(buf, "\t\toperands[%v].type: IMM = 0x%x\n", i, (uint64(op.Imm))) + fmt.Fprintf(buf, "\t\toperands[%v].type: IMM = 0x%x\n", i, (uint32(op.Imm))) case ARM_OP_FP: fmt.Fprintf(buf, "\t\toperands[%v].type: FP = %f\n", i, op.FP) case ARM_OP_MEM: @@ -46,6 +46,9 @@ func armInsnDetail(insn Instruction, engine *Engine, buf *bytes.Buffer) { if op.Mem.Disp != 0 { fmt.Fprintf(buf, "\t\t\toperands[%v].mem.disp: 0x%x\n", i, uint32(op.Mem.Disp)) } + if op.Mem.LShift != 0 { + fmt.Fprintf(buf, "\t\t\toperands[%v].mem.lshift: 0x%x\n", i, uint32(op.Mem.LShift)) + } case ARM_OP_PIMM: fmt.Fprintf(buf, "\t\toperands[%v].type: P-IMM = %v\n", i, op.Imm) case ARM_OP_CIMM: @@ -61,6 +64,19 @@ func armInsnDetail(insn Instruction, engine *Engine, buf *bytes.Buffer) { } + if op.NeonLane != -1 { + fmt.Fprintf(buf, "\t\toperands[%v].neon_lane = %v\n", i, op.NeonLane) + } + + switch op.Access { + case CS_AC_READ: + fmt.Fprintf(buf, "\t\toperands[%v].access: READ\n", i) + case CS_AC_WRITE: + fmt.Fprintf(buf, "\t\toperands[%v].access: WRITE\n", i) + case CS_AC_READ | CS_AC_WRITE: + fmt.Fprintf(buf, "\t\toperands[%v].access: READ | WRITE\n", i) + } + if op.Shift.Type != ARM_SFT_INVALID && op.Shift.Value != 0 { if op.Shift.Type < ARM_SFT_ASR_REG { // shift with constant value @@ -114,6 +130,22 @@ func armInsnDetail(insn Instruction, engine *Engine, buf *bytes.Buffer) { fmt.Fprintf(buf, "\tMemory-barrier: %v\n", insn.Arm.MemBarrier) } + if len(insn.AllRegistersRead) > 0 { + fmt.Fprintf(buf, "\tRegisters read:") + for _, reg := range insn.AllRegistersRead { + fmt.Fprintf(buf, " %s", engine.RegName(reg)) + } + fmt.Fprintf(buf, "\n") + } + + if len(insn.AllRegistersWritten) > 0 { + fmt.Fprintf(buf, "\tRegisters modified:") + for _, reg := range insn.AllRegistersWritten { + fmt.Fprintf(buf, " %s", engine.RegName(reg)) + } + fmt.Fprintf(buf, "\n") + } + fmt.Fprintf(buf, "\n") } @@ -121,6 +153,7 @@ func TestArm(t *testing.T) { t.Parallel() + var address = uint64(0x80001000) final := new(bytes.Buffer) spec_file := "arm.SPEC" diff --git a/bench_iter_test.go b/bench_iter_test.go index 9934497..07c8ad8 100644 --- a/bench_iter_test.go +++ b/bench_iter_test.go @@ -11,7 +11,7 @@ func benchmarkBasicX86(scale int, b *testing.B) { engine, err := New(CS_ARCH_X86, CS_MODE_32) if err != nil { - b.Fatal("Failed to initialize engine: %v", err) + b.Fatalf("Failed to initialize engine: %v", err) } defer engine.Close() @@ -33,7 +33,7 @@ func benchmarkBasicX86(scale int, b *testing.B) { ) if err != nil { - b.Fatal("Disassembly error: %v", err) + b.Fatalf("Disassembly error: %v", err) } var count uint = 0 for _, insn := range insns { @@ -50,7 +50,7 @@ func benchmarkIterX86(scale int, b *testing.B) { engine, err := New(CS_ARCH_X86, CS_MODE_32) if err != nil { - b.Fatal("Failed to initialize engine: %v", err) + b.Fatalf("Failed to initialize engine: %v", err) } defer engine.Close() diff --git a/engine.go b/engine.go index 63f4c81..fc44be7 100644 --- a/engine.go +++ b/engine.go @@ -67,7 +67,7 @@ var dietMode = bool(C.cs_support(CS_SUPPORT_DIET)) type Engine struct { handle C.csh arch int - mode uint + mode int skipdata *C.cs_opt_skipdata } @@ -86,9 +86,11 @@ type InstructionHeader struct { // Not available without the decomposer. BE CAREFUL! By default, // CS_OPT_DETAIL is set to CS_OPT_OFF so the result of accessing these // members is undefined. - RegistersRead []uint // List of implicit registers read by this instruction - RegistersWritten []uint // List of implicit registers written by this instruction - Groups []uint // List of *_GRP_* groups this instruction belongs to. + AllRegistersRead []uint // List of implicit and explicit registers read by this instruction + AllRegistersWritten []uint // List of implicit and explicit registers written by this instruction + RegistersRead []uint // List of implicit registers read by this instruction + RegistersWritten []uint // List of implicit registers written by this instruction + Groups []uint // List of *_GRP_* groups this instruction belongs to. } // arch specific information will be filled in for exactly one of the @@ -96,18 +98,18 @@ type InstructionHeader struct { // fill in only the Arm structure member. type Instruction struct { InstructionHeader - Arm *ArmInstruction + X86 *X86Instruction Arm64 *Arm64Instruction + Arm *ArmInstruction Mips *MipsInstruction - X86 *X86Instruction PPC *PPCInstruction - SysZ *SysZInstruction Sparc *SparcInstruction + SysZ *SysZInstruction Xcore *XcoreInstruction } // Called by the arch specific decomposers -func fillGenericHeader(raw C.cs_insn, insn *Instruction) { +func fillGenericHeader(e *Engine, raw C.cs_insn, insn *Instruction) { insn.Id = uint(raw.id) insn.Address = uint(raw.address) @@ -136,6 +138,28 @@ func fillGenericHeader(raw C.cs_insn, insn *Instruction) { for i := 0; i < int(raw.detail.groups_count); i++ { insn.Groups = append(insn.Groups, uint(raw.detail.groups[i])) } + + var regsRead C.cs_regs + var regsReadCount C.uint8_t + var regsWrite C.cs_regs + var regsWriteCount C.uint8_t + res := C.cs_regs_access( + e.handle, + &raw, + ®sRead[0], + ®sReadCount, + ®sWrite[0], + ®sWriteCount) + + if Errno(res) == ErrOK { + for i := 0; i < int(regsReadCount); i++ { + insn.AllRegistersRead = append(insn.AllRegistersRead, uint(regsRead[i])) + } + + for i := 0; i < int(regsWriteCount); i++ { + insn.AllRegistersWritten = append(insn.AllRegistersWritten, uint(regsWrite[i])) + } + } } } @@ -153,7 +177,7 @@ func (e *Engine) Close() error { func (e *Engine) Arch() int { return e.arch } // Accessor for the Engine mode CS_MODE_* -func (e *Engine) Mode() uint { return e.mode } +func (e *Engine) Mode() int { return e.mode } // Check if a particular arch is supported by this engine. // To verify if this engine supports everything, use CS_ARCH_ALL @@ -247,28 +271,38 @@ func (e *Engine) Disasm(input []byte, address, count uint64) ([]Instruction, err switch e.arch { case CS_ARCH_ARM: - return decomposeArm(insns), nil + return decomposeArm(e, insns), nil case CS_ARCH_ARM64: - return decomposeArm64(insns), nil + return decomposeArm64(e, insns), nil case CS_ARCH_MIPS: - return decomposeMips(insns), nil + return decomposeMips(e, insns), nil case CS_ARCH_X86: - return decomposeX86(insns), nil + return decomposeX86(e, insns), nil case CS_ARCH_PPC: - return decomposePPC(insns), nil + return decomposePPC(e, insns), nil case CS_ARCH_SYSZ: - return decomposeSysZ(insns), nil + return decomposeSysZ(e, insns), nil case CS_ARCH_SPARC: - return decomposeSparc(insns), nil + return decomposeSparc(e, insns), nil case CS_ARCH_XCORE: - return decomposeXcore(insns), nil + return decomposeXcore(e, insns), nil default: - return []Instruction{}, ErrArch + return decomposeGeneric(e, insns), nil } } return []Instruction{}, e.Errno() } +func decomposeGeneric(e *Engine, raws []C.cs_insn) []Instruction { + decomposed := []Instruction{} + for _, raw := range raws { + decomp := new(Instruction) + fillGenericHeader(e, raw, decomp) + decomposed = append(decomposed, *decomp) + } + return decomposed +} + // user callback function prototype type SkipDataCB func(buffer []byte, offset int, userData interface{}) int @@ -331,7 +365,7 @@ func (e *Engine) SkipDataStop() { } // Create a new Engine with the specified arch and mode -func New(arch int, mode uint) (Engine, error) { +func New(arch int, mode int) (Engine, error) { var handle C.csh res := C.cs_open(C.cs_arch(arch), C.cs_mode(mode), &handle) if Errno(res) == ErrOK { diff --git a/engine_constants.go b/engine_constants.go index 6a1318f..bbf03d7 100644 --- a/engine_constants.go +++ b/engine_constants.go @@ -19,48 +19,71 @@ import "C" const ( // Engine Architectures - CS_ARCH_ARM = C.CS_ARCH_ARM // ARM architecture (including Thumb Thumb-2) - CS_ARCH_ARM64 = C.CS_ARCH_ARM64 // ARM-64, also called AArch64 - CS_ARCH_MIPS = C.CS_ARCH_MIPS // Mips architecture - CS_ARCH_X86 = C.CS_ARCH_X86 // X86 architecture (including x86 & x86-64) - CS_ARCH_PPC = C.CS_ARCH_PPC // PowerPC architecture - CS_ARCH_SPARC = C.CS_ARCH_SPARC // Sparc architecture - CS_ARCH_SYSZ = C.CS_ARCH_SYSZ // SystemZ architecture - CS_ARCH_XCORE = C.CS_ARCH_XCORE // Xcore architecture - CS_ARCH_MAX = C.CS_ARCH_MAX - CS_ARCH_ALL = C.CS_ARCH_ALL + CS_ARCH_ARM = C.CS_ARCH_ARM // ARM architecture (including Thumb Thumb-2) + CS_ARCH_ARM64 = C.CS_ARCH_ARM64 // ARM-64, also called AArch64 + CS_ARCH_MIPS = C.CS_ARCH_MIPS // Mips architecture + CS_ARCH_X86 = C.CS_ARCH_X86 // X86 architecture (including x86 & x86-64) + CS_ARCH_PPC = C.CS_ARCH_PPC // PowerPC architecture + CS_ARCH_SPARC = C.CS_ARCH_SPARC // Sparc architecture + CS_ARCH_SYSZ = C.CS_ARCH_SYSZ // SystemZ architecture + CS_ARCH_XCORE = C.CS_ARCH_XCORE // Xcore architecture + CS_ARCH_M68K = C.CS_ARCH_M68K // 68K architecture + CS_ARCH_TMS320C64X = C.CS_ARCH_TMS320C64X // TMS320C64x architecture + CS_ARCH_M680X = C.CS_ARCH_M680X // 680X architecture + CS_ARCH_EVM = C.CS_ARCH_EVM // Ethereum architecture + CS_ARCH_MAX = C.CS_ARCH_MAX + CS_ARCH_ALL = C.CS_ARCH_ALL ) const ( // Engine modes CS_MODE_LITTLE_ENDIAN = C.CS_MODE_LITTLE_ENDIAN // little endian mode (default mode) CS_MODE_ARM = C.CS_MODE_ARM // 32-bit ARM - CS_MODE_16 = C.CS_MODE_16 // 16-bit mode - CS_MODE_32 = C.CS_MODE_32 // 32-bit mode - CS_MODE_64 = C.CS_MODE_64 // 64-bit mode + CS_MODE_16 = C.CS_MODE_16 // 16-bit mode (X86) + CS_MODE_32 = C.CS_MODE_32 // 32-bit mode (X86) + CS_MODE_64 = C.CS_MODE_64 // 64-bit mode (X86, PPC) CS_MODE_THUMB = C.CS_MODE_THUMB // ARM's Thumb mode, including Thumb-2 CS_MODE_MCLASS = C.CS_MODE_MCLASS // ARM's Cortex-M series CS_MODE_V8 = C.CS_MODE_V8 // ARMv8 A32 encodings for ARM - CS_MODE_MICRO = C.CS_MODE_MICRO // MicroMips mode (MIPS architecture) + CS_MODE_MICRO = C.CS_MODE_MICRO // MicroMips mode (MIPS) CS_MODE_MIPS3 = C.CS_MODE_MIPS3 // Mips III ISA CS_MODE_MIPS32R6 = C.CS_MODE_MIPS32R6 // Mips32r6 ISA - CS_MODE_MIPSGP64 = C.CS_MODE_MIPSGP64 // General Purpose Registers are 64-bit wide (MIPS arch) - CS_MODE_V9 = C.CS_MODE_V9 // SparcV9 mode (Sparc architecture) - CS_MODE_BIG_ENDIAN = 1 << 31 // big endian mode + CS_MODE_MIPS2 = C.CS_MODE_MIPS2 // Mips II ISA + CS_MODE_V9 = C.CS_MODE_V9 // SparcV9 mode (Sparc) + CS_MODE_QPX = C.CS_MODE_QPX // Quad Processing eXtensions mode (PPC) + CS_MODE_M68K_000 = C.CS_MODE_M68K_000 // M68K 68000 mode + CS_MODE_M68K_010 = C.CS_MODE_M68K_010 // M68K 68010 mode + CS_MODE_M68K_020 = C.CS_MODE_M68K_020 // M68K 68020 mode + CS_MODE_M68K_030 = C.CS_MODE_M68K_030 // M68K 68030 mode + CS_MODE_M68K_040 = C.CS_MODE_M68K_040 // M68K 68040 mode + CS_MODE_M68K_060 = C.CS_MODE_M68K_060 // M68K 68060 mode + CS_MODE_BIG_ENDIAN = C.CS_MODE_BIG_ENDIAN // big-endian mode CS_MODE_MIPS32 = C.CS_MODE_MIPS32 // Mips32 ISA (Mips) CS_MODE_MIPS64 = C.CS_MODE_MIPS64 // Mips64 ISA (Mips) + CS_MODE_M680X_6301 = C.CS_MODE_M680X_6301 // M680X Hitachi 6301,6303 mode + CS_MODE_M680X_6309 = C.CS_MODE_M680X_6309 // M680X Hitachi 6309 mode + CS_MODE_M680X_6800 = C.CS_MODE_M680X_6800 // M680X Motorola 6800,6802 mode + CS_MODE_M680X_6801 = C.CS_MODE_M680X_6801 // M680X Motorola 6801,6803 mode + CS_MODE_M680X_6805 = C.CS_MODE_M680X_6805 // M680X Motorola/Freescale 6805 mode + CS_MODE_M680X_6808 = C.CS_MODE_M680X_6808 // M680X Motorola/Freescale/NXP 68HC08 mode + CS_MODE_M680X_6809 = C.CS_MODE_M680X_6809 // M680X Motorola 6809 mode + CS_MODE_M680X_6811 = C.CS_MODE_M680X_6811 // M680X Motorola/Freescale/NXP 68HC11 mode + CS_MODE_M680X_CPU12 = C.CS_MODE_M680X_CPU12 // M680X Motorola/Freescale/NXP CPU12 used on M68HC12/HCS12 + CS_MODE_M680X_HCS08 = C.CS_MODE_M680X_HCS08 // M680X Freescale/NXP HCS08 mode ) const ( // Engine Options types + CS_OPT_INVALID = C.CS_OPT_INVALID // No option specified CS_OPT_SYNTAX = C.CS_OPT_SYNTAX // Asssembly output syntax CS_OPT_DETAIL = C.CS_OPT_DETAIL // Break down instruction structure into details CS_OPT_MODE = C.CS_OPT_MODE // Change engine's mode at run-time CS_OPT_MEM = C.CS_OPT_MEM // User-defined memory malloc/calloc/free CS_OPT_SKIPDATA = C.CS_OPT_SKIPDATA // Skip data when disassembling. Then engine is in SKIPDATA mode. CS_OPT_SKIPDATA_SETUP = C.CS_OPT_SKIPDATA_SETUP // Setup user-defined function for SKIPDATA option - + CS_OPT_MNEMONIC = C.CS_OPT_MNEMONIC // Customize instruction mnemonic + CS_OPT_UNSIGNED = C.CS_OPT_UNSIGNED // print immediate operands in unsigned form ) const ( @@ -70,7 +93,8 @@ const ( CS_OPT_SYNTAX_DEFAULT = C.CS_OPT_SYNTAX_DEFAULT // Default asm syntax (CS_OPT_SYNTAX). CS_OPT_SYNTAX_INTEL = C.CS_OPT_SYNTAX_INTEL // X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX). CS_OPT_SYNTAX_ATT = C.CS_OPT_SYNTAX_ATT // X86 ATT asm syntax (CS_OPT_SYNTAX). - CS_OPT_SYNTAX_NOREGNAME = C.CS_OPT_SYNTAX_NOREGNAME // PPC asm syntax: Prints register name with only number (CS_OPT_SYNTAX) + CS_OPT_SYNTAX_NOREGNAME = C.CS_OPT_SYNTAX_NOREGNAME // Prints register name with only number (CS_OPT_SYNTAX) + CS_OPT_SYNTAX_MASM = C.CS_OPT_SYNTAX_MASM // X86 Intel Masm syntax (CS_OPT_SYNTAX). ) const ( @@ -90,7 +114,7 @@ const ( CS_ERR_SKIPDATA = C.CS_ERR_SKIPDATA // Access irrelevant data for "data" instruction in SKIPDATA mode CS_ERR_X86_ATT = C.CS_ERR_X86_ATT // X86 AT&T syntax is unsupported (opt-out at compile time) CS_ERR_X86_INTEL = C.CS_ERR_X86_INTEL // X86 Intel syntax is unsupported (opt-out at compile time) - + CS_ERR_X86_MASM = C.CS_ERR_X86_MASM // X86 Intel syntax is unsupported (opt-out at compile time) ) // Common instruction operand types - to be consistent across all architectures. @@ -102,14 +126,24 @@ const ( CS_OP_FP = C.CS_OP_FP // Floating-Point operand. ) +// Common instruction operand access types - to be consistent across all architectures. +// It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE +const ( + CS_AC_INVALID = C.CS_AC_INVALID // Uninitialized/invalid access type. + CS_AC_READ = C.CS_AC_READ // Operand read from memory or register. + CS_AC_WRITE = C.CS_AC_WRITE // Operand write to memory or register. +) + // Common instruction groups - to be consistent across all architectures. const ( - CS_GRP_INVALID = C.CS_GRP_INVALID // uninitialized/invalid group. - CS_GRP_JUMP = C.CS_GRP_JUMP // all jump instructions (conditional+direct+indirect jumps) - CS_GRP_CALL = C.CS_GRP_CALL // all call instructions - CS_GRP_RET = C.CS_GRP_RET // all return instructions - CS_GRP_INT = C.CS_GRP_INT // all interrupt instructions (int+syscall) - CS_GRP_IRET = C.CS_GRP_IRET // all interrupt return instructions + CS_GRP_INVALID = C.CS_GRP_INVALID // uninitialized/invalid group. + CS_GRP_JUMP = C.CS_GRP_JUMP // all jump instructions (conditional+direct+indirect jumps) + CS_GRP_CALL = C.CS_GRP_CALL // all call instructions + CS_GRP_RET = C.CS_GRP_RET // all return instructions + CS_GRP_INT = C.CS_GRP_INT // all interrupt instructions (int+syscall) + CS_GRP_IRET = C.CS_GRP_IRET // all interrupt return instructions + CS_GRP_PRIVILEGE = C.CS_GRP_PRIVILEGE ///< all privileged instructions + CS_GRP_BRANCH_RELATIVE = C.CS_GRP_BRANCH_RELATIVE ///< all relative branching instructions ) const CS_SUPPORT_DIET = C.CS_SUPPORT_DIET diff --git a/engine_iter.go b/engine_iter.go index d5d517a..61b2d64 100644 --- a/engine_iter.go +++ b/engine_iter.go @@ -58,21 +58,21 @@ func (e *Engine) DisasmIter(input []byte, address uint64) <-chan Instruction { switch e.arch { case CS_ARCH_ARM: - out <- decomposeArm(insns)[0] + out <- decomposeArm(e, insns)[0] case CS_ARCH_ARM64: - out <- decomposeArm64(insns)[0] + out <- decomposeArm64(e, insns)[0] case CS_ARCH_MIPS: - out <- decomposeMips(insns)[0] + out <- decomposeMips(e, insns)[0] case CS_ARCH_X86: - out <- decomposeX86(insns)[0] + out <- decomposeX86(e, insns)[0] case CS_ARCH_PPC: - out <- decomposePPC(insns)[0] + out <- decomposePPC(e, insns)[0] case CS_ARCH_SYSZ: - out <- decomposeSysZ(insns)[0] + out <- decomposeSysZ(e, insns)[0] case CS_ARCH_SPARC: - out <- decomposeSparc(insns)[0] + out <- decomposeSparc(e, insns)[0] case CS_ARCH_XCORE: - out <- decomposeXcore(insns)[0] + out <- decomposeXcore(e, insns)[0] default: return } diff --git a/genspec b/genspec index b724d16..93d82da 100755 --- a/genspec +++ b/genspec @@ -11,11 +11,12 @@ end stub = ARGV[0].chomp('/') commands = [ - "#{stub}/test > $GOPATH/src/github.com/bnagy/gapstone/test.SPEC", + "#{stub}/test_basic > $GOPATH/src/github.com/bnagy/gapstone/test.SPEC", "#{stub}/test_detail > $GOPATH/src/github.com/bnagy/gapstone/test_detail.SPEC", "#{stub}/test_arm > $GOPATH/src/github.com/bnagy/gapstone/arm.SPEC", "#{stub}/test_arm64 > $GOPATH/src/github.com/bnagy/gapstone/arm64.SPEC", - "#{stub}/test_x86 > $GOPATH/src/github.com/bnagy/gapstone/x86.SPEC", + # Temporarily disabled. See https://github.com/aquynh/capstone/pull/1365 + #"#{stub}/test_x86 > $GOPATH/src/github.com/bnagy/gapstone/x86.SPEC", "#{stub}/test_mips > $GOPATH/src/github.com/bnagy/gapstone/mips.SPEC", "#{stub}/test_ppc > $GOPATH/src/github.com/bnagy/gapstone/ppc.SPEC", "#{stub}/test_systemz > $GOPATH/src/github.com/bnagy/gapstone/sysZ.SPEC", diff --git a/mips.SPEC b/mips.SPEC index 3bcce53..0d0c747 100644 --- a/mips.SPEC +++ b/mips.SPEC @@ -89,3 +89,29 @@ Disasm: 0x1008: +**************** +Platform: MIPS-64-EL + Mips II (Little-endian) +Code:0x70 0x00 0xb2 0xff +Disasm: +0x1000: sdc3 $18, 0x70($sp) + op_count: 2 + operands[0].type: REG = s2 + operands[1].type: MEM + operands[1].mem.base: REG = sp + operands[1].mem.disp: 0x70 + +0x1004: + +**************** +Platform: MIPS-64-EL (Little-endian) +Code:0x70 0x00 0xb2 0xff +Disasm: +0x1000: sd $s2, 0x70($sp) + op_count: 2 + operands[0].type: REG = s2 + operands[1].type: MEM + operands[1].mem.base: REG = sp + operands[1].mem.disp: 0x70 + +0x1004: + diff --git a/mips_constants.go b/mips_constants.go index 0899709..c5a41c7 100644 --- a/mips_constants.go +++ b/mips_constants.go @@ -8,8 +8,8 @@ try reading the *_test.go files. (c) 2013 COSEINC. All Rights Reserved. THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT! - Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/ - 2016-04-13T12:04:37+09:30 + Command: ./genconst /Users/scottknight/work/capstone/bindings/python/capstone/ + 2019-02-02T13:26:27-05:00 */ @@ -243,6 +243,10 @@ const ( MIPS_INS_ABSQ_S = C.MIPS_INS_ABSQ_S MIPS_INS_ADD = C.MIPS_INS_ADD MIPS_INS_ADDIUPC = C.MIPS_INS_ADDIUPC + MIPS_INS_ADDIUR1SP = C.MIPS_INS_ADDIUR1SP + MIPS_INS_ADDIUR2 = C.MIPS_INS_ADDIUR2 + MIPS_INS_ADDIUS5 = C.MIPS_INS_ADDIUS5 + MIPS_INS_ADDIUSP = C.MIPS_INS_ADDIUSP MIPS_INS_ADDQH = C.MIPS_INS_ADDQH MIPS_INS_ADDQH_R = C.MIPS_INS_ADDQH_R MIPS_INS_ADDQ = C.MIPS_INS_ADDQ @@ -251,6 +255,7 @@ const ( MIPS_INS_ADDS_A = C.MIPS_INS_ADDS_A MIPS_INS_ADDS_S = C.MIPS_INS_ADDS_S MIPS_INS_ADDS_U = C.MIPS_INS_ADDS_U + MIPS_INS_ADDU16 = C.MIPS_INS_ADDU16 MIPS_INS_ADDUH = C.MIPS_INS_ADDUH MIPS_INS_ADDUH_R = C.MIPS_INS_ADDUH_R MIPS_INS_ADDU = C.MIPS_INS_ADDU @@ -264,6 +269,8 @@ const ( MIPS_INS_ALIGN = C.MIPS_INS_ALIGN MIPS_INS_ALUIPC = C.MIPS_INS_ALUIPC MIPS_INS_AND = C.MIPS_INS_AND + MIPS_INS_AND16 = C.MIPS_INS_AND16 + MIPS_INS_ANDI16 = C.MIPS_INS_ANDI16 MIPS_INS_ANDI = C.MIPS_INS_ANDI MIPS_INS_APPEND = C.MIPS_INS_APPEND MIPS_INS_ASUB_S = C.MIPS_INS_ASUB_S @@ -274,10 +281,15 @@ const ( MIPS_INS_AVER_U = C.MIPS_INS_AVER_U MIPS_INS_AVE_S = C.MIPS_INS_AVE_S MIPS_INS_AVE_U = C.MIPS_INS_AVE_U + MIPS_INS_B16 = C.MIPS_INS_B16 MIPS_INS_BADDU = C.MIPS_INS_BADDU MIPS_INS_BAL = C.MIPS_INS_BAL MIPS_INS_BALC = C.MIPS_INS_BALC MIPS_INS_BALIGN = C.MIPS_INS_BALIGN + MIPS_INS_BBIT0 = C.MIPS_INS_BBIT0 + MIPS_INS_BBIT032 = C.MIPS_INS_BBIT032 + MIPS_INS_BBIT1 = C.MIPS_INS_BBIT1 + MIPS_INS_BBIT132 = C.MIPS_INS_BBIT132 MIPS_INS_BC = C.MIPS_INS_BC MIPS_INS_BC0F = C.MIPS_INS_BC0F MIPS_INS_BC0FL = C.MIPS_INS_BC0FL @@ -304,6 +316,7 @@ const ( MIPS_INS_BEQ = C.MIPS_INS_BEQ MIPS_INS_BEQC = C.MIPS_INS_BEQC MIPS_INS_BEQL = C.MIPS_INS_BEQL + MIPS_INS_BEQZ16 = C.MIPS_INS_BEQZ16 MIPS_INS_BEQZALC = C.MIPS_INS_BEQZALC MIPS_INS_BEQZC = C.MIPS_INS_BEQZC MIPS_INS_BGEC = C.MIPS_INS_BGEC @@ -347,6 +360,7 @@ const ( MIPS_INS_BNEGI = C.MIPS_INS_BNEGI MIPS_INS_BNEG = C.MIPS_INS_BNEG MIPS_INS_BNEL = C.MIPS_INS_BNEL + MIPS_INS_BNEZ16 = C.MIPS_INS_BNEZ16 MIPS_INS_BNEZALC = C.MIPS_INS_BNEZALC MIPS_INS_BNEZC = C.MIPS_INS_BNEZC MIPS_INS_BNVC = C.MIPS_INS_BNVC @@ -354,6 +368,7 @@ const ( MIPS_INS_BOVC = C.MIPS_INS_BOVC MIPS_INS_BPOSGE32 = C.MIPS_INS_BPOSGE32 MIPS_INS_BREAK = C.MIPS_INS_BREAK + MIPS_INS_BREAK16 = C.MIPS_INS_BREAK16 MIPS_INS_BSELI = C.MIPS_INS_BSELI MIPS_INS_BSEL = C.MIPS_INS_BSEL MIPS_INS_BSETI = C.MIPS_INS_BSETI @@ -563,16 +578,19 @@ const ( MIPS_INS_J = C.MIPS_INS_J MIPS_INS_JAL = C.MIPS_INS_JAL MIPS_INS_JALR = C.MIPS_INS_JALR + MIPS_INS_JALRS16 = C.MIPS_INS_JALRS16 MIPS_INS_JALRS = C.MIPS_INS_JALRS MIPS_INS_JALS = C.MIPS_INS_JALS MIPS_INS_JALX = C.MIPS_INS_JALX MIPS_INS_JIALC = C.MIPS_INS_JIALC MIPS_INS_JIC = C.MIPS_INS_JIC MIPS_INS_JR = C.MIPS_INS_JR + MIPS_INS_JR16 = C.MIPS_INS_JR16 MIPS_INS_JRADDIUSP = C.MIPS_INS_JRADDIUSP MIPS_INS_JRC = C.MIPS_INS_JRC MIPS_INS_JALRC = C.MIPS_INS_JALRC MIPS_INS_LB = C.MIPS_INS_LB + MIPS_INS_LBU16 = C.MIPS_INS_LBU16 MIPS_INS_LBUX = C.MIPS_INS_LBUX MIPS_INS_LBU = C.MIPS_INS_LBU MIPS_INS_LD = C.MIPS_INS_LD @@ -585,24 +603,31 @@ const ( MIPS_INS_LDR = C.MIPS_INS_LDR MIPS_INS_LDXC1 = C.MIPS_INS_LDXC1 MIPS_INS_LH = C.MIPS_INS_LH + MIPS_INS_LHU16 = C.MIPS_INS_LHU16 MIPS_INS_LHX = C.MIPS_INS_LHX MIPS_INS_LHU = C.MIPS_INS_LHU + MIPS_INS_LI16 = C.MIPS_INS_LI16 MIPS_INS_LL = C.MIPS_INS_LL MIPS_INS_LLD = C.MIPS_INS_LLD MIPS_INS_LSA = C.MIPS_INS_LSA MIPS_INS_LUXC1 = C.MIPS_INS_LUXC1 MIPS_INS_LUI = C.MIPS_INS_LUI MIPS_INS_LW = C.MIPS_INS_LW + MIPS_INS_LW16 = C.MIPS_INS_LW16 MIPS_INS_LWC1 = C.MIPS_INS_LWC1 MIPS_INS_LWC2 = C.MIPS_INS_LWC2 MIPS_INS_LWC3 = C.MIPS_INS_LWC3 MIPS_INS_LWL = C.MIPS_INS_LWL + MIPS_INS_LWM16 = C.MIPS_INS_LWM16 + MIPS_INS_LWM32 = C.MIPS_INS_LWM32 MIPS_INS_LWPC = C.MIPS_INS_LWPC + MIPS_INS_LWP = C.MIPS_INS_LWP MIPS_INS_LWR = C.MIPS_INS_LWR MIPS_INS_LWUPC = C.MIPS_INS_LWUPC MIPS_INS_LWU = C.MIPS_INS_LWU MIPS_INS_LWX = C.MIPS_INS_LWX MIPS_INS_LWXC1 = C.MIPS_INS_LWXC1 + MIPS_INS_LWXS = C.MIPS_INS_LWXS MIPS_INS_LI = C.MIPS_INS_LI MIPS_INS_MADD = C.MIPS_INS_MADD MIPS_INS_MADDF = C.MIPS_INS_MADDF @@ -638,6 +663,7 @@ const ( MIPS_INS_MOD_S = C.MIPS_INS_MOD_S MIPS_INS_MOD_U = C.MIPS_INS_MOD_U MIPS_INS_MOVE = C.MIPS_INS_MOVE + MIPS_INS_MOVEP = C.MIPS_INS_MOVEP MIPS_INS_MOVF = C.MIPS_INS_MOVF MIPS_INS_MOVN = C.MIPS_INS_MOVN MIPS_INS_MOVT = C.MIPS_INS_MOVT @@ -682,8 +708,10 @@ const ( MIPS_INS_NMSUB = C.MIPS_INS_NMSUB MIPS_INS_NOR = C.MIPS_INS_NOR MIPS_INS_NORI = C.MIPS_INS_NORI + MIPS_INS_NOT16 = C.MIPS_INS_NOT16 MIPS_INS_NOT = C.MIPS_INS_NOT MIPS_INS_OR = C.MIPS_INS_OR + MIPS_INS_OR16 = C.MIPS_INS_OR16 MIPS_INS_ORI = C.MIPS_INS_ORI MIPS_INS_PACKRL = C.MIPS_INS_PACKRL MIPS_INS_PAUSE = C.MIPS_INS_PAUSE @@ -715,10 +743,12 @@ const ( MIPS_INS_SAT_S = C.MIPS_INS_SAT_S MIPS_INS_SAT_U = C.MIPS_INS_SAT_U MIPS_INS_SB = C.MIPS_INS_SB + MIPS_INS_SB16 = C.MIPS_INS_SB16 MIPS_INS_SC = C.MIPS_INS_SC MIPS_INS_SCD = C.MIPS_INS_SCD MIPS_INS_SD = C.MIPS_INS_SD MIPS_INS_SDBBP = C.MIPS_INS_SDBBP + MIPS_INS_SDBBP16 = C.MIPS_INS_SDBBP16 MIPS_INS_SDC1 = C.MIPS_INS_SDC1 MIPS_INS_SDC2 = C.MIPS_INS_SDC2 MIPS_INS_SDC3 = C.MIPS_INS_SDC3 @@ -733,6 +763,7 @@ const ( MIPS_INS_SEQ = C.MIPS_INS_SEQ MIPS_INS_SEQI = C.MIPS_INS_SEQI MIPS_INS_SH = C.MIPS_INS_SH + MIPS_INS_SH16 = C.MIPS_INS_SH16 MIPS_INS_SHF = C.MIPS_INS_SHF MIPS_INS_SHILO = C.MIPS_INS_SHILO MIPS_INS_SHILOV = C.MIPS_INS_SHILOV @@ -749,6 +780,7 @@ const ( MIPS_INS_SLDI = C.MIPS_INS_SLDI MIPS_INS_SLD = C.MIPS_INS_SLD MIPS_INS_SLL = C.MIPS_INS_SLL + MIPS_INS_SLL16 = C.MIPS_INS_SLL16 MIPS_INS_SLLI = C.MIPS_INS_SLLI MIPS_INS_SLLV = C.MIPS_INS_SLLV MIPS_INS_SLT = C.MIPS_INS_SLT @@ -765,6 +797,7 @@ const ( MIPS_INS_SRAR = C.MIPS_INS_SRAR MIPS_INS_SRAV = C.MIPS_INS_SRAV MIPS_INS_SRL = C.MIPS_INS_SRL + MIPS_INS_SRL16 = C.MIPS_INS_SRL16 MIPS_INS_SRLI = C.MIPS_INS_SRLI MIPS_INS_SRLRI = C.MIPS_INS_SRLRI MIPS_INS_SRLR = C.MIPS_INS_SRLR @@ -779,6 +812,7 @@ const ( MIPS_INS_SUBSUU_S = C.MIPS_INS_SUBSUU_S MIPS_INS_SUBS_S = C.MIPS_INS_SUBS_S MIPS_INS_SUBS_U = C.MIPS_INS_SUBS_U + MIPS_INS_SUBU16 = C.MIPS_INS_SUBU16 MIPS_INS_SUBUH = C.MIPS_INS_SUBUH MIPS_INS_SUBUH_R = C.MIPS_INS_SUBUH_R MIPS_INS_SUBU = C.MIPS_INS_SUBU @@ -787,13 +821,18 @@ const ( MIPS_INS_SUBV = C.MIPS_INS_SUBV MIPS_INS_SUXC1 = C.MIPS_INS_SUXC1 MIPS_INS_SW = C.MIPS_INS_SW + MIPS_INS_SW16 = C.MIPS_INS_SW16 MIPS_INS_SWC1 = C.MIPS_INS_SWC1 MIPS_INS_SWC2 = C.MIPS_INS_SWC2 MIPS_INS_SWC3 = C.MIPS_INS_SWC3 MIPS_INS_SWL = C.MIPS_INS_SWL + MIPS_INS_SWM16 = C.MIPS_INS_SWM16 + MIPS_INS_SWM32 = C.MIPS_INS_SWM32 + MIPS_INS_SWP = C.MIPS_INS_SWP MIPS_INS_SWR = C.MIPS_INS_SWR MIPS_INS_SWXC1 = C.MIPS_INS_SWXC1 MIPS_INS_SYNC = C.MIPS_INS_SYNC + MIPS_INS_SYNCI = C.MIPS_INS_SYNCI MIPS_INS_SYSCALL = C.MIPS_INS_SYSCALL MIPS_INS_TEQ = C.MIPS_INS_TEQ MIPS_INS_TEQI = C.MIPS_INS_TEQI @@ -820,6 +859,7 @@ const ( MIPS_INS_WRDSP = C.MIPS_INS_WRDSP MIPS_INS_WSBH = C.MIPS_INS_WSBH MIPS_INS_XOR = C.MIPS_INS_XOR + MIPS_INS_XOR16 = C.MIPS_INS_XOR16 MIPS_INS_XORI = C.MIPS_INS_XORI ) @@ -843,7 +883,13 @@ const ( // Generic groups const ( - MIPS_GRP_JUMP = C.MIPS_GRP_JUMP + MIPS_GRP_JUMP = C.MIPS_GRP_JUMP + MIPS_GRP_CALL = C.MIPS_GRP_CALL + MIPS_GRP_RET = C.MIPS_GRP_RET + MIPS_GRP_INT = C.MIPS_GRP_INT + MIPS_GRP_IRET = C.MIPS_GRP_IRET + MIPS_GRP_PRIVILEGE = C.MIPS_GRP_PRIVILEGE + MIPS_GRP_BRANCH_RELATIVE = C.MIPS_GRP_BRANCH_RELATIVE ) // Architecture-specific groups diff --git a/mips_decomposer.go b/mips_decomposer.go index fc74e13..fd3c1ef 100644 --- a/mips_decomposer.go +++ b/mips_decomposer.go @@ -98,11 +98,11 @@ func fillMipsHeader(raw C.cs_insn, insn *Instruction) { insn.Mips = &mips } -func decomposeMips(raws []C.cs_insn) []Instruction { +func decomposeMips(e *Engine, raws []C.cs_insn) []Instruction { decomposed := []Instruction{} for _, raw := range raws { decomp := new(Instruction) - fillGenericHeader(raw, decomp) + fillGenericHeader(e, raw, decomp) fillMipsHeader(raw, decomp) decomposed = append(decomposed, *decomp) } diff --git a/ppc.SPEC b/ppc.SPEC index 59f1c7d..dddc981 100644 --- a/ppc.SPEC +++ b/ppc.SPEC @@ -7,22 +7,22 @@ Disasm: operands[0].type: IMM = 0xc04 Branch hint: 1 -0x1004: bdztla 4*cr5+eq, 0xffffff14 +0x1004: bdztla 4*cr5+eq, 0xffffffffffffff14 op_count: 2 operands[0].type: CRX operands[0].crx.scale: 4 operands[0].crx.reg: cr5 operands[0].crx.cond: eq - operands[1].type: IMM = 0xffffff14 + operands[1].type: IMM = 0xffffffffffffff14 Branch hint: 1 -0x1008: lwz r1, (0) +0x1008: lwz r1, 0(0) op_count: 2 operands[0].type: REG = r1 operands[1].type: MEM operands[1].mem.base: REG = r0 -0x100c: lwz r1, (r31) +0x100c: lwz r1, 0(r31) op_count: 2 operands[0].type: REG = r1 operands[1].type: MEM @@ -82,3 +82,26 @@ Disasm: 0x1034: +**************** +Platform: PPC-64 + QPX +Code:0x10 0x60 0x2a 0x10 0x10 0x64 0x28 0x88 0x7c 0x4a 0x5d 0x0f +Disasm: +0x1000: qvfabs q3, q5 + op_count: 2 + operands[0].type: REG = q3 + operands[1].type: REG = q5 + +0x1004: qvfand q3, q4, q5 + op_count: 3 + operands[0].type: REG = q3 + operands[1].type: REG = q4 + operands[2].type: REG = q5 + +0x1008: qvstfsxa q2, r10, r11 + op_count: 3 + operands[0].type: REG = q2 + operands[1].type: REG = r10 + operands[2].type: REG = r11 + +0x100c: + diff --git a/ppc_constants.go b/ppc_constants.go index e10c300..7d633c8 100644 --- a/ppc_constants.go +++ b/ppc_constants.go @@ -8,8 +8,8 @@ try reading the *_test.go files. (c) 2013 COSEINC. All Rights Reserved. THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT! - Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/ - 2016-04-13T12:04:37+09:30 + Command: ./genconst /Users/scottknight/work/capstone/bindings/python/capstone/ + 2019-02-02T13:26:27-05:00 */ @@ -58,7 +58,6 @@ const ( const ( PPC_REG_INVALID = C.PPC_REG_INVALID PPC_REG_CARRY = C.PPC_REG_CARRY - PPC_REG_CC = C.PPC_REG_CC PPC_REG_CR0 = C.PPC_REG_CR0 PPC_REG_CR1 = C.PPC_REG_CR1 PPC_REG_CR2 = C.PPC_REG_CR2 @@ -230,10 +229,43 @@ const ( PPC_REG_VS61 = C.PPC_REG_VS61 PPC_REG_VS62 = C.PPC_REG_VS62 PPC_REG_VS63 = C.PPC_REG_VS63 + PPC_REG_Q0 = C.PPC_REG_Q0 + PPC_REG_Q1 = C.PPC_REG_Q1 + PPC_REG_Q2 = C.PPC_REG_Q2 + PPC_REG_Q3 = C.PPC_REG_Q3 + PPC_REG_Q4 = C.PPC_REG_Q4 + PPC_REG_Q5 = C.PPC_REG_Q5 + PPC_REG_Q6 = C.PPC_REG_Q6 + PPC_REG_Q7 = C.PPC_REG_Q7 + PPC_REG_Q8 = C.PPC_REG_Q8 + PPC_REG_Q9 = C.PPC_REG_Q9 + PPC_REG_Q10 = C.PPC_REG_Q10 + PPC_REG_Q11 = C.PPC_REG_Q11 + PPC_REG_Q12 = C.PPC_REG_Q12 + PPC_REG_Q13 = C.PPC_REG_Q13 + PPC_REG_Q14 = C.PPC_REG_Q14 + PPC_REG_Q15 = C.PPC_REG_Q15 + PPC_REG_Q16 = C.PPC_REG_Q16 + PPC_REG_Q17 = C.PPC_REG_Q17 + PPC_REG_Q18 = C.PPC_REG_Q18 + PPC_REG_Q19 = C.PPC_REG_Q19 + PPC_REG_Q20 = C.PPC_REG_Q20 + PPC_REG_Q21 = C.PPC_REG_Q21 + PPC_REG_Q22 = C.PPC_REG_Q22 + PPC_REG_Q23 = C.PPC_REG_Q23 + PPC_REG_Q24 = C.PPC_REG_Q24 + PPC_REG_Q25 = C.PPC_REG_Q25 + PPC_REG_Q26 = C.PPC_REG_Q26 + PPC_REG_Q27 = C.PPC_REG_Q27 + PPC_REG_Q28 = C.PPC_REG_Q28 + PPC_REG_Q29 = C.PPC_REG_Q29 + PPC_REG_Q30 = C.PPC_REG_Q30 + PPC_REG_Q31 = C.PPC_REG_Q31 PPC_REG_RM = C.PPC_REG_RM PPC_REG_CTR8 = C.PPC_REG_CTR8 PPC_REG_LR8 = C.PPC_REG_LR8 PPC_REG_CR1EQ = C.PPC_REG_CR1EQ + PPC_REG_X2 = C.PPC_REG_X2 PPC_REG_ENDING = C.PPC_REG_ENDING ) @@ -252,6 +284,7 @@ const ( PPC_INS_ANDC = C.PPC_INS_ANDC PPC_INS_ANDIS = C.PPC_INS_ANDIS PPC_INS_ANDI = C.PPC_INS_ANDI + PPC_INS_ATTN = C.PPC_INS_ATTN PPC_INS_B = C.PPC_INS_B PPC_INS_BA = C.PPC_INS_BA PPC_INS_BC = C.PPC_INS_BC @@ -262,6 +295,7 @@ const ( PPC_INS_BCLRL = C.PPC_INS_BCLRL PPC_INS_BCTR = C.PPC_INS_BCTR PPC_INS_BCTRL = C.PPC_INS_BCTRL + PPC_INS_BCT = C.PPC_INS_BCT PPC_INS_BDNZ = C.PPC_INS_BDNZ PPC_INS_BDNZA = C.PPC_INS_BDNZA PPC_INS_BDNZL = C.PPC_INS_BDNZL @@ -279,6 +313,7 @@ const ( PPC_INS_BLR = C.PPC_INS_BLR PPC_INS_BLRL = C.PPC_INS_BLRL PPC_INS_BRINC = C.PPC_INS_BRINC + PPC_INS_CMPB = C.PPC_INS_CMPB PPC_INS_CMPD = C.PPC_INS_CMPD PPC_INS_CMPDI = C.PPC_INS_CMPDI PPC_INS_CMPLD = C.PPC_INS_CMPLD @@ -316,7 +351,6 @@ const ( PPC_INS_DSTST = C.PPC_INS_DSTST PPC_INS_DSTSTT = C.PPC_INS_DSTSTT PPC_INS_DSTT = C.PPC_INS_DSTT - PPC_INS_EIEIO = C.PPC_INS_EIEIO PPC_INS_EQV = C.PPC_INS_EQV PPC_INS_EVABS = C.PPC_INS_EVABS PPC_INS_EVADDIW = C.PPC_INS_EVADDIW @@ -492,6 +526,7 @@ const ( PPC_INS_EXTSB = C.PPC_INS_EXTSB PPC_INS_EXTSH = C.PPC_INS_EXTSH PPC_INS_EXTSW = C.PPC_INS_EXTSW + PPC_INS_EIEIO = C.PPC_INS_EIEIO PPC_INS_FABS = C.PPC_INS_FABS PPC_INS_FADD = C.PPC_INS_FADD PPC_INS_FADDS = C.PPC_INS_FADDS @@ -537,17 +572,20 @@ const ( PPC_INS_FSUB = C.PPC_INS_FSUB PPC_INS_FSUBS = C.PPC_INS_FSUBS PPC_INS_ICBI = C.PPC_INS_ICBI + PPC_INS_ICBT = C.PPC_INS_ICBT PPC_INS_ICCCI = C.PPC_INS_ICCCI PPC_INS_ISEL = C.PPC_INS_ISEL PPC_INS_ISYNC = C.PPC_INS_ISYNC PPC_INS_LA = C.PPC_INS_LA PPC_INS_LBZ = C.PPC_INS_LBZ + PPC_INS_LBZCIX = C.PPC_INS_LBZCIX PPC_INS_LBZU = C.PPC_INS_LBZU PPC_INS_LBZUX = C.PPC_INS_LBZUX PPC_INS_LBZX = C.PPC_INS_LBZX PPC_INS_LD = C.PPC_INS_LD PPC_INS_LDARX = C.PPC_INS_LDARX PPC_INS_LDBRX = C.PPC_INS_LDBRX + PPC_INS_LDCIX = C.PPC_INS_LDCIX PPC_INS_LDU = C.PPC_INS_LDU PPC_INS_LDUX = C.PPC_INS_LDUX PPC_INS_LDX = C.PPC_INS_LDX @@ -567,6 +605,7 @@ const ( PPC_INS_LHAX = C.PPC_INS_LHAX PPC_INS_LHBRX = C.PPC_INS_LHBRX PPC_INS_LHZ = C.PPC_INS_LHZ + PPC_INS_LHZCIX = C.PPC_INS_LHZCIX PPC_INS_LHZU = C.PPC_INS_LHZU PPC_INS_LHZUX = C.PPC_INS_LHZUX PPC_INS_LHZX = C.PPC_INS_LHZX @@ -587,6 +626,7 @@ const ( PPC_INS_LWAX = C.PPC_INS_LWAX PPC_INS_LWBRX = C.PPC_INS_LWBRX PPC_INS_LWZ = C.PPC_INS_LWZ + PPC_INS_LWZCIX = C.PPC_INS_LWZCIX PPC_INS_LWZU = C.PPC_INS_LWZU PPC_INS_LWZUX = C.PPC_INS_LWZUX PPC_INS_LWZX = C.PPC_INS_LWZX @@ -596,6 +636,7 @@ const ( PPC_INS_LXVW4X = C.PPC_INS_LXVW4X PPC_INS_MBAR = C.PPC_INS_MBAR PPC_INS_MCRF = C.PPC_INS_MCRF + PPC_INS_MCRFS = C.PPC_INS_MCRFS PPC_INS_MFCR = C.PPC_INS_MFCR PPC_INS_MFCTR = C.PPC_INS_MFCTR PPC_INS_MFDCR = C.PPC_INS_MFDCR @@ -615,6 +656,7 @@ const ( PPC_INS_MTFSB0 = C.PPC_INS_MTFSB0 PPC_INS_MTFSB1 = C.PPC_INS_MTFSB1 PPC_INS_MTFSF = C.PPC_INS_MTFSF + PPC_INS_MTFSFI = C.PPC_INS_MTFSFI PPC_INS_MTLR = C.PPC_INS_MTLR PPC_INS_MTMSR = C.PPC_INS_MTMSR PPC_INS_MTMSRD = C.PPC_INS_MTMSRD @@ -640,6 +682,124 @@ const ( PPC_INS_ORIS = C.PPC_INS_ORIS PPC_INS_POPCNTD = C.PPC_INS_POPCNTD PPC_INS_POPCNTW = C.PPC_INS_POPCNTW + PPC_INS_QVALIGNI = C.PPC_INS_QVALIGNI + PPC_INS_QVESPLATI = C.PPC_INS_QVESPLATI + PPC_INS_QVFABS = C.PPC_INS_QVFABS + PPC_INS_QVFADD = C.PPC_INS_QVFADD + PPC_INS_QVFADDS = C.PPC_INS_QVFADDS + PPC_INS_QVFCFID = C.PPC_INS_QVFCFID + PPC_INS_QVFCFIDS = C.PPC_INS_QVFCFIDS + PPC_INS_QVFCFIDU = C.PPC_INS_QVFCFIDU + PPC_INS_QVFCFIDUS = C.PPC_INS_QVFCFIDUS + PPC_INS_QVFCMPEQ = C.PPC_INS_QVFCMPEQ + PPC_INS_QVFCMPGT = C.PPC_INS_QVFCMPGT + PPC_INS_QVFCMPLT = C.PPC_INS_QVFCMPLT + PPC_INS_QVFCPSGN = C.PPC_INS_QVFCPSGN + PPC_INS_QVFCTID = C.PPC_INS_QVFCTID + PPC_INS_QVFCTIDU = C.PPC_INS_QVFCTIDU + PPC_INS_QVFCTIDUZ = C.PPC_INS_QVFCTIDUZ + PPC_INS_QVFCTIDZ = C.PPC_INS_QVFCTIDZ + PPC_INS_QVFCTIW = C.PPC_INS_QVFCTIW + PPC_INS_QVFCTIWU = C.PPC_INS_QVFCTIWU + PPC_INS_QVFCTIWUZ = C.PPC_INS_QVFCTIWUZ + PPC_INS_QVFCTIWZ = C.PPC_INS_QVFCTIWZ + PPC_INS_QVFLOGICAL = C.PPC_INS_QVFLOGICAL + PPC_INS_QVFMADD = C.PPC_INS_QVFMADD + PPC_INS_QVFMADDS = C.PPC_INS_QVFMADDS + PPC_INS_QVFMR = C.PPC_INS_QVFMR + PPC_INS_QVFMSUB = C.PPC_INS_QVFMSUB + PPC_INS_QVFMSUBS = C.PPC_INS_QVFMSUBS + PPC_INS_QVFMUL = C.PPC_INS_QVFMUL + PPC_INS_QVFMULS = C.PPC_INS_QVFMULS + PPC_INS_QVFNABS = C.PPC_INS_QVFNABS + PPC_INS_QVFNEG = C.PPC_INS_QVFNEG + PPC_INS_QVFNMADD = C.PPC_INS_QVFNMADD + PPC_INS_QVFNMADDS = C.PPC_INS_QVFNMADDS + PPC_INS_QVFNMSUB = C.PPC_INS_QVFNMSUB + PPC_INS_QVFNMSUBS = C.PPC_INS_QVFNMSUBS + PPC_INS_QVFPERM = C.PPC_INS_QVFPERM + PPC_INS_QVFRE = C.PPC_INS_QVFRE + PPC_INS_QVFRES = C.PPC_INS_QVFRES + PPC_INS_QVFRIM = C.PPC_INS_QVFRIM + PPC_INS_QVFRIN = C.PPC_INS_QVFRIN + PPC_INS_QVFRIP = C.PPC_INS_QVFRIP + PPC_INS_QVFRIZ = C.PPC_INS_QVFRIZ + PPC_INS_QVFRSP = C.PPC_INS_QVFRSP + PPC_INS_QVFRSQRTE = C.PPC_INS_QVFRSQRTE + PPC_INS_QVFRSQRTES = C.PPC_INS_QVFRSQRTES + PPC_INS_QVFSEL = C.PPC_INS_QVFSEL + PPC_INS_QVFSUB = C.PPC_INS_QVFSUB + PPC_INS_QVFSUBS = C.PPC_INS_QVFSUBS + PPC_INS_QVFTSTNAN = C.PPC_INS_QVFTSTNAN + PPC_INS_QVFXMADD = C.PPC_INS_QVFXMADD + PPC_INS_QVFXMADDS = C.PPC_INS_QVFXMADDS + PPC_INS_QVFXMUL = C.PPC_INS_QVFXMUL + PPC_INS_QVFXMULS = C.PPC_INS_QVFXMULS + PPC_INS_QVFXXCPNMADD = C.PPC_INS_QVFXXCPNMADD + PPC_INS_QVFXXCPNMADDS = C.PPC_INS_QVFXXCPNMADDS + PPC_INS_QVFXXMADD = C.PPC_INS_QVFXXMADD + PPC_INS_QVFXXMADDS = C.PPC_INS_QVFXXMADDS + PPC_INS_QVFXXNPMADD = C.PPC_INS_QVFXXNPMADD + PPC_INS_QVFXXNPMADDS = C.PPC_INS_QVFXXNPMADDS + PPC_INS_QVGPCI = C.PPC_INS_QVGPCI + PPC_INS_QVLFCDUX = C.PPC_INS_QVLFCDUX + PPC_INS_QVLFCDUXA = C.PPC_INS_QVLFCDUXA + PPC_INS_QVLFCDX = C.PPC_INS_QVLFCDX + PPC_INS_QVLFCDXA = C.PPC_INS_QVLFCDXA + PPC_INS_QVLFCSUX = C.PPC_INS_QVLFCSUX + PPC_INS_QVLFCSUXA = C.PPC_INS_QVLFCSUXA + PPC_INS_QVLFCSX = C.PPC_INS_QVLFCSX + PPC_INS_QVLFCSXA = C.PPC_INS_QVLFCSXA + PPC_INS_QVLFDUX = C.PPC_INS_QVLFDUX + PPC_INS_QVLFDUXA = C.PPC_INS_QVLFDUXA + PPC_INS_QVLFDX = C.PPC_INS_QVLFDX + PPC_INS_QVLFDXA = C.PPC_INS_QVLFDXA + PPC_INS_QVLFIWAX = C.PPC_INS_QVLFIWAX + PPC_INS_QVLFIWAXA = C.PPC_INS_QVLFIWAXA + PPC_INS_QVLFIWZX = C.PPC_INS_QVLFIWZX + PPC_INS_QVLFIWZXA = C.PPC_INS_QVLFIWZXA + PPC_INS_QVLFSUX = C.PPC_INS_QVLFSUX + PPC_INS_QVLFSUXA = C.PPC_INS_QVLFSUXA + PPC_INS_QVLFSX = C.PPC_INS_QVLFSX + PPC_INS_QVLFSXA = C.PPC_INS_QVLFSXA + PPC_INS_QVLPCLDX = C.PPC_INS_QVLPCLDX + PPC_INS_QVLPCLSX = C.PPC_INS_QVLPCLSX + PPC_INS_QVLPCRDX = C.PPC_INS_QVLPCRDX + PPC_INS_QVLPCRSX = C.PPC_INS_QVLPCRSX + PPC_INS_QVSTFCDUX = C.PPC_INS_QVSTFCDUX + PPC_INS_QVSTFCDUXA = C.PPC_INS_QVSTFCDUXA + PPC_INS_QVSTFCDUXI = C.PPC_INS_QVSTFCDUXI + PPC_INS_QVSTFCDUXIA = C.PPC_INS_QVSTFCDUXIA + PPC_INS_QVSTFCDX = C.PPC_INS_QVSTFCDX + PPC_INS_QVSTFCDXA = C.PPC_INS_QVSTFCDXA + PPC_INS_QVSTFCDXI = C.PPC_INS_QVSTFCDXI + PPC_INS_QVSTFCDXIA = C.PPC_INS_QVSTFCDXIA + PPC_INS_QVSTFCSUX = C.PPC_INS_QVSTFCSUX + PPC_INS_QVSTFCSUXA = C.PPC_INS_QVSTFCSUXA + PPC_INS_QVSTFCSUXI = C.PPC_INS_QVSTFCSUXI + PPC_INS_QVSTFCSUXIA = C.PPC_INS_QVSTFCSUXIA + PPC_INS_QVSTFCSX = C.PPC_INS_QVSTFCSX + PPC_INS_QVSTFCSXA = C.PPC_INS_QVSTFCSXA + PPC_INS_QVSTFCSXI = C.PPC_INS_QVSTFCSXI + PPC_INS_QVSTFCSXIA = C.PPC_INS_QVSTFCSXIA + PPC_INS_QVSTFDUX = C.PPC_INS_QVSTFDUX + PPC_INS_QVSTFDUXA = C.PPC_INS_QVSTFDUXA + PPC_INS_QVSTFDUXI = C.PPC_INS_QVSTFDUXI + PPC_INS_QVSTFDUXIA = C.PPC_INS_QVSTFDUXIA + PPC_INS_QVSTFDX = C.PPC_INS_QVSTFDX + PPC_INS_QVSTFDXA = C.PPC_INS_QVSTFDXA + PPC_INS_QVSTFDXI = C.PPC_INS_QVSTFDXI + PPC_INS_QVSTFDXIA = C.PPC_INS_QVSTFDXIA + PPC_INS_QVSTFIWX = C.PPC_INS_QVSTFIWX + PPC_INS_QVSTFIWXA = C.PPC_INS_QVSTFIWXA + PPC_INS_QVSTFSUX = C.PPC_INS_QVSTFSUX + PPC_INS_QVSTFSUXA = C.PPC_INS_QVSTFSUXA + PPC_INS_QVSTFSUXI = C.PPC_INS_QVSTFSUXI + PPC_INS_QVSTFSUXIA = C.PPC_INS_QVSTFSUXIA + PPC_INS_QVSTFSX = C.PPC_INS_QVSTFSX + PPC_INS_QVSTFSXA = C.PPC_INS_QVSTFSXA + PPC_INS_QVSTFSXI = C.PPC_INS_QVSTFSXI + PPC_INS_QVSTFSXIA = C.PPC_INS_QVSTFSXIA PPC_INS_RFCI = C.PPC_INS_RFCI PPC_INS_RFDI = C.PPC_INS_RFDI PPC_INS_RFI = C.PPC_INS_RFI @@ -668,11 +828,13 @@ const ( PPC_INS_SRD = C.PPC_INS_SRD PPC_INS_SRW = C.PPC_INS_SRW PPC_INS_STB = C.PPC_INS_STB + PPC_INS_STBCIX = C.PPC_INS_STBCIX PPC_INS_STBU = C.PPC_INS_STBU PPC_INS_STBUX = C.PPC_INS_STBUX PPC_INS_STBX = C.PPC_INS_STBX PPC_INS_STD = C.PPC_INS_STD PPC_INS_STDBRX = C.PPC_INS_STDBRX + PPC_INS_STDCIX = C.PPC_INS_STDCIX PPC_INS_STDCX = C.PPC_INS_STDCX PPC_INS_STDU = C.PPC_INS_STDU PPC_INS_STDUX = C.PPC_INS_STDUX @@ -688,6 +850,7 @@ const ( PPC_INS_STFSX = C.PPC_INS_STFSX PPC_INS_STH = C.PPC_INS_STH PPC_INS_STHBRX = C.PPC_INS_STHBRX + PPC_INS_STHCIX = C.PPC_INS_STHCIX PPC_INS_STHU = C.PPC_INS_STHU PPC_INS_STHUX = C.PPC_INS_STHUX PPC_INS_STHX = C.PPC_INS_STHX @@ -700,6 +863,7 @@ const ( PPC_INS_STVXL = C.PPC_INS_STVXL PPC_INS_STW = C.PPC_INS_STW PPC_INS_STWBRX = C.PPC_INS_STWBRX + PPC_INS_STWCIX = C.PPC_INS_STWCIX PPC_INS_STWCX = C.PPC_INS_STWCX PPC_INS_STWU = C.PPC_INS_STWU PPC_INS_STWUX = C.PPC_INS_STWUX @@ -736,6 +900,7 @@ const ( PPC_INS_VADDSWS = C.PPC_INS_VADDSWS PPC_INS_VADDUBM = C.PPC_INS_VADDUBM PPC_INS_VADDUBS = C.PPC_INS_VADDUBS + PPC_INS_VADDUDM = C.PPC_INS_VADDUDM PPC_INS_VADDUHM = C.PPC_INS_VADDUHM PPC_INS_VADDUHS = C.PPC_INS_VADDUHS PPC_INS_VADDUWM = C.PPC_INS_VADDUWM @@ -750,35 +915,47 @@ const ( PPC_INS_VAVGUW = C.PPC_INS_VAVGUW PPC_INS_VCFSX = C.PPC_INS_VCFSX PPC_INS_VCFUX = C.PPC_INS_VCFUX + PPC_INS_VCLZB = C.PPC_INS_VCLZB + PPC_INS_VCLZD = C.PPC_INS_VCLZD + PPC_INS_VCLZH = C.PPC_INS_VCLZH + PPC_INS_VCLZW = C.PPC_INS_VCLZW PPC_INS_VCMPBFP = C.PPC_INS_VCMPBFP PPC_INS_VCMPEQFP = C.PPC_INS_VCMPEQFP PPC_INS_VCMPEQUB = C.PPC_INS_VCMPEQUB + PPC_INS_VCMPEQUD = C.PPC_INS_VCMPEQUD PPC_INS_VCMPEQUH = C.PPC_INS_VCMPEQUH PPC_INS_VCMPEQUW = C.PPC_INS_VCMPEQUW PPC_INS_VCMPGEFP = C.PPC_INS_VCMPGEFP PPC_INS_VCMPGTFP = C.PPC_INS_VCMPGTFP PPC_INS_VCMPGTSB = C.PPC_INS_VCMPGTSB + PPC_INS_VCMPGTSD = C.PPC_INS_VCMPGTSD PPC_INS_VCMPGTSH = C.PPC_INS_VCMPGTSH PPC_INS_VCMPGTSW = C.PPC_INS_VCMPGTSW PPC_INS_VCMPGTUB = C.PPC_INS_VCMPGTUB + PPC_INS_VCMPGTUD = C.PPC_INS_VCMPGTUD PPC_INS_VCMPGTUH = C.PPC_INS_VCMPGTUH PPC_INS_VCMPGTUW = C.PPC_INS_VCMPGTUW PPC_INS_VCTSXS = C.PPC_INS_VCTSXS PPC_INS_VCTUXS = C.PPC_INS_VCTUXS + PPC_INS_VEQV = C.PPC_INS_VEQV PPC_INS_VEXPTEFP = C.PPC_INS_VEXPTEFP PPC_INS_VLOGEFP = C.PPC_INS_VLOGEFP PPC_INS_VMADDFP = C.PPC_INS_VMADDFP PPC_INS_VMAXFP = C.PPC_INS_VMAXFP PPC_INS_VMAXSB = C.PPC_INS_VMAXSB + PPC_INS_VMAXSD = C.PPC_INS_VMAXSD PPC_INS_VMAXSH = C.PPC_INS_VMAXSH PPC_INS_VMAXSW = C.PPC_INS_VMAXSW PPC_INS_VMAXUB = C.PPC_INS_VMAXUB + PPC_INS_VMAXUD = C.PPC_INS_VMAXUD PPC_INS_VMAXUH = C.PPC_INS_VMAXUH PPC_INS_VMAXUW = C.PPC_INS_VMAXUW PPC_INS_VMHADDSHS = C.PPC_INS_VMHADDSHS PPC_INS_VMHRADDSHS = C.PPC_INS_VMHRADDSHS + PPC_INS_VMINUD = C.PPC_INS_VMINUD PPC_INS_VMINFP = C.PPC_INS_VMINFP PPC_INS_VMINSB = C.PPC_INS_VMINSB + PPC_INS_VMINSD = C.PPC_INS_VMINSD PPC_INS_VMINSH = C.PPC_INS_VMINSH PPC_INS_VMINSW = C.PPC_INS_VMINSW PPC_INS_VMINUB = C.PPC_INS_VMINUB @@ -799,15 +976,22 @@ const ( PPC_INS_VMSUMUHS = C.PPC_INS_VMSUMUHS PPC_INS_VMULESB = C.PPC_INS_VMULESB PPC_INS_VMULESH = C.PPC_INS_VMULESH + PPC_INS_VMULESW = C.PPC_INS_VMULESW PPC_INS_VMULEUB = C.PPC_INS_VMULEUB PPC_INS_VMULEUH = C.PPC_INS_VMULEUH + PPC_INS_VMULEUW = C.PPC_INS_VMULEUW PPC_INS_VMULOSB = C.PPC_INS_VMULOSB PPC_INS_VMULOSH = C.PPC_INS_VMULOSH + PPC_INS_VMULOSW = C.PPC_INS_VMULOSW PPC_INS_VMULOUB = C.PPC_INS_VMULOUB PPC_INS_VMULOUH = C.PPC_INS_VMULOUH + PPC_INS_VMULOUW = C.PPC_INS_VMULOUW + PPC_INS_VMULUWM = C.PPC_INS_VMULUWM + PPC_INS_VNAND = C.PPC_INS_VNAND PPC_INS_VNMSUBFP = C.PPC_INS_VNMSUBFP PPC_INS_VNOR = C.PPC_INS_VNOR PPC_INS_VOR = C.PPC_INS_VOR + PPC_INS_VORC = C.PPC_INS_VORC PPC_INS_VPERM = C.PPC_INS_VPERM PPC_INS_VPKPX = C.PPC_INS_VPKPX PPC_INS_VPKSHSS = C.PPC_INS_VPKSHSS @@ -818,18 +1002,24 @@ const ( PPC_INS_VPKUHUS = C.PPC_INS_VPKUHUS PPC_INS_VPKUWUM = C.PPC_INS_VPKUWUM PPC_INS_VPKUWUS = C.PPC_INS_VPKUWUS + PPC_INS_VPOPCNTB = C.PPC_INS_VPOPCNTB + PPC_INS_VPOPCNTD = C.PPC_INS_VPOPCNTD + PPC_INS_VPOPCNTH = C.PPC_INS_VPOPCNTH + PPC_INS_VPOPCNTW = C.PPC_INS_VPOPCNTW PPC_INS_VREFP = C.PPC_INS_VREFP PPC_INS_VRFIM = C.PPC_INS_VRFIM PPC_INS_VRFIN = C.PPC_INS_VRFIN PPC_INS_VRFIP = C.PPC_INS_VRFIP PPC_INS_VRFIZ = C.PPC_INS_VRFIZ PPC_INS_VRLB = C.PPC_INS_VRLB + PPC_INS_VRLD = C.PPC_INS_VRLD PPC_INS_VRLH = C.PPC_INS_VRLH PPC_INS_VRLW = C.PPC_INS_VRLW PPC_INS_VRSQRTEFP = C.PPC_INS_VRSQRTEFP PPC_INS_VSEL = C.PPC_INS_VSEL PPC_INS_VSL = C.PPC_INS_VSL PPC_INS_VSLB = C.PPC_INS_VSLB + PPC_INS_VSLD = C.PPC_INS_VSLD PPC_INS_VSLDOI = C.PPC_INS_VSLDOI PPC_INS_VSLH = C.PPC_INS_VSLH PPC_INS_VSLO = C.PPC_INS_VSLO @@ -842,9 +1032,11 @@ const ( PPC_INS_VSPLTW = C.PPC_INS_VSPLTW PPC_INS_VSR = C.PPC_INS_VSR PPC_INS_VSRAB = C.PPC_INS_VSRAB + PPC_INS_VSRAD = C.PPC_INS_VSRAD PPC_INS_VSRAH = C.PPC_INS_VSRAH PPC_INS_VSRAW = C.PPC_INS_VSRAW PPC_INS_VSRB = C.PPC_INS_VSRB + PPC_INS_VSRD = C.PPC_INS_VSRD PPC_INS_VSRH = C.PPC_INS_VSRH PPC_INS_VSRO = C.PPC_INS_VSRO PPC_INS_VSRW = C.PPC_INS_VSRW @@ -855,6 +1047,7 @@ const ( PPC_INS_VSUBSWS = C.PPC_INS_VSUBSWS PPC_INS_VSUBUBM = C.PPC_INS_VSUBUBM PPC_INS_VSUBUBS = C.PPC_INS_VSUBUBS + PPC_INS_VSUBUDM = C.PPC_INS_VSUBUDM PPC_INS_VSUBUHM = C.PPC_INS_VSUBUHM PPC_INS_VSUBUHS = C.PPC_INS_VSUBUHS PPC_INS_VSUBUWM = C.PPC_INS_VSUBUWM @@ -997,8 +1190,11 @@ const ( PPC_INS_XVTSQRTSP = C.PPC_INS_XVTSQRTSP PPC_INS_XXLAND = C.PPC_INS_XXLAND PPC_INS_XXLANDC = C.PPC_INS_XXLANDC + PPC_INS_XXLEQV = C.PPC_INS_XXLEQV + PPC_INS_XXLNAND = C.PPC_INS_XXLNAND PPC_INS_XXLNOR = C.PPC_INS_XXLNOR PPC_INS_XXLOR = C.PPC_INS_XXLOR + PPC_INS_XXLORC = C.PPC_INS_XXLORC PPC_INS_XXLXOR = C.PPC_INS_XXLXOR PPC_INS_XXMRGHW = C.PPC_INS_XXMRGHW PPC_INS_XXMRGLW = C.PPC_INS_XXMRGLW @@ -1173,6 +1369,18 @@ const ( PPC_INS_BDNZFLRL = C.PPC_INS_BDNZFLRL PPC_INS_BDZTLRL = C.PPC_INS_BDZTLRL PPC_INS_BDZFLRL = C.PPC_INS_BDZFLRL + PPC_INS_QVFAND = C.PPC_INS_QVFAND + PPC_INS_QVFCLR = C.PPC_INS_QVFCLR + PPC_INS_QVFANDC = C.PPC_INS_QVFANDC + PPC_INS_QVFCTFB = C.PPC_INS_QVFCTFB + PPC_INS_QVFXOR = C.PPC_INS_QVFXOR + PPC_INS_QVFOR = C.PPC_INS_QVFOR + PPC_INS_QVFNOR = C.PPC_INS_QVFNOR + PPC_INS_QVFEQU = C.PPC_INS_QVFEQU + PPC_INS_QVFNOT = C.PPC_INS_QVFNOT + PPC_INS_QVFORC = C.PPC_INS_QVFORC + PPC_INS_QVFNAND = C.PPC_INS_QVFNAND + PPC_INS_QVFSET = C.PPC_INS_QVFSET PPC_INS_ENDING = C.PPC_INS_ENDING ) @@ -1188,15 +1396,19 @@ const ( // Architecture-specific groups const ( - PPC_GRP_ALTIVEC = C.PPC_GRP_ALTIVEC - PPC_GRP_MODE32 = C.PPC_GRP_MODE32 - PPC_GRP_MODE64 = C.PPC_GRP_MODE64 - PPC_GRP_BOOKE = C.PPC_GRP_BOOKE - PPC_GRP_NOTBOOKE = C.PPC_GRP_NOTBOOKE - PPC_GRP_SPE = C.PPC_GRP_SPE - PPC_GRP_VSX = C.PPC_GRP_VSX - PPC_GRP_E500 = C.PPC_GRP_E500 - PPC_GRP_PPC4XX = C.PPC_GRP_PPC4XX - PPC_GRP_PPC6XX = C.PPC_GRP_PPC6XX - PPC_GRP_ENDING = C.PPC_GRP_ENDING + PPC_GRP_ALTIVEC = C.PPC_GRP_ALTIVEC + PPC_GRP_MODE32 = C.PPC_GRP_MODE32 + PPC_GRP_MODE64 = C.PPC_GRP_MODE64 + PPC_GRP_BOOKE = C.PPC_GRP_BOOKE + PPC_GRP_NOTBOOKE = C.PPC_GRP_NOTBOOKE + PPC_GRP_SPE = C.PPC_GRP_SPE + PPC_GRP_VSX = C.PPC_GRP_VSX + PPC_GRP_E500 = C.PPC_GRP_E500 + PPC_GRP_PPC4XX = C.PPC_GRP_PPC4XX + PPC_GRP_PPC6XX = C.PPC_GRP_PPC6XX + PPC_GRP_ICBT = C.PPC_GRP_ICBT + PPC_GRP_P8ALTIVEC = C.PPC_GRP_P8ALTIVEC + PPC_GRP_P8VECTOR = C.PPC_GRP_P8VECTOR + PPC_GRP_QPX = C.PPC_GRP_QPX + PPC_GRP_ENDING = C.PPC_GRP_ENDING ) diff --git a/ppc_decomposer.go b/ppc_decomposer.go index 99013b9..3b4390e 100644 --- a/ppc_decomposer.go +++ b/ppc_decomposer.go @@ -44,7 +44,7 @@ func (insn PPCInstruction) OpCount(optype uint) int { type PPCOperand struct { Type uint // PPC_OP_* - determines which field is set below Reg uint - Imm int32 + Imm int64 Mem PPCMemoryOperand CRX PPCCRXOperand } @@ -95,7 +95,7 @@ func fillPPCHeader(raw C.cs_insn, insn *Instruction) { switch cop._type { // fake a union by setting only the correct struct member case PPC_OP_IMM: - gop.Imm = int32(*(*C.int32_t)(unsafe.Pointer(&cop.anon0[0]))) + gop.Imm = int64(*(*C.int32_t)(unsafe.Pointer(&cop.anon0[0]))) case PPC_OP_REG: gop.Reg = uint(*(*C.uint)(unsafe.Pointer(&cop.anon0[0]))) case PPC_OP_MEM: @@ -120,11 +120,11 @@ func fillPPCHeader(raw C.cs_insn, insn *Instruction) { insn.PPC = &ppc } -func decomposePPC(raws []C.cs_insn) []Instruction { +func decomposePPC(e *Engine, raws []C.cs_insn) []Instruction { decomposed := []Instruction{} for _, raw := range raws { decomp := new(Instruction) - fillGenericHeader(raw, decomp) + fillGenericHeader(e, raw, decomp) fillPPCHeader(raw, decomp) decomposed = append(decomposed, *decomp) } diff --git a/ppc_decomposer_test.go b/ppc_decomposer_test.go index d1d3a62..8a059ac 100644 --- a/ppc_decomposer_test.go +++ b/ppc_decomposer_test.go @@ -55,7 +55,7 @@ func ppcInsnDetail(insn Instruction, engine *Engine, buf *bytes.Buffer) { case PPC_OP_REG: fmt.Fprintf(buf, "\t\toperands[%v].type: REG = %v\n", i, engine.RegName(op.Reg)) case PPC_OP_IMM: - fmt.Fprintf(buf, "\t\toperands[%v].type: IMM = 0x%x\n", i, (uint32(op.Imm))) + fmt.Fprintf(buf, "\t\toperands[%v].type: IMM = 0x%x\n", i, uint64(op.Imm)) case PPC_OP_MEM: fmt.Fprintf(buf, "\t\toperands[%v].type: MEM\n", i) if op.Mem.Base != PPC_REG_INVALID { diff --git a/sparc_constants.go b/sparc_constants.go index 19da403..93afc18 100644 --- a/sparc_constants.go +++ b/sparc_constants.go @@ -8,8 +8,8 @@ try reading the *_test.go files. (c) 2013 COSEINC. All Rights Reserved. THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT! - Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/ - 2016-04-13T12:04:37+09:30 + Command: ./genconst /Users/scottknight/work/capstone/bindings/python/capstone/ + 2019-02-02T13:26:27-05:00 */ diff --git a/sparc_decomposer.go b/sparc_decomposer.go index ed01a7e..c7536f2 100644 --- a/sparc_decomposer.go +++ b/sparc_decomposer.go @@ -46,7 +46,7 @@ func (insn SparcInstruction) OpCount(optype uint) int { type SparcOperand struct { Type uint // SPARC_OP_* - determines which field is set below Reg uint - Imm int32 + Imm int64 Mem SparcMemoryOperand } @@ -91,7 +91,7 @@ func fillSparcHeader(raw C.cs_insn, insn *Instruction) { switch cop._type { // fake a union by setting only the correct struct member case SPARC_OP_IMM: - gop.Imm = int32(*(*C.int32_t)(unsafe.Pointer(&cop.anon0[0]))) + gop.Imm = int64(*(*C.int32_t)(unsafe.Pointer(&cop.anon0[0]))) case SPARC_OP_REG: gop.Reg = uint(*(*C.uint)(unsafe.Pointer(&cop.anon0[0]))) case SPARC_OP_MEM: @@ -109,11 +109,11 @@ func fillSparcHeader(raw C.cs_insn, insn *Instruction) { insn.Sparc = &sparc } -func decomposeSparc(raws []C.cs_insn) []Instruction { +func decomposeSparc(e *Engine, raws []C.cs_insn) []Instruction { decomposed := []Instruction{} for _, raw := range raws { decomp := new(Instruction) - fillGenericHeader(raw, decomp) + fillGenericHeader(e, raw, decomp) fillSparcHeader(raw, decomp) decomposed = append(decomposed, *decomp) } diff --git a/sysz_constants.go b/sysz_constants.go index b67cfad..a302896 100644 --- a/sysz_constants.go +++ b/sysz_constants.go @@ -8,8 +8,8 @@ try reading the *_test.go files. (c) 2013 COSEINC. All Rights Reserved. THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT! - Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/ - 2016-04-13T12:04:37+09:30 + Command: ./genconst /Users/scottknight/work/capstone/bindings/python/capstone/ + 2019-02-02T13:26:27-05:00 */ diff --git a/sysz_decomposer.go b/sysz_decomposer.go index 9011503..dbc38fd 100644 --- a/sysz_decomposer.go +++ b/sysz_decomposer.go @@ -107,11 +107,11 @@ func fillSysZHeader(raw C.cs_insn, insn *Instruction) { insn.SysZ = &sysz } -func decomposeSysZ(raws []C.cs_insn) []Instruction { +func decomposeSysZ(e *Engine, raws []C.cs_insn) []Instruction { decomposed := []Instruction{} for _, raw := range raws { decomp := new(Instruction) - fillGenericHeader(raw, decomp) + fillGenericHeader(e, raw, decomp) fillSysZHeader(raw, decomp) decomposed = append(decomposed, *decomp) } diff --git a/test.SPEC b/test.SPEC index 883184e..a021ff0 100644 --- a/test.SPEC +++ b/test.SPEC @@ -2,7 +2,7 @@ Platform: X86 16bit (Intel syntax) Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 Disasm: -0x1000: lea cx, word ptr [si + 0x32] +0x1000: lea cx, [si + 0x32] 0x1003: or byte ptr [bx + di], al 0x1005: fadd dword ptr [bx + di + 0x34c6] 0x1009: adc al, byte ptr [bx + si] @@ -10,21 +10,33 @@ Disasm: **************** Platform: X86 32bit (ATT syntax) -Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 +Code: 0xba 0xcd 0xab 0x00 0x00 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 Disasm: -0x1000: leal 8(%edx, %esi), %ecx -0x1004: addl %ebx, %eax -0x1006: addl $0x1234, %esi -0x100c: +0x1000: movl $0xabcd, %edx +0x1005: leal 8(%edx, %esi), %ecx +0x1009: addl %ebx, %eax +0x100b: addl $0x1234, %esi +0x1011: **************** Platform: X86 32 (Intel syntax) -Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 +Code: 0xba 0xcd 0xab 0x00 0x00 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 Disasm: -0x1000: lea ecx, dword ptr [edx + esi + 8] -0x1004: add eax, ebx -0x1006: add esi, 0x1234 -0x100c: +0x1000: mov edx, 0xabcd +0x1005: lea ecx, [edx + esi + 8] +0x1009: add eax, ebx +0x100b: add esi, 0x1234 +0x1011: + +**************** +Platform: X86 32 (MASM syntax) +Code: 0xba 0xcd 0xab 0x00 0x00 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 +Disasm: +0x1000: mov edx, 0abcdh +0x1005: lea ecx, [edx + esi + 8] +0x1009: add eax, ebx +0x100b: add esi, 1234h +0x1011: **************** Platform: X86 64 (Intel syntax) @@ -140,38 +152,6 @@ Disasm: 0x100c: ldr w1, [sp, #8] 0x1010: -**************** -Platform: PPC-64 -Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 -Disasm: -0x1000: lwz r1, (0) -0x1004: lwz r1, (r31) -0x1008: vpkpx v2, v3, v4 -0x100c: stfs f2, 0x80(r4) -0x1010: crand 2, 3, 4 -0x1014: cmpwi cr2, r3, 0x80 -0x1018: addc r2, r3, r4 -0x101c: mulhd. r2, r3, r4 -0x1020: bdnzlrl+ -0x1024: bgelrl- cr2 -0x1028: - -**************** -Platform: PPC-64, print register with number only -Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 -Disasm: -0x1000: lwz 1, (0) -0x1004: lwz 1, (31) -0x1008: vpkpx 2, 3, 4 -0x100c: stfs 2, 0x80(4) -0x1010: crand 2, 3, 4 -0x1014: cmpwi 2, 3, 0x80 -0x1018: addc 2, 3, 4 -0x101c: mulhd. 2, 3, 4 -0x1020: bdnzlrl+ -0x1024: bgelrl- cr2 -0x1028: - **************** Platform: Sparc Code: 0x80 0xa0 0x40 0x02 0x85 0xc2 0x60 0x08 0x85 0xe8 0x20 0x01 0x81 0xe8 0x00 0x00 0x90 0x10 0x20 0x01 0xd5 0xf6 0x10 0x16 0x21 0x00 0x00 0x0a 0x86 0x00 0x40 0x02 0x01 0x00 0x00 0x00 0x12 0xbf 0xff 0xff 0x10 0xbf 0xff 0xff 0xa0 0x02 0x00 0x09 0x0d 0xbf 0xff 0xff 0xd4 0x20 0x60 0x00 0xd4 0x4e 0x00 0x16 0x2a 0xc2 0x80 0x03 @@ -233,3 +213,58 @@ Disasm: 0x101a: add r1, r2, r3 0x101c: +**************** +Platform: M68K +Code: 0xd4 0x40 0x87 0x5a 0x4e 0x71 0x02 0xb4 0xc0 0xde 0xc0 0xde 0x5c 0x00 0x1d 0x80 0x71 0x12 0x01 0x23 0xf2 0x3c 0x44 0x22 0x40 0x49 0x0e 0x56 0x54 0xc5 0xf2 0x3c 0x44 0x00 0x44 0x7a 0x00 0x00 0xf2 0x00 0x0a 0x28 +Disasm: +0x1000: add.w d0, d2 +0x1002: or.w d3, (a2)+ +0x1004: nop +0x1006: andi.l #$c0dec0de, (a4, d5.l * 4) +0x100e: move.b d0, ([a6, d7.w], $123) +0x1014: fadd.s #3.141500, fp0 +0x101c: scc.b d5 +0x101e: fmove.s #1000.000000, fp0 +0x1026: fsub fp2, fp4 +0x102a: + +**************** +Platform: TMS320C64x +Code: 0x01 0xac 0x88 0x40 0x81 0xac 0x88 0x43 0x00 0x00 0x00 0x00 0x02 0x90 0x32 0x96 0x02 0x80 0x46 0x9e 0x05 0x3c 0x83 0xe6 0x0b 0x0c 0x8b 0x24 +Disasm: +0x1000: add a11, a4, a3 +0x1004: add b11, b4, b3 +0x1008: NOP +0x100c: ldbu *++a4[1], b5 +0x1010: ldbu *+b15[0x46], b5 +0x1014: lddw *+a15[4], b11:b10 +0x1018: ldndw *+a3(a4), a23:a22 +0x101c: + +**************** +Platform: M680X_M6809 +Code: 0x06 0x10 0x19 0x1a 0x55 0x1e 0x01 0x23 0xe9 0x31 0x06 0x34 0x55 0xa6 0x81 0xa7 0x89 0x7f 0xff 0xa6 0x9d 0x10 0x00 0xa7 0x91 0xa6 0x9f 0x10 0x00 0x11 0xac 0x99 0x10 0x00 0x39 +Disasm: +0x1000: ror $10 +0x1002: daa +0x1003: orcc #85 +0x1005: exg d,x +0x1007: bls $0FF2 +0x1009: leay 6,x +0x100b: pshs cc,b,x,u +0x100d: lda ,x++ +0x100f: sta 32767,x +0x1013: lda [$2017,pcR] +0x1017: sta [,x++] +0x1019: lda [$1000] +0x101d: cmps [4096,x] +0x1022: rts +0x1023: + +**************** +Platform: EVM +Code: 0x60 0x61 +Disasm: +0x1000: push1 61 +0x1002: + diff --git a/test_detail.SPEC b/test_detail.SPEC index 1bf2195..814b0e1 100644 --- a/test_detail.SPEC +++ b/test_detail.SPEC @@ -2,11 +2,12 @@ Platform: X86 16bit (Intel syntax) Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 Disasm: -0x1000: lea cx, word ptr [si + 0x32] // insn-ID: 315, insn-mnem: lea -0x1003: or byte ptr [bx + di], al // insn-ID: 325, insn-mnem: or +0x1000: lea cx, [si + 0x32] // insn-ID: 322, insn-mnem: lea +0x1003: or byte ptr [bx + di], al // insn-ID: 332, insn-mnem: or Implicit registers modified: flags 0x1005: fadd dword ptr [bx + di + 0x34c6] // insn-ID: 15, insn-mnem: fadd Implicit registers modified: fpsw + This instruction belongs to groups: fpu 0x1009: adc al, byte ptr [bx + si] // insn-ID: 6, insn-mnem: adc Implicit registers read: flags Implicit registers modified: flags @@ -16,7 +17,7 @@ Disasm: Platform: X86 32bit (ATT syntax) Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 Disasm: -0x1000: leal 8(%edx, %esi), %ecx // insn-ID: 315, insn-mnem: lea +0x1000: leal 8(%edx, %esi), %ecx // insn-ID: 322, insn-mnem: lea This instruction belongs to groups: not64bitmode 0x1004: addl %ebx, %eax // insn-ID: 8, insn-mnem: add Implicit registers modified: eflags @@ -28,7 +29,7 @@ Disasm: Platform: X86 32 (Intel syntax) Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 Disasm: -0x1000: lea ecx, dword ptr [edx + esi + 8] // insn-ID: 315, insn-mnem: lea +0x1000: lea ecx, [edx + esi + 8] // insn-ID: 322, insn-mnem: lea This instruction belongs to groups: not64bitmode 0x1004: add eax, ebx // insn-ID: 8, insn-mnem: add Implicit registers modified: eflags @@ -40,11 +41,11 @@ Disasm: Platform: X86 64 (Intel syntax) Code: 0x55 0x48 0x8b 0x05 0xb8 0x13 0x00 0x00 Disasm: -0x1000: push rbp // insn-ID: 580, insn-mnem: push +0x1000: push rbp // insn-ID: 588, insn-mnem: push Implicit registers read: rsp Implicit registers modified: rsp This instruction belongs to groups: mode64 -0x1001: mov rax, qword ptr [rip + 0x13b8] // insn-ID: 442, insn-mnem: mov +0x1001: mov rax, qword ptr [rip + 0x13b8] // insn-ID: 449, insn-mnem: mov 0x1008: **************** @@ -53,19 +54,19 @@ Code: 0xed 0xff 0xff 0xeb 0x04 0xe0 0x2d 0xe5 0x00 0x00 0x00 0x00 0xe0 0x83 0x22 Disasm: 0x1000: bl #0xfbc // insn-ID: 13, insn-mnem: bl Implicit registers read: pc - Implicit registers modified: lr - This instruction belongs to groups: arm jump -0x1004: str lr, [sp, #-4]! // insn-ID: 212, insn-mnem: str + Implicit registers modified: lr pc + This instruction belongs to groups: call branch_relative arm jump +0x1004: str lr, [sp, #-4]! // insn-ID: 214, insn-mnem: str This instruction belongs to groups: arm 0x1008: andeq r0, r0, r0 // insn-ID: 8, insn-mnem: and This instruction belongs to groups: arm -0x100c: str r8, [r2, #-0x3e0]! // insn-ID: 212, insn-mnem: str +0x100c: str r8, [r2, #-0x3e0]! // insn-ID: 214, insn-mnem: str This instruction belongs to groups: arm -0x1010: mcreq p2, #0, r0, c3, c1, #7 // insn-ID: 74, insn-mnem: mcr +0x1010: mcreq p2, #0, r0, c3, c1, #7 // insn-ID: 76, insn-mnem: mcr + This instruction belongs to groups: privilege arm +0x1014: mov r0, #0 // insn-ID: 82, insn-mnem: mov This instruction belongs to groups: arm -0x1014: mov r0, #0 // insn-ID: 80, insn-mnem: mov - This instruction belongs to groups: arm -0x1018: strb r3, [r1, r2] // insn-ID: 203, insn-mnem: strb +0x1018: strb r3, [r1, r2] // insn-ID: 205, insn-mnem: strb This instruction belongs to groups: arm 0x101c: cmp r3, #0 // insn-ID: 23, insn-mnem: cmp Implicit registers modified: cpsr @@ -76,11 +77,13 @@ Disasm: Platform: THUMB-2 Code: 0x4f 0xf0 0x00 0x01 0xbd 0xe8 0x00 0x88 0xd1 0xe8 0x00 0xf0 Disasm: -0x1000: mov.w r1, #0 // insn-ID: 80, insn-mnem: mov +0x1000: mov.w r1, #0 // insn-ID: 82, insn-mnem: mov This instruction belongs to groups: thumb2 -0x1004: pop.w {fp, pc} // insn-ID: 425, insn-mnem: pop +0x1004: pop.w {fp, pc} // insn-ID: 423, insn-mnem: pop + Implicit registers read: sp + Implicit registers modified: sp This instruction belongs to groups: thumb2 -0x1008: tbb [r1, r0] // insn-ID: 420, insn-mnem: tbb +0x1008: tbb [r1, r0] // insn-ID: 419, insn-mnem: tbb This instruction belongs to groups: thumb2 jump 0x100c: @@ -88,13 +91,13 @@ Disasm: Platform: ARM: Cortex-A15 + NEON Code: 0x10 0xf1 0x10 0xe7 0x11 0xf2 0x31 0xe7 0xdc 0xa1 0x2e 0xf3 0xe8 0x4e 0x62 0xf3 Disasm: -0x1000: sdiv r0, r0, r1 // insn-ID: 122, insn-mnem: sdiv +0x1000: sdiv r0, r0, r1 // insn-ID: 124, insn-mnem: sdiv This instruction belongs to groups: arm -0x1004: udiv r1, r1, r2 // insn-ID: 231, insn-mnem: udiv +0x1004: udiv r1, r1, r2 // insn-ID: 233, insn-mnem: udiv This instruction belongs to groups: arm -0x1008: vbit q5, q15, q6 // insn-ID: 274, insn-mnem: vbit +0x1008: vbit q5, q15, q6 // insn-ID: 276, insn-mnem: vbit This instruction belongs to groups: neon -0x100c: vcgt.f32 q10, q9, q12 // insn-ID: 278, insn-mnem: vcgt +0x100c: vcgt.f32 q10, q9, q12 // insn-ID: 280, insn-mnem: vcgt This instruction belongs to groups: neon 0x1010: @@ -103,12 +106,13 @@ Platform: THUMB Code: 0x70 0x47 0xeb 0x46 0x83 0xb0 0xc9 0x68 Disasm: 0x1000: bx lr // insn-ID: 15, insn-mnem: bx + Implicit registers modified: pc This instruction belongs to groups: thumb jump -0x1002: mov fp, sp // insn-ID: 80, insn-mnem: mov +0x1002: mov fp, sp // insn-ID: 82, insn-mnem: mov This instruction belongs to groups: thumb thumb1only -0x1004: sub sp, #0xc // insn-ID: 213, insn-mnem: sub +0x1004: sub sp, #0xc // insn-ID: 215, insn-mnem: sub This instruction belongs to groups: thumb thumb1only -0x1006: ldr r1, [r1, #0xc] // insn-ID: 73, insn-mnem: ldr +0x1006: ldr r1, [r1, #0xc] // insn-ID: 75, insn-mnem: ldr This instruction belongs to groups: thumb thumb1only 0x1008: @@ -116,7 +120,7 @@ Disasm: Platform: Thumb-MClass Code: 0xef 0xf3 0x02 0x80 Disasm: -0x1000: mrs r0, eapsr // insn-ID: 87, insn-mnem: mrs +0x1000: mrs r0, eapsr // insn-ID: 89, insn-mnem: mrs This instruction belongs to groups: thumb mclass 0x1004: @@ -124,7 +128,7 @@ Disasm: Platform: Arm-V8 Code: 0xe0 0x3b 0xb2 0xee 0x42 0x00 0x01 0xe1 0x51 0xf0 0x7f 0xf5 Disasm: -0x1000: vcvtt.f64.f16 d3, s1 // insn-ID: 292, insn-mnem: vcvtt +0x1000: vcvtt.f64.f16 d3, s1 // insn-ID: 294, insn-mnem: vcvtt This instruction belongs to groups: fparmv8 dpvfp 0x1004: crc32b r0, r1, r2 // insn-ID: 25, insn-mnem: crc32b This instruction belongs to groups: arm v8 crc @@ -136,18 +140,18 @@ Disasm: Platform: MIPS-32 (Big-endian) Code: 0x0c 0x10 0x00 0x97 0x00 0x00 0x00 0x00 0x24 0x02 0x00 0x0c 0x8f 0xa2 0x00 0x00 0x34 0x21 0x34 0x56 0x00 0x80 0x04 0x08 Disasm: -0x1000: jal 0x40025c // insn-ID: 322, insn-mnem: jal +0x1000: jal 0x40025c // insn-ID: 337, insn-mnem: jal Implicit registers modified: ra This instruction belongs to groups: stdenc -0x1004: nop // insn-ID: 582, insn-mnem: nop - This instruction belongs to groups: stdenc -0x1008: addiu $v0, $zero, 0xc // insn-ID: 21, insn-mnem: addiu - This instruction belongs to groups: stdenc -0x100c: lw $v0, ($sp) // insn-ID: 353, insn-mnem: lw - This instruction belongs to groups: stdenc -0x1010: ori $at, $at, 0x3456 // insn-ID: 445, insn-mnem: ori +0x1004: nop // insn-ID: 622, insn-mnem: nop + This instruction belongs to groups: stdenc notinmicromips +0x1008: addiu $v0, $zero, 0xc // insn-ID: 26, insn-mnem: addiu + This instruction belongs to groups: stdenc notinmicromips +0x100c: lw $v0, ($sp) // insn-ID: 373, insn-mnem: lw + This instruction belongs to groups: stdenc notinmicromips +0x1010: ori $at, $at, 0x3456 // insn-ID: 473, insn-mnem: ori This instruction belongs to groups: stdenc -0x1014: jr.hb $a0 // insn-ID: 585, insn-mnem: jr.hb +0x1014: jr.hb $a0 // insn-ID: 345, insn-mnem: jr This instruction belongs to groups: stdenc mips32 notmips32r6 notmips64r6 jump 0x1018: @@ -155,23 +159,23 @@ Disasm: Platform: MIPS-64-EL (Little-endian) Code: 0x56 0x34 0x21 0x34 0xc2 0x17 0x01 0x00 Disasm: -0x1000: ori $at, $at, 0x3456 // insn-ID: 445, insn-mnem: ori - This instruction belongs to groups: stdenc -0x1004: srl $v0, $at, 0x1f // insn-ID: 525, insn-mnem: srl +0x1000: ori $at, $at, 0x3456 // insn-ID: 473, insn-mnem: ori This instruction belongs to groups: stdenc +0x1004: srl $v0, $at, 0x1f // insn-ID: 557, insn-mnem: srl + This instruction belongs to groups: stdenc notinmicromips 0x1008: **************** Platform: MIPS-32R6 | Micro (Big-endian) Code: 0x00 0x07 0x00 0x07 0x00 0x11 0x93 0x7c 0x01 0x8c 0x8b 0x7c 0x00 0xc7 0x48 0xd0 Disasm: -0x1000: break 7, 0 // insn-ID: 114, insn-mnem: break - This instruction belongs to groups: micromips -0x1004: wait 0x11 // insn-ID: 577, insn-mnem: wait +0x1000: break 7, 0 // insn-ID: 128, insn-mnem: break This instruction belongs to groups: micromips -0x1008: syscall 0x18c // insn-ID: 555, insn-mnem: syscall +0x1004: wait 0x11 // insn-ID: 616, insn-mnem: wait This instruction belongs to groups: micromips -0x100c: rotrv $t1, $a2, $a3 // insn-ID: 471, insn-mnem: rotrv +0x1008: syscall 0x18c // insn-ID: 594, insn-mnem: syscall + This instruction belongs to groups: micromips int +0x100c: rotrv $t1, $a2, $a3 // insn-ID: 499, insn-mnem: rotrv This instruction belongs to groups: micromips 0x1010: @@ -181,7 +185,7 @@ Code: 0xec 0x80 0x00 0x19 0x7c 0x43 0x22 0xa0 Disasm: 0x1000: addiupc $a0, 0x64 // insn-ID: 3, insn-mnem: addiupc This instruction belongs to groups: stdenc mips32r6 -0x1004: align $a0, $v0, $v1, 2 // insn-ID: 22, insn-mnem: align +0x1004: align $a0, $v0, $v1, 2 // insn-ID: 27, insn-mnem: align This instruction belongs to groups: stdenc mips32r6 0x1008: @@ -190,9 +194,12 @@ Platform: ARM-64 Code: 0x09 0x00 0x38 0xd5 0xbf 0x40 0x00 0xd5 0x0c 0x05 0x13 0xd5 0x20 0x50 0x02 0x0e 0x20 0xe4 0x3d 0x0f 0x00 0x18 0xa0 0x5f 0xa2 0x00 0xae 0x9e 0x9f 0x37 0x03 0xd5 0xbf 0x33 0x03 0xd5 0xdf 0x3f 0x03 0xd5 0x21 0x7c 0x02 0x9b 0x21 0x7c 0x00 0x53 0x00 0x40 0x21 0x4b 0xe1 0x0b 0x40 0xb9 0x20 0x04 0x81 0xda 0x20 0x08 0x02 0x8b 0x10 0x5b 0xe8 0x3c Disasm: 0x1000: mrs x9, midr_el1 // insn-ID: 192, insn-mnem: mrs + This instruction belongs to groups: privilege 0x1004: msr spsel, #0 // insn-ID: 193, insn-mnem: msr Implicit registers modified: nzcv + This instruction belongs to groups: privilege 0x1008: msr dbgdtrtx_el0, x12 // insn-ID: 193, insn-mnem: msr + This instruction belongs to groups: privilege 0x100c: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // insn-ID: 347, insn-mnem: tbx This instruction belongs to groups: neon 0x1010: scvtf v0.2s, v1.2s, #3 // insn-ID: 234, insn-mnem: scvtf @@ -214,32 +221,6 @@ Disasm: 0x1040: ldr q16, [x24, w8, uxtw #4] // insn-ID: 162, insn-mnem: ldr 0x1044: -**************** -Platform: PPC-64 -Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 0x40 0x82 0x00 0x14 -Disasm: -0x1000: lwz r1, (0) // insn-ID: 347, insn-mnem: lwz -0x1004: lwz r1, (r31) // insn-ID: 347, insn-mnem: lwz -0x1008: vpkpx v2, v3, v4 // insn-ID: 570, insn-mnem: vpkpx - This instruction belongs to groups: altivec -0x100c: stfs f2, 0x80(r4) // insn-ID: 443, insn-mnem: stfs -0x1010: crand 2, 3, 4 // insn-ID: 52, insn-mnem: crand -0x1014: cmpwi cr2, r3, 0x80 // insn-ID: 47, insn-mnem: cmpwi -0x1018: addc r2, r3, r4 // insn-ID: 2, insn-mnem: addc - Implicit registers modified: ca -0x101c: mulhd. r2, r3, r4 // insn-ID: 384, insn-mnem: mulhd - Implicit registers modified: cr0 -0x1020: bdnzlrl+ // insn-ID: 28, insn-mnem: bdnzlrl - Implicit registers read: ctr lr rm - Implicit registers modified: ctr -0x1024: bgelrl- cr2 // insn-ID: 38, insn-mnem: blrl - Implicit registers read: ctr lr rm - Implicit registers modified: lr ctr -0x1028: bne 0x103c // insn-ID: 13, insn-mnem: b - Implicit registers read: ctr rm - Implicit registers modified: ctr -0x102c: - **************** Platform: Sparc Code: 0x80 0xa0 0x40 0x02 0x85 0xc2 0x60 0x08 0x85 0xe8 0x20 0x01 0x81 0xe8 0x00 0x00 0x90 0x10 0x20 0x01 0xd5 0xf6 0x10 0x16 0x21 0x00 0x00 0x0a 0x86 0x00 0x40 0x02 0x01 0x00 0x00 0x00 0x12 0xbf 0xff 0xff 0x10 0xbf 0xff 0xff 0xa0 0x02 0x00 0x09 0x0d 0xbf 0xff 0xff 0xd4 0x20 0x60 0x00 0xd4 0x4e 0x00 0x16 0x2a 0xc2 0x80 0x03 @@ -320,3 +301,78 @@ Disasm: 0x101a: add r1, r2, r3 // insn-ID: 1, insn-mnem: add 0x101c: +**************** +Platform: M68K +Code: 0xd4 0x40 0x87 0x5a 0x4e 0x71 0x02 0xb4 0xc0 0xde 0xc0 0xde 0x5c 0x00 0x1d 0x80 0x71 0x12 0x01 0x23 0xf2 0x3c 0x44 0x22 0x40 0x49 0x0e 0x56 0x54 0xc5 0xf2 0x3c 0x44 0x00 0x44 0x7a 0x00 0x00 0xf2 0x00 0x0a 0x28 +Disasm: +0x1000: add.w d0, d2 // insn-ID: 2, insn-mnem: add + Implicit registers read: d0 + Implicit registers modified: d2 +0x1002: or.w d3, (a2)+ // insn-ID: 296, insn-mnem: or + Implicit registers read: d3 + Implicit registers modified: a2 +0x1004: nop // insn-ID: 294, insn-mnem: nop +0x1006: andi.l #$c0dec0de, (a4, d5.l * 4) // insn-ID: 8, insn-mnem: andi + Implicit registers read: d5 a4 +0x100e: move.b d0, ([a6, d7.w], $123) // insn-ID: 281, insn-mnem: move + Implicit registers read: d0 d7 a6 +0x1014: fadd.s #3.141500, fp0 // insn-ID: 89, insn-mnem: fadd + Implicit registers modified: fp0 +0x101c: scc.b d5 // insn-ID: 330, insn-mnem: scc + Implicit registers modified: d5 +0x101e: fmove.s #1000.000000, fp0 // insn-ID: 176, insn-mnem: fmove + Implicit registers modified: fp0 +0x1026: fsub fp2, fp4 // insn-ID: 232, insn-mnem: fsub + Implicit registers read: fp2 + Implicit registers modified: fp4 +0x102a: + +**************** +Platform: M680X_M6809 +Code: 0x06 0x10 0x19 0x1a 0x55 0x1e 0x01 0x23 0xe9 0x31 0x06 0x34 0x55 0xa6 0x81 0xa7 0x89 0x7f 0xff 0xa6 0x9d 0x10 0x00 0xa7 0x91 0xa6 0x9f 0x10 0x00 0x11 0xac 0x99 0x10 0x00 0x39 +Disasm: +0x1000: ror $10 // insn-ID: 276, insn-mnem: ror + Implicit registers read: cc + Implicit registers modified: cc +0x1002: daa // insn-ID: 117, insn-mnem: daa + Implicit registers read: cc a + Implicit registers modified: cc a +0x1003: orcc #85 // insn-ID: 243, insn-mnem: orcc + Implicit registers read: cc + Implicit registers modified: cc +0x1005: exg d,x // insn-ID: 153, insn-mnem: exg + Implicit registers read: d x + Implicit registers modified: d x +0x1007: bls $0FF2 // insn-ID: 58, insn-mnem: bls + Implicit registers read: cc + This instruction belongs to groups: branch_relative jump +0x1009: leay 6,x // insn-ID: 209, insn-mnem: leay + Implicit registers read: cc x + Implicit registers modified: cc y +0x100b: pshs cc,b,x,u // insn-ID: 251, insn-mnem: pshs + Implicit registers read: s cc b x u + Implicit registers modified: s +0x100d: lda ,x++ // insn-ID: 190, insn-mnem: lda + Implicit registers read: cc x + Implicit registers modified: cc a x +0x100f: sta 32767,x // insn-ID: 298, insn-mnem: sta + Implicit registers read: cc a x + Implicit registers modified: cc +0x1013: lda [$2017,pcR] // insn-ID: 190, insn-mnem: lda + Implicit registers read: cc pc + Implicit registers modified: cc a +0x1017: sta [,x++] // insn-ID: 298, insn-mnem: sta + Implicit registers read: cc a x + Implicit registers modified: cc x +0x1019: lda [$1000] // insn-ID: 190, insn-mnem: lda + Implicit registers read: cc + Implicit registers modified: cc a +0x101d: cmps [4096,x] // insn-ID: 98, insn-mnem: cmps + Implicit registers read: cc s x + Implicit registers modified: cc +0x1022: rts // insn-ID: 285, insn-mnem: rts + Implicit registers read: s + Implicit registers modified: s pc + This instruction belongs to groups: return +0x1023: + diff --git a/test_resources_test.go b/test_resources_test.go index c9a6d34..a139f8b 100644 --- a/test_resources_test.go +++ b/test_resources_test.go @@ -17,7 +17,7 @@ import ( // Maintain the expected version and sanity checks manually, so we can verify // against the installed C lib. Not foolproof, but should save 90% of accidents -const expectedMaj = 3 +const expectedMaj = 4 const expectedMin = 0 type sanityCheck struct { @@ -37,23 +37,23 @@ func (s *sanityChecks) Min() int { return expectedMin } var checks = sanityChecks{ CS_ARCH_ARM64: sanityCheck{ regMax: 260, - insMax: 452, + insMax: 454, grpMax: 132, }, CS_ARCH_ARM: sanityCheck{ regMax: 111, - insMax: 435, - grpMax: 159, + insMax: 433, + grpMax: 160, }, CS_ARCH_MIPS: sanityCheck{ - regMax: 136, - insMax: 586, + regMax: 137, + insMax: 626, grpMax: 161, }, CS_ARCH_PPC: sanityCheck{ - regMax: 178, - insMax: 934, - grpMax: 138, + regMax: 210, + insMax: 1110, + grpMax: 142, }, CS_ARCH_SPARC: sanityCheck{ regMax: 88, @@ -66,9 +66,9 @@ var checks = sanityChecks{ grpMax: 133, }, CS_ARCH_X86: sanityCheck{ - regMax: 234, - insMax: 1295, - grpMax: 169, + regMax: 242, + insMax: 1501, + grpMax: 170, }, CS_ARCH_XCORE: sanityCheck{ regMax: 26, @@ -84,7 +84,7 @@ type option struct { type platform struct { arch int - mode uint + mode int options []option code string comment string @@ -93,43 +93,76 @@ type platform struct { type platforms []platform var address = uint64(0x1000) -var armCode = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00" + +var armCode = "\x86\x48\x60\xf4\x4d\x0f\xe2\xf4\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00" var armCode2 = "\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c" -var thumbCode = "\x70\x47\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84" +var thumbCode = "\x60\xf9\x1f\x04\xe0\xf9\x4f\x07\x70\x47\x00\xf0\x10\xe8\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84\x52\xf8\x23\xf0" var thumbCode2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01" var thumbMClass = "\xef\xf3\x02\x80" var armV8 = "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" var arm64Code = "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c" -var x86Code64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00" -var x86Code16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6" -var x86Code32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6" +var x86Code64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00\xe9\xea\xbe\xad\xde\xff\x25\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff" +var x86Code16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\x66\xe9\xb8\x00\x00\x00\x67\xff\xa0\x23\x01\x00\x00\x66\xe8\xcb\x00\x00\x00\x74\xfc" +var x86Code32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\xe9\xea\xbe\xad\xde\xff\xa0\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff" var mipsCode = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56" var mipsCode2 = "\x56\x34\x21\x34\xc2\x17\x01\x00" var mips32R6M = "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" var mips32R6 = "\xec\x80\x00\x19\x7c\x43\x22\xa0" +var mips64SD = "\x70\x00\xb2\xff" +var ppcCode = "\x43\x20\x0c\x07\x41\x56\xff\x17\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14" +var ppcCode2 = "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" +var sysZCode = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78\xec\x18\x00\x00\xc1\x7f" +var sparcCode = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" +var sparcV9Code = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" +var xcoreCode = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10\x09\xfd\xec\xa7" + var basicX86Code16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" -var basicX86Code32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +var basicX86Code32 = "\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" var basicX86Code64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00" var basicArmCode = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3" var basicArmCode2 = "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3" +var basicArmV8 = "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" +var basicThumbMClass = "\xef\xf3\x02\x80" var basicThumbCode = "\x70\x47\xeb\x46\x83\xb0\xc9\x68" var basicThumbCode2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0" -var basicMipsCode = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08" +var basicMipsCode = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56" var basicMipsCode2 = "\x56\x34\x21\x34\xc2\x17\x01\x00" -var basicMips32R6 = "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" -var basicArm64Code = "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c" -var basicArm64Code2 = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9" -var basicPPCCode = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14" -var basicPPCCode2 = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21" +var basicMips32R6M = "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" +var basicMips32R6 = "\xec\x80\x00\x19\x7c\x43\x22\xa0" +var basicArm64Code = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9" +var basicPPCCode = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21" +var basicPPCCode2 = "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" var basicSparcCode = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" var basicSparcV9Code = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" var basicSysZCode = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" var basicXcoreCode = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" -var ppcCode = "\x43\x20\x0c\x07\x41\x56\xff\x17\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14" -var sysZCode = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78\xec\x18\x00\x00\xc1\x7f" -var sparcCode = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" -var sparcV9Code = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" -var xcoreCode = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10\x09\xfd\xec\xa7" +var basicM68KCode = "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28" +var basicTMS320C64XCode = "\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24" +var basicM680XCode = "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" +var basicEVMCode = "\x60\x61" + +var detailX86Code16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +var detailX86Code32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +var detailX86Code64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00" +var detailArmCode = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3" +var detailArmCode2 = "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3" +var detailThumbCode = "\x70\x47\xeb\x46\x83\xb0\xc9\x68" +var detailThumbCode2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0" +var detailThumbMClass = "\xef\xf3\x02\x80" +var detailArmV8 = "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" +var detailMipsCode = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08" +var detailMipsCode2 = "\x56\x34\x21\x34\xc2\x17\x01\x00" +var detailMips32R6M = "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" +var detailMips32R6 = "\xec\x80\x00\x19\x7c\x43\x22\xa0" +var detailArm64Code = "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c" +var detailPPCCode = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14" +var detailPPCCode2 = "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" +var detailSparcCode = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" +var detailSparcV9Code = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" +var detailSysZCode = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" +var detailXcoreCode = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" +var detailM68KCode = "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28" +var detailM680XCode = "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" var basicTests = platforms{ { @@ -153,6 +186,13 @@ var basicTests = platforms{ basicX86Code32, "X86 32 (Intel syntax)", }, + { + CS_ARCH_X86, + CS_MODE_32, + []option{{CS_OPT_SYNTAX, CS_OPT_SYNTAX_MASM}, {CS_OPT_DETAIL, CS_OPT_ON}}, + basicX86Code32, + "X86 32 (MASM syntax)", + }, { CS_ARCH_X86, CS_MODE_64, @@ -192,21 +232,21 @@ var basicTests = platforms{ CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - thumbMClass, + basicThumbMClass, "Thumb-MClass", }, platform{ CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - armV8, + basicArmV8, "Arm-V8", }, { CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - mipsCode, + basicMipsCode, "MIPS-32 (Big-endian)", }, { @@ -220,42 +260,52 @@ var basicTests = platforms{ CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicMips32R6, + basicMips32R6M, "MIPS-32R6 | Micro (Big-endian)", }, { CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - mips32R6, + basicMips32R6, "MIPS-32R6 (Big-endian)", }, - { + platform{ CS_ARCH_ARM64, CS_MODE_ARM, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicArm64Code2, + basicArm64Code, "ARM-64", }, - platform{ - CS_ARCH_PPC, - CS_MODE_BIG_ENDIAN, - []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicPPCCode2, - "PPC-64", - }, - platform{ - CS_ARCH_PPC, - CS_MODE_BIG_ENDIAN, - []option{{CS_OPT_DETAIL, CS_OPT_ON}, {CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME}}, - basicPPCCode2, - "PPC-64, print register with number only", - }, + /* + Temporarily disabled. See https://github.com/aquynh/capstone/pull/1361 + platform{ + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN, + []option{{CS_OPT_DETAIL, CS_OPT_ON}}, + basicPPCCode, + "PPC-64", + }, + platform{ + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN, + []option{{CS_OPT_DETAIL, CS_OPT_ON}, {CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME}}, + basicPPCCode, + "PPC-64, print register with number only", + }, + platform{ + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN + CS_MODE_QPX, + []option{{CS_OPT_DETAIL, CS_OPT_ON}}, + basicPPCCode2, + "PPC-64 + QPX", + }, + */ platform{ CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - sparcCode, + basicSparcCode, "Sparc", }, platform{ @@ -279,6 +329,34 @@ var basicTests = platforms{ basicXcoreCode, "XCore", }, + platform{ + CS_ARCH_M68K, + CS_MODE_BIG_ENDIAN + CS_MODE_M68K_040, + []option{{CS_OPT_DETAIL, CS_OPT_ON}}, + basicM68KCode, + "M68K", + }, + platform{ + CS_ARCH_TMS320C64X, + 0, + []option{}, + basicTMS320C64XCode, + "TMS320C64x", + }, + platform{ + CS_ARCH_M680X, + CS_MODE_M680X_6809, + []option{{CS_OPT_DETAIL, CS_OPT_ON}}, + basicM680XCode, + "M680X_M6809", + }, + platform{ + CS_ARCH_EVM, + 0, + []option{{CS_OPT_DETAIL, CS_OPT_ON}}, + basicEVMCode, + "EVM", + }, } // Honestly, these are _almost_ identical, but it's just easier to maintain @@ -289,142 +367,166 @@ var detailTests = platforms{ CS_ARCH_X86, CS_MODE_16, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicX86Code16, + detailX86Code16, "X86 16bit (Intel syntax)", }, { CS_ARCH_X86, CS_MODE_32, []option{{CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT}, {CS_OPT_DETAIL, CS_OPT_ON}}, - basicX86Code32, + detailX86Code32, "X86 32bit (ATT syntax)", }, { CS_ARCH_X86, CS_MODE_32, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicX86Code32, + detailX86Code32, "X86 32 (Intel syntax)", }, { CS_ARCH_X86, CS_MODE_64, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicX86Code64, + detailX86Code64, "X86 64 (Intel syntax)", }, { CS_ARCH_ARM, CS_MODE_ARM, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicArmCode, + detailArmCode, "ARM", }, { CS_ARCH_ARM, CS_MODE_THUMB, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicThumbCode2, + detailThumbCode2, "THUMB-2", }, { CS_ARCH_ARM, CS_MODE_ARM, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicArmCode2, + detailArmCode2, "ARM: Cortex-A15 + NEON", }, { CS_ARCH_ARM, CS_MODE_THUMB, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicThumbCode, + detailThumbCode, "THUMB", }, platform{ CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - thumbMClass, + detailThumbMClass, "Thumb-MClass", }, platform{ CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - armV8, + detailArmV8, "Arm-V8", }, { CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicMipsCode, + detailMipsCode, "MIPS-32 (Big-endian)", }, { CS_ARCH_MIPS, CS_MODE_64 + CS_MODE_LITTLE_ENDIAN, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicMipsCode2, + detailMipsCode2, "MIPS-64-EL (Little-endian)", }, { CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicMips32R6, + detailMips32R6M, "MIPS-32R6 | Micro (Big-endian)", }, { CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - mips32R6, + detailMips32R6, "MIPS-32R6 (Big-endian)", }, platform{ CS_ARCH_ARM64, CS_MODE_ARM, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - arm64Code, + detailArm64Code, "ARM-64", }, - platform{ - CS_ARCH_PPC, - CS_MODE_BIG_ENDIAN, - []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicPPCCode, - "PPC-64", - }, + /* + Temporarily disabled. See https://github.com/aquynh/capstone/pull/1361 + platform{ + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN, + []option{{CS_OPT_DETAIL, CS_OPT_ON}}, + detailPPCCode, + "PPC-64", + }, + platform{ + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN + CS_MODE_QPX, + []option{{CS_OPT_DETAIL, CS_OPT_ON}}, + detailPPCCode2, + "PPC-64 + QPX", + }, + */ platform{ CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicSparcCode, + detailSparcCode, "Sparc", }, platform{ CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicSparcV9Code, + detailSparcV9Code, "SparcV9", }, platform{ CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicSysZCode, + detailSysZCode, "SystemZ", }, platform{ CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicXcoreCode, + detailXcoreCode, "XCore", }, + platform{ + CS_ARCH_M68K, + CS_MODE_BIG_ENDIAN + CS_MODE_M68K_040, + []option{{CS_OPT_DETAIL, CS_OPT_ON}}, + detailM68KCode, + "M68K", + }, + platform{ + CS_ARCH_M680X, + CS_MODE_M680X_6809, + []option{{CS_OPT_DETAIL, CS_OPT_ON}}, + detailM680XCode, + "M680X_M6809", + }, } var armTests = platforms{ @@ -504,7 +606,7 @@ var mips_tests = platforms{ CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, []option{{CS_OPT_DETAIL, CS_OPT_ON}}, - basicMips32R6, + mips32R6M, "MIPS-32R6 | Micro (Big-endian)", }, { @@ -514,6 +616,20 @@ var mips_tests = platforms{ mips32R6, "MIPS-32R6 (Big-endian)", }, + { + CS_ARCH_MIPS, + CS_MODE_MIPS64 + CS_MODE_MIPS2 + CS_MODE_LITTLE_ENDIAN, + []option{{CS_OPT_DETAIL, CS_OPT_ON}}, + mips64SD, + "MIPS-64-EL + Mips II (Little-endian)", + }, + { + CS_ARCH_MIPS, + CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, + []option{{CS_OPT_DETAIL, CS_OPT_ON}}, + mips64SD, + "MIPS-64-EL (Little-endian)", + }, } var x86Tests = platforms{ @@ -555,6 +671,13 @@ var ppcTests = platforms{ ppcCode, "PPC-64", }, + platform{ + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN + CS_MODE_QPX, + []option{{CS_OPT_DETAIL, CS_OPT_ON}}, + ppcCode2, + "PPC-64 + QPX", + }, } var sysZTests = platforms{ diff --git a/test_test.go b/test_test.go index a2262dd..cc6ae79 100644 --- a/test_test.go +++ b/test_test.go @@ -68,7 +68,7 @@ func TestTest(t *testing.T) { } if fs := final.String(); string(spec) != fs { // Debugging - uncomment below and run the test | diff - test.SPEC - fmt.Println(fs) + // fmt.Println(fs) t.Errorf("Output failed to match spec!") } else { t.Logf("Clean diff with %v.\n", spec_file) diff --git a/travis_install_capstone_stable.sh b/travis_install_capstone_stable.sh index a3958fb..3902bd5 100755 --- a/travis_install_capstone_stable.sh +++ b/travis_install_capstone_stable.sh @@ -2,7 +2,7 @@ set -ex mkdir -p $HOME/src && cd $HOME/src -git clone --depth=50 --branch=3.0.4 https://github.com/aquynh/capstone.git && cd capstone +git clone --depth=50 --branch=4.0.1 https://github.com/aquynh/capstone.git && cd capstone echo `git log | head` PREFIX=$HOME/capstone make && PREFIX=$HOME/capstone make install cd $TRAVIS_BUILD_DIR \ No newline at end of file diff --git a/x86.SPEC b/x86.SPEC index 0097de8..18f9887 100644 --- a/x86.SPEC +++ b/x86.SPEC @@ -1,21 +1,28 @@ **************** Platform: X86 16bit (Intel syntax) -Code:0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x05 0x23 0x01 0x00 0x00 0x36 0x8b 0x84 0x91 0x23 0x01 0x00 0x00 0x41 0x8d 0x84 0x39 0x89 0x67 0x00 0x00 0x8d 0x87 0x89 0x67 0x00 0x00 0xb4 0xc6 +Code:0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x05 0x23 0x01 0x00 0x00 0x36 0x8b 0x84 0x91 0x23 0x01 0x00 0x00 0x41 0x8d 0x84 0x39 0x89 0x67 0x00 0x00 0x8d 0x87 0x89 0x67 0x00 0x00 0xb4 0xc6 0x66 0xe9 0xb8 0x00 0x00 0x00 0x67 0xff 0xa0 0x23 0x01 0x00 0x00 0x66 0xe8 0xcb 0x00 0x00 0x00 0x74 0xfc Disasm: -0x1000: lea cx, word ptr [si + 0x32] +0x1000: lea cx, [si + 0x32] Prefix:0x00 0x00 0x00 0x00 Opcode:0x8d 0x00 0x00 0x00 rex: 0x0 addr_size: 2 modrm: 0x4c + modrm_offset: 0x1 disp: 0x32 + disp_offset: 0x2 + disp_size: 0x1 op_count: 2 operands[0].type: REG = cx operands[0].size: 2 + operands[0].access: WRITE operands[1].type: MEM operands[1].mem.base: REG = si operands[1].mem.disp: 0x32 operands[1].size: 2 + operands[1].access: READ + Registers read: si + Registers modified: cx 0x1003: or byte ptr [bx + di], al Prefix:0x00 0x00 0x00 0x00 @@ -23,14 +30,20 @@ Disasm: rex: 0x0 addr_size: 2 modrm: 0x1 + modrm_offset: 0x1 disp: 0x0 op_count: 2 operands[0].type: MEM operands[0].mem.base: REG = bx operands[0].mem.index: REG = di operands[0].size: 1 + operands[0].access: READ | WRITE operands[1].type: REG = al operands[1].size: 1 + operands[1].access: READ + Registers read: bx di al + Registers modified: flags + EFLAGS: MOD_SF MOD_ZF MOD_PF RESET_OF RESET_CF UNDEF_AF 0x1005: fadd dword ptr [bx + di + 0x34c6] Prefix:0x00 0x00 0x00 0x00 @@ -38,13 +51,20 @@ Disasm: rex: 0x0 addr_size: 2 modrm: 0x81 + modrm_offset: 0x1 disp: 0x34c6 + disp_offset: 0x2 + disp_size: 0x2 op_count: 1 operands[0].type: MEM operands[0].mem.base: REG = bx operands[0].mem.index: REG = di operands[0].mem.disp: 0x34c6 operands[0].size: 4 + operands[0].access: READ + Registers read: bx di + Registers modified: fpsw + FPU_FLAGS: MOD_C1 UNDEF_C0 UNDEF_C2 UNDEF_C3 0x1009: adc al, byte ptr [bx + si] Prefix:0x00 0x00 0x00 0x00 @@ -52,14 +72,20 @@ Disasm: rex: 0x0 addr_size: 2 modrm: 0x0 + modrm_offset: 0x1 disp: 0x0 op_count: 2 operands[0].type: REG = al operands[0].size: 1 + operands[0].access: READ | WRITE operands[1].type: MEM operands[1].mem.base: REG = bx operands[1].mem.index: REG = si operands[1].size: 1 + operands[1].access: READ + Registers read: flags al bx si + Registers modified: flags al + EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF 0x100b: add byte ptr [di], al Prefix:0x00 0x00 0x00 0x00 @@ -67,13 +93,19 @@ Disasm: rex: 0x0 addr_size: 2 modrm: 0x5 + modrm_offset: 0x1 disp: 0x0 op_count: 2 operands[0].type: MEM operands[0].mem.base: REG = di operands[0].size: 1 + operands[0].access: READ | WRITE operands[1].type: REG = al operands[1].size: 1 + operands[1].access: READ + Registers read: di al + Registers modified: flags + EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF 0x100d: and ax, word ptr [bx + di] Prefix:0x00 0x00 0x00 0x00 @@ -81,14 +113,20 @@ Disasm: rex: 0x0 addr_size: 2 modrm: 0x1 + modrm_offset: 0x1 disp: 0x0 op_count: 2 operands[0].type: REG = ax operands[0].size: 2 + operands[0].access: READ | WRITE operands[1].type: MEM operands[1].mem.base: REG = bx operands[1].mem.index: REG = di operands[1].size: 2 + operands[1].access: READ + Registers read: ax bx di + Registers modified: flags ax + EFLAGS: MOD_SF MOD_ZF MOD_PF RESET_OF RESET_CF UNDEF_AF 0x100f: add byte ptr [bx + si], al Prefix:0x00 0x00 0x00 0x00 @@ -96,14 +134,20 @@ Disasm: rex: 0x0 addr_size: 2 modrm: 0x0 + modrm_offset: 0x1 disp: 0x0 op_count: 2 operands[0].type: MEM operands[0].mem.base: REG = bx operands[0].mem.index: REG = si operands[0].size: 1 + operands[0].access: READ | WRITE operands[1].type: REG = al operands[1].size: 1 + operands[1].access: READ + Registers read: bx si al + Registers modified: flags + EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF 0x1011: mov ax, word ptr ss:[si + 0x2391] Prefix:0x00 0x36 0x00 0x00 @@ -111,15 +155,22 @@ Disasm: rex: 0x0 addr_size: 2 modrm: 0x84 + modrm_offset: 0x2 disp: 0x2391 + disp_offset: 0x3 + disp_size: 0x2 op_count: 2 operands[0].type: REG = ax operands[0].size: 2 + operands[0].access: WRITE operands[1].type: MEM operands[1].mem.segment: REG = ss operands[1].mem.base: REG = si operands[1].mem.disp: 0x2391 operands[1].size: 2 + operands[1].access: READ + Registers read: ss si + Registers modified: ax 0x1016: add word ptr [bx + si], ax Prefix:0x00 0x00 0x00 0x00 @@ -127,14 +178,20 @@ Disasm: rex: 0x0 addr_size: 2 modrm: 0x0 + modrm_offset: 0x1 disp: 0x0 op_count: 2 operands[0].type: MEM operands[0].mem.base: REG = bx operands[0].mem.index: REG = si operands[0].size: 2 + operands[0].access: READ | WRITE operands[1].type: REG = ax operands[1].size: 2 + operands[1].access: READ + Registers read: bx si ax + Registers modified: flags + EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF 0x1018: add byte ptr [bx + di - 0x73], al Prefix:0x00 0x00 0x00 0x00 @@ -142,15 +199,23 @@ Disasm: rex: 0x0 addr_size: 2 modrm: 0x41 - disp: 0xffffff8d + modrm_offset: 0x1 + disp: 0xffffffffffffff8d + disp_offset: 0x2 + disp_size: 0x1 op_count: 2 operands[0].type: MEM operands[0].mem.base: REG = bx operands[0].mem.index: REG = di operands[0].mem.disp: 0xffffffffffffff8d operands[0].size: 1 + operands[0].access: READ | WRITE operands[1].type: REG = al operands[1].size: 1 + operands[1].access: READ + Registers read: bx di al + Registers modified: flags + EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF 0x101b: test byte ptr [bx + di], bh Prefix:0x00 0x00 0x00 0x00 @@ -158,14 +223,20 @@ Disasm: rex: 0x0 addr_size: 2 modrm: 0x39 + modrm_offset: 0x1 disp: 0x0 op_count: 2 operands[0].type: MEM operands[0].mem.base: REG = bx operands[0].mem.index: REG = di operands[0].size: 1 + operands[0].access: READ operands[1].type: REG = bh operands[1].size: 1 + operands[1].access: READ + Registers read: bx di bh + Registers modified: flags + EFLAGS: MOD_SF MOD_ZF MOD_PF RESET_OF RESET_CF UNDEF_AF 0x101d: mov word ptr [bx], sp Prefix:0x00 0x00 0x00 0x00 @@ -173,13 +244,19 @@ Disasm: rex: 0x0 addr_size: 2 modrm: 0x67 + modrm_offset: 0x1 disp: 0x0 + disp_offset: 0x2 + disp_size: 0x1 op_count: 2 operands[0].type: MEM operands[0].mem.base: REG = bx operands[0].size: 2 + operands[0].access: WRITE operands[1].type: REG = sp operands[1].size: 2 + operands[1].access: READ + Registers read: bx sp 0x1020: add byte ptr [di - 0x7679], cl Prefix:0x00 0x00 0x00 0x00 @@ -187,14 +264,22 @@ Disasm: rex: 0x0 addr_size: 2 modrm: 0x8d - disp: 0xffff8987 + modrm_offset: 0x1 + disp: 0xffffffffffff8987 + disp_offset: 0x2 + disp_size: 0x2 op_count: 2 operands[0].type: MEM operands[0].mem.base: REG = di operands[0].mem.disp: 0xffffffffffff8987 operands[0].size: 1 + operands[0].access: READ | WRITE operands[1].type: REG = cl operands[1].size: 1 + operands[1].access: READ + Registers read: di cl + Registers modified: flags + EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF 0x1024: add byte ptr [eax], al Prefix:0x00 0x00 0x00 0x67 @@ -202,13 +287,19 @@ Disasm: rex: 0x0 addr_size: 4 modrm: 0x0 + modrm_offset: 0x2 disp: 0x0 op_count: 2 operands[0].type: MEM operands[0].mem.base: REG = eax operands[0].size: 1 + operands[0].access: READ | WRITE operands[1].type: REG = al operands[1].size: 1 + operands[1].access: READ + Registers read: eax al + Registers modified: flags + EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF 0x1027: mov ah, 0xc6 Prefix:0x00 0x00 0x00 0x00 @@ -219,17 +310,87 @@ Disasm: disp: 0x0 imm_count: 1 imms[1]: 0xc6 + imm_offset: 0x1 + imm_size: 0x1 op_count: 2 operands[0].type: REG = ah operands[0].size: 1 + operands[0].access: WRITE operands[1].type: IMM = 0xc6 operands[1].size: 1 + Registers modified: ah -0x1029: +0x1029: jmp 0x10e7 + Prefix:0x00 0x00 0x66 0x00 + Opcode:0xe9 0x00 0x00 0x00 + rex: 0x0 + addr_size: 2 + modrm: 0x0 + disp: 0x0 + imm_count: 1 + imms[1]: 0x10e7 + imm_offset: 0x2 + imm_size: 0x4 + op_count: 1 + operands[0].type: IMM = 0x10e7 + operands[0].size: 4 + +0x102f: jmp word ptr [eax + 0x123] + Prefix:0x00 0x00 0x00 0x67 + Opcode:0xff 0x00 0x00 0x00 + rex: 0x0 + addr_size: 4 + modrm: 0xa0 + modrm_offset: 0x2 + disp: 0x123 + disp_offset: 0x3 + disp_size: 0x4 + op_count: 1 + operands[0].type: MEM + operands[0].mem.base: REG = eax + operands[0].mem.disp: 0x123 + operands[0].size: 2 + Registers read: eax + +0x1036: call 0x1107 + Prefix:0x00 0x00 0x66 0x00 + Opcode:0xe8 0x00 0x00 0x00 + rex: 0x0 + addr_size: 2 + modrm: 0x0 + disp: 0x0 + imm_count: 1 + imms[1]: 0x1107 + imm_offset: 0x2 + imm_size: 0x4 + op_count: 1 + operands[0].type: IMM = 0x1107 + operands[0].size: 4 + Registers read: esp eip + Registers modified: esp + +0x103c: je 0x103a + Prefix:0x00 0x00 0x00 0x00 + Opcode:0x74 0x00 0x00 0x00 + rex: 0x0 + addr_size: 2 + modrm: 0x0 + disp: 0x0 + imm_count: 1 + imms[1]: 0x103a + imm_offset: 0x1 + imm_size: 0x1 + op_count: 1 + operands[0].type: IMM = 0x103a + operands[0].size: 2 + Registers read: flags + EFLAGS: TEST_ZF + +0x103e: **************** Platform: X86 32 (AT&T syntax) -Code:0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x05 0x23 0x01 0x00 0x00 0x36 0x8b 0x84 0x91 0x23 0x01 0x00 0x00 0x41 0x8d 0x84 0x39 0x89 0x67 0x00 0x00 0x8d 0x87 0x89 0x67 0x00 0x00 0xb4 0xc6 +Code:0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x05 0x23 0x01 0x00 0x00 0x36 0x8b 0x84 0x91 0x23 0x01 0x00 0x00 0x41 0x8d 0x84 0x39 0x89 0x67 0x00 0x00 0x8d 0x87 0x89 0x67 0x00 0x00 0xb4 0xc6 0xe9 0xea 0xbe 0xad 0xde 0xff 0xa0 0x23 0x01 0x00 0x00 0xe8 0xdf 0xbe 0xad 0xde 0x74 0xff Disasm: 0x1000: leal 8(%edx, %esi), %ecx Prefix:0x00 0x00 0x00 0x00 @@ -237,7 +398,10 @@ Disasm: rex: 0x0 addr_size: 4 modrm: 0x4c + modrm_offset: 0x1 disp: 0x8 + disp_offset: 0x3 + disp_size: 0x1 sib: 0x32 sib_base: edx sib_index: esi @@ -248,8 +412,12 @@ Disasm: operands[0].mem.index: REG = esi operands[0].mem.disp: 0x8 operands[0].size: 4 + operands[0].access: READ operands[1].type: REG = ecx operands[1].size: 4 + operands[1].access: WRITE + Registers read: edx esi + Registers modified: ecx 0x1004: addl %ebx, %eax Prefix:0x00 0x00 0x00 0x00 @@ -257,13 +425,19 @@ Disasm: rex: 0x0 addr_size: 4 modrm: 0xd8 + modrm_offset: 0x1 disp: 0x0 sib: 0x0 op_count: 2 operands[0].type: REG = ebx operands[0].size: 4 + operands[0].access: READ operands[1].type: REG = eax operands[1].size: 4 + operands[1].access: READ | WRITE + Registers read: ebx eax + Registers modified: eflags eax + EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF 0x1006: addl $0x1234, %esi Prefix:0x00 0x00 0x00 0x00 @@ -271,15 +445,22 @@ Disasm: rex: 0x0 addr_size: 4 modrm: 0xc6 + modrm_offset: 0x1 disp: 0x0 sib: 0x0 imm_count: 1 imms[1]: 0x1234 + imm_offset: 0x2 + imm_size: 0x4 op_count: 2 operands[0].type: IMM = 0x1234 operands[0].size: 4 operands[1].type: REG = esi operands[1].size: 4 + operands[1].access: READ | WRITE + Registers read: esi + Registers modified: eflags esi + EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF 0x100c: addl $0x123, %eax Prefix:0x00 0x00 0x00 0x00 @@ -291,11 +472,17 @@ Disasm: sib: 0x0 imm_count: 1 imms[1]: 0x123 + imm_offset: 0x1 + imm_size: 0x4 op_count: 2 operands[0].type: IMM = 0x123 operands[0].size: 4 operands[1].type: REG = eax operands[1].size: 4 + operands[1].access: READ | WRITE + Registers read: eax + Registers modified: eflags eax + EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF 0x1011: movl %ss:0x123(%ecx, %edx, 4), %eax Prefix:0x00 0x36 0x00 0x00 @@ -303,7 +490,10 @@ Disasm: rex: 0x0 addr_size: 4 modrm: 0x84 + modrm_offset: 0x2 disp: 0x123 + disp_offset: 0x4 + disp_size: 0x4 sib: 0x91 sib_base: ecx sib_index: edx @@ -316,8 +506,12 @@ Disasm: operands[0].mem.scale: 4 operands[0].mem.disp: 0x123 operands[0].size: 4 + operands[0].access: READ operands[1].type: REG = eax operands[1].size: 4 + operands[1].access: WRITE + Registers read: ss ecx edx + Registers modified: eax 0x1019: incl %ecx Prefix:0x00 0x00 0x00 0x00 @@ -330,6 +524,10 @@ Disasm: op_count: 1 operands[0].type: REG = ecx operands[0].size: 4 + operands[0].access: READ | WRITE + Registers read: ecx + Registers modified: eflags ecx + EFLAGS: MOD_AF MOD_SF MOD_ZF MOD_PF MOD_OF 0x101a: leal 0x6789(%ecx, %edi), %eax Prefix:0x00 0x00 0x00 0x00 @@ -337,7 +535,10 @@ Disasm: rex: 0x0 addr_size: 4 modrm: 0x84 + modrm_offset: 0x1 disp: 0x6789 + disp_offset: 0x3 + disp_size: 0x4 sib: 0x39 sib_base: ecx sib_index: edi @@ -348,8 +549,12 @@ Disasm: operands[0].mem.index: REG = edi operands[0].mem.disp: 0x6789 operands[0].size: 4 + operands[0].access: READ operands[1].type: REG = eax operands[1].size: 4 + operands[1].access: WRITE + Registers read: ecx edi + Registers modified: eax 0x1021: leal 0x6789(%edi), %eax Prefix:0x00 0x00 0x00 0x00 @@ -357,15 +562,22 @@ Disasm: rex: 0x0 addr_size: 4 modrm: 0x87 + modrm_offset: 0x1 disp: 0x6789 + disp_offset: 0x2 + disp_size: 0x4 sib: 0x0 op_count: 2 operands[0].type: MEM operands[0].mem.base: REG = edi operands[0].mem.disp: 0x6789 operands[0].size: 4 + operands[0].access: READ operands[1].type: REG = eax operands[1].size: 4 + operands[1].access: WRITE + Registers read: edi + Registers modified: eax 0x1027: movb $0xc6, %ah Prefix:0x00 0x00 0x00 0x00 @@ -377,25 +589,102 @@ Disasm: sib: 0x0 imm_count: 1 imms[1]: 0xc6 + imm_offset: 0x1 + imm_size: 0x1 op_count: 2 operands[0].type: IMM = 0xc6 operands[0].size: 1 operands[1].type: REG = ah operands[1].size: 1 + operands[1].access: WRITE + Registers modified: ah -0x1029: +0x1029: jmp 0xdeadcf18 + Prefix:0x00 0x00 0x00 0x00 + Opcode:0xe9 0x00 0x00 0x00 + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + imm_count: 1 + imms[1]: 0xdeadcf18 + imm_offset: 0x1 + imm_size: 0x4 + op_count: 1 + operands[0].type: IMM = 0xdeadcf18 + operands[0].size: 4 + +0x102e: jmpl *0x123(%eax) + Prefix:0x00 0x00 0x00 0x00 + Opcode:0xff 0x00 0x00 0x00 + rex: 0x0 + addr_size: 4 + modrm: 0xa0 + modrm_offset: 0x1 + disp: 0x123 + disp_offset: 0x2 + disp_size: 0x4 + sib: 0x0 + op_count: 1 + operands[0].type: MEM + operands[0].mem.base: REG = eax + operands[0].mem.disp: 0x123 + operands[0].size: 4 + Registers read: eax + +0x1034: calll 0xdeadcf18 + Prefix:0x00 0x00 0x00 0x00 + Opcode:0xe8 0x00 0x00 0x00 + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + imm_count: 1 + imms[1]: 0xdeadcf18 + imm_offset: 0x1 + imm_size: 0x4 + op_count: 1 + operands[0].type: IMM = 0xdeadcf18 + operands[0].size: 4 + Registers read: esp eip + Registers modified: esp + +0x1039: je 0x103a + Prefix:0x00 0x00 0x00 0x00 + Opcode:0x74 0x00 0x00 0x00 + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + imm_count: 1 + imms[1]: 0x103a + imm_offset: 0x1 + imm_size: 0x1 + op_count: 1 + operands[0].type: IMM = 0x103a + operands[0].size: 4 + Registers read: eflags + EFLAGS: TEST_ZF + +0x103b: **************** Platform: X86 32 (Intel syntax) -Code:0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x05 0x23 0x01 0x00 0x00 0x36 0x8b 0x84 0x91 0x23 0x01 0x00 0x00 0x41 0x8d 0x84 0x39 0x89 0x67 0x00 0x00 0x8d 0x87 0x89 0x67 0x00 0x00 0xb4 0xc6 +Code:0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x05 0x23 0x01 0x00 0x00 0x36 0x8b 0x84 0x91 0x23 0x01 0x00 0x00 0x41 0x8d 0x84 0x39 0x89 0x67 0x00 0x00 0x8d 0x87 0x89 0x67 0x00 0x00 0xb4 0xc6 0xe9 0xea 0xbe 0xad 0xde 0xff 0xa0 0x23 0x01 0x00 0x00 0xe8 0xdf 0xbe 0xad 0xde 0x74 0xff Disasm: -0x1000: lea ecx, dword ptr [edx + esi + 8] +0x1000: lea ecx, [edx + esi + 8] Prefix:0x00 0x00 0x00 0x00 Opcode:0x8d 0x00 0x00 0x00 rex: 0x0 addr_size: 4 modrm: 0x4c + modrm_offset: 0x1 disp: 0x8 + disp_offset: 0x3 + disp_size: 0x1 sib: 0x32 sib_base: edx sib_index: esi @@ -403,11 +692,15 @@ Disasm: op_count: 2 operands[0].type: REG = ecx operands[0].size: 4 + operands[0].access: WRITE operands[1].type: MEM operands[1].mem.base: REG = edx operands[1].mem.index: REG = esi operands[1].mem.disp: 0x8 operands[1].size: 4 + operands[1].access: READ + Registers read: edx esi + Registers modified: ecx 0x1004: add eax, ebx Prefix:0x00 0x00 0x00 0x00 @@ -415,13 +708,19 @@ Disasm: rex: 0x0 addr_size: 4 modrm: 0xd8 + modrm_offset: 0x1 disp: 0x0 sib: 0x0 op_count: 2 operands[0].type: REG = eax operands[0].size: 4 + operands[0].access: READ | WRITE operands[1].type: REG = ebx operands[1].size: 4 + operands[1].access: READ + Registers read: eax ebx + Registers modified: eflags eax + EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF 0x1006: add esi, 0x1234 Prefix:0x00 0x00 0x00 0x00 @@ -429,15 +728,22 @@ Disasm: rex: 0x0 addr_size: 4 modrm: 0xc6 + modrm_offset: 0x1 disp: 0x0 sib: 0x0 imm_count: 1 imms[1]: 0x1234 + imm_offset: 0x2 + imm_size: 0x4 op_count: 2 operands[0].type: REG = esi operands[0].size: 4 + operands[0].access: READ | WRITE operands[1].type: IMM = 0x1234 operands[1].size: 4 + Registers read: esi + Registers modified: eflags esi + EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF 0x100c: add eax, 0x123 Prefix:0x00 0x00 0x00 0x00 @@ -449,11 +755,17 @@ Disasm: sib: 0x0 imm_count: 1 imms[1]: 0x123 + imm_offset: 0x1 + imm_size: 0x4 op_count: 2 operands[0].type: REG = eax operands[0].size: 4 + operands[0].access: READ | WRITE operands[1].type: IMM = 0x123 operands[1].size: 4 + Registers read: eax + Registers modified: eflags eax + EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF 0x1011: mov eax, dword ptr ss:[ecx + edx*4 + 0x123] Prefix:0x00 0x36 0x00 0x00 @@ -461,7 +773,10 @@ Disasm: rex: 0x0 addr_size: 4 modrm: 0x84 + modrm_offset: 0x2 disp: 0x123 + disp_offset: 0x4 + disp_size: 0x4 sib: 0x91 sib_base: ecx sib_index: edx @@ -469,6 +784,7 @@ Disasm: op_count: 2 operands[0].type: REG = eax operands[0].size: 4 + operands[0].access: WRITE operands[1].type: MEM operands[1].mem.segment: REG = ss operands[1].mem.base: REG = ecx @@ -476,6 +792,9 @@ Disasm: operands[1].mem.scale: 4 operands[1].mem.disp: 0x123 operands[1].size: 4 + operands[1].access: READ + Registers read: ss ecx edx + Registers modified: eax 0x1019: inc ecx Prefix:0x00 0x00 0x00 0x00 @@ -488,14 +807,21 @@ Disasm: op_count: 1 operands[0].type: REG = ecx operands[0].size: 4 + operands[0].access: READ | WRITE + Registers read: ecx + Registers modified: eflags ecx + EFLAGS: MOD_AF MOD_SF MOD_ZF MOD_PF MOD_OF -0x101a: lea eax, dword ptr [ecx + edi + 0x6789] +0x101a: lea eax, [ecx + edi + 0x6789] Prefix:0x00 0x00 0x00 0x00 Opcode:0x8d 0x00 0x00 0x00 rex: 0x0 addr_size: 4 modrm: 0x84 + modrm_offset: 0x1 disp: 0x6789 + disp_offset: 0x3 + disp_size: 0x4 sib: 0x39 sib_base: ecx sib_index: edi @@ -503,27 +829,38 @@ Disasm: op_count: 2 operands[0].type: REG = eax operands[0].size: 4 + operands[0].access: WRITE operands[1].type: MEM operands[1].mem.base: REG = ecx operands[1].mem.index: REG = edi operands[1].mem.disp: 0x6789 operands[1].size: 4 + operands[1].access: READ + Registers read: ecx edi + Registers modified: eax -0x1021: lea eax, dword ptr [edi + 0x6789] +0x1021: lea eax, [edi + 0x6789] Prefix:0x00 0x00 0x00 0x00 Opcode:0x8d 0x00 0x00 0x00 rex: 0x0 addr_size: 4 modrm: 0x87 + modrm_offset: 0x1 disp: 0x6789 + disp_offset: 0x2 + disp_size: 0x4 sib: 0x0 op_count: 2 operands[0].type: REG = eax operands[0].size: 4 + operands[0].access: WRITE operands[1].type: MEM operands[1].mem.base: REG = edi operands[1].mem.disp: 0x6789 operands[1].size: 4 + operands[1].access: READ + Registers read: edi + Registers modified: eax 0x1027: mov ah, 0xc6 Prefix:0x00 0x00 0x00 0x00 @@ -535,17 +872,91 @@ Disasm: sib: 0x0 imm_count: 1 imms[1]: 0xc6 + imm_offset: 0x1 + imm_size: 0x1 op_count: 2 operands[0].type: REG = ah operands[0].size: 1 + operands[0].access: WRITE operands[1].type: IMM = 0xc6 operands[1].size: 1 + Registers modified: ah -0x1029: +0x1029: jmp 0xdeadcf18 + Prefix:0x00 0x00 0x00 0x00 + Opcode:0xe9 0x00 0x00 0x00 + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + imm_count: 1 + imms[1]: 0xdeadcf18 + imm_offset: 0x1 + imm_size: 0x4 + op_count: 1 + operands[0].type: IMM = 0xdeadcf18 + operands[0].size: 4 + +0x102e: jmp dword ptr [eax + 0x123] + Prefix:0x00 0x00 0x00 0x00 + Opcode:0xff 0x00 0x00 0x00 + rex: 0x0 + addr_size: 4 + modrm: 0xa0 + modrm_offset: 0x1 + disp: 0x123 + disp_offset: 0x2 + disp_size: 0x4 + sib: 0x0 + op_count: 1 + operands[0].type: MEM + operands[0].mem.base: REG = eax + operands[0].mem.disp: 0x123 + operands[0].size: 4 + Registers read: eax + +0x1034: call 0xdeadcf18 + Prefix:0x00 0x00 0x00 0x00 + Opcode:0xe8 0x00 0x00 0x00 + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + imm_count: 1 + imms[1]: 0xdeadcf18 + imm_offset: 0x1 + imm_size: 0x4 + op_count: 1 + operands[0].type: IMM = 0xdeadcf18 + operands[0].size: 4 + Registers read: esp eip + Registers modified: esp + +0x1039: je 0x103a + Prefix:0x00 0x00 0x00 0x00 + Opcode:0x74 0x00 0x00 0x00 + rex: 0x0 + addr_size: 4 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + imm_count: 1 + imms[1]: 0x103a + imm_offset: 0x1 + imm_size: 0x1 + op_count: 1 + operands[0].type: IMM = 0x103a + operands[0].size: 4 + Registers read: eflags + EFLAGS: TEST_ZF + +0x103b: **************** Platform: X86 64 (Intel syntax) -Code:0x55 0x48 0x8b 0x05 0xb8 0x13 0x00 0x00 +Code:0x55 0x48 0x8b 0x05 0xb8 0x13 0x00 0x00 0xe9 0xea 0xbe 0xad 0xde 0xff 0x25 0x23 0x01 0x00 0x00 0xe8 0xdf 0xbe 0xad 0xde 0x74 0xff Disasm: 0x1000: push rbp Prefix:0x00 0x00 0x00 0x00 @@ -558,6 +969,9 @@ Disasm: op_count: 1 operands[0].type: REG = rbp operands[0].size: 8 + operands[0].access: READ + Registers read: rsp rbp + Registers modified: rsp 0x1001: mov rax, qword ptr [rip + 0x13b8] Prefix:0x00 0x00 0x00 0x00 @@ -565,15 +979,92 @@ Disasm: rex: 0x48 addr_size: 8 modrm: 0x5 + modrm_offset: 0x2 disp: 0x13b8 + disp_offset: 0x3 + disp_size: 0x4 sib: 0x0 op_count: 2 operands[0].type: REG = rax operands[0].size: 8 + operands[0].access: WRITE operands[1].type: MEM operands[1].mem.base: REG = rip operands[1].mem.disp: 0x13b8 operands[1].size: 8 + operands[1].access: READ + Registers read: rip + Registers modified: rax + +0x1008: jmp 0xffffffffdeadcef7 + Prefix:0x00 0x00 0x00 0x00 + Opcode:0xe9 0x00 0x00 0x00 + rex: 0x0 + addr_size: 8 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + imm_count: 1 + imms[1]: 0xffffffffdeadcef7 + imm_offset: 0x1 + imm_size: 0x4 + op_count: 1 + operands[0].type: IMM = 0xffffffffdeadcef7 + operands[0].size: 8 + +0x100d: jmp qword ptr [rip + 0x123] + Prefix:0x00 0x00 0x00 0x00 + Opcode:0xff 0x00 0x00 0x00 + rex: 0x0 + addr_size: 8 + modrm: 0x25 + modrm_offset: 0x1 + disp: 0x123 + disp_offset: 0x2 + disp_size: 0x4 + sib: 0x0 + op_count: 1 + operands[0].type: MEM + operands[0].mem.base: REG = rip + operands[0].mem.disp: 0x123 + operands[0].size: 8 + Registers read: rip + +0x1013: call 0xffffffffdeadcef7 + Prefix:0x00 0x00 0x00 0x00 + Opcode:0xe8 0x00 0x00 0x00 + rex: 0x0 + addr_size: 8 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + imm_count: 1 + imms[1]: 0xffffffffdeadcef7 + imm_offset: 0x1 + imm_size: 0x4 + op_count: 1 + operands[0].type: IMM = 0xffffffffdeadcef7 + operands[0].size: 8 + Registers read: rsp rip + Registers modified: rsp + +0x1018: je 0x1019 + Prefix:0x00 0x00 0x00 0x00 + Opcode:0x74 0x00 0x00 0x00 + rex: 0x0 + addr_size: 8 + modrm: 0x0 + disp: 0x0 + sib: 0x0 + imm_count: 1 + imms[1]: 0x1019 + imm_offset: 0x1 + imm_size: 0x1 + op_count: 1 + operands[0].type: IMM = 0x1019 + operands[0].size: 8 + Registers read: rflags + EFLAGS: TEST_ZF -0x1008: +0x101a: diff --git a/x86_constants.go b/x86_constants.go index ea1077f..cb70ba6 100644 --- a/x86_constants.go +++ b/x86_constants.go @@ -8,8 +8,8 @@ try reading the *_test.go files. (c) 2013 COSEINC. All Rights Reserved. THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT! - Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/ - 2016-04-13T12:04:37+09:30 + Command: ./genconst /Users/scottknight/work/capstone/bindings/python/capstone/ + 2019-02-02T13:26:27-05:00 */ @@ -99,6 +99,14 @@ const ( X86_REG_DR5 = C.X86_REG_DR5 X86_REG_DR6 = C.X86_REG_DR6 X86_REG_DR7 = C.X86_REG_DR7 + X86_REG_DR8 = C.X86_REG_DR8 + X86_REG_DR9 = C.X86_REG_DR9 + X86_REG_DR10 = C.X86_REG_DR10 + X86_REG_DR11 = C.X86_REG_DR11 + X86_REG_DR12 = C.X86_REG_DR12 + X86_REG_DR13 = C.X86_REG_DR13 + X86_REG_DR14 = C.X86_REG_DR14 + X86_REG_DR15 = C.X86_REG_DR15 X86_REG_FP0 = C.X86_REG_FP0 X86_REG_FP1 = C.X86_REG_FP1 X86_REG_FP2 = C.X86_REG_FP2 @@ -262,13 +270,108 @@ const ( X86_REG_ENDING = C.X86_REG_ENDING ) +// Sub-flags of EFLAGS +const ( + X86_EFLAGS_MODIFY_AF = C.X86_EFLAGS_MODIFY_AF + X86_EFLAGS_MODIFY_CF = C.X86_EFLAGS_MODIFY_CF + X86_EFLAGS_MODIFY_SF = C.X86_EFLAGS_MODIFY_SF + X86_EFLAGS_MODIFY_ZF = C.X86_EFLAGS_MODIFY_ZF + X86_EFLAGS_MODIFY_PF = C.X86_EFLAGS_MODIFY_PF + X86_EFLAGS_MODIFY_OF = C.X86_EFLAGS_MODIFY_OF + X86_EFLAGS_MODIFY_TF = C.X86_EFLAGS_MODIFY_TF + X86_EFLAGS_MODIFY_IF = C.X86_EFLAGS_MODIFY_IF + X86_EFLAGS_MODIFY_DF = C.X86_EFLAGS_MODIFY_DF + X86_EFLAGS_MODIFY_NT = C.X86_EFLAGS_MODIFY_NT + X86_EFLAGS_MODIFY_RF = C.X86_EFLAGS_MODIFY_RF + X86_EFLAGS_PRIOR_OF = C.X86_EFLAGS_PRIOR_OF + X86_EFLAGS_PRIOR_SF = C.X86_EFLAGS_PRIOR_SF + X86_EFLAGS_PRIOR_ZF = C.X86_EFLAGS_PRIOR_ZF + X86_EFLAGS_PRIOR_AF = C.X86_EFLAGS_PRIOR_AF + X86_EFLAGS_PRIOR_PF = C.X86_EFLAGS_PRIOR_PF + X86_EFLAGS_PRIOR_CF = C.X86_EFLAGS_PRIOR_CF + X86_EFLAGS_PRIOR_TF = C.X86_EFLAGS_PRIOR_TF + X86_EFLAGS_PRIOR_IF = C.X86_EFLAGS_PRIOR_IF + X86_EFLAGS_PRIOR_DF = C.X86_EFLAGS_PRIOR_DF + X86_EFLAGS_PRIOR_NT = C.X86_EFLAGS_PRIOR_NT + X86_EFLAGS_RESET_OF = C.X86_EFLAGS_RESET_OF + X86_EFLAGS_RESET_CF = C.X86_EFLAGS_RESET_CF + X86_EFLAGS_RESET_DF = C.X86_EFLAGS_RESET_DF + X86_EFLAGS_RESET_IF = C.X86_EFLAGS_RESET_IF + X86_EFLAGS_RESET_SF = C.X86_EFLAGS_RESET_SF + X86_EFLAGS_RESET_AF = C.X86_EFLAGS_RESET_AF + X86_EFLAGS_RESET_TF = C.X86_EFLAGS_RESET_TF + X86_EFLAGS_RESET_NT = C.X86_EFLAGS_RESET_NT + X86_EFLAGS_RESET_PF = C.X86_EFLAGS_RESET_PF + X86_EFLAGS_SET_CF = C.X86_EFLAGS_SET_CF + X86_EFLAGS_SET_DF = C.X86_EFLAGS_SET_DF + X86_EFLAGS_SET_IF = C.X86_EFLAGS_SET_IF + X86_EFLAGS_TEST_OF = C.X86_EFLAGS_TEST_OF + X86_EFLAGS_TEST_SF = C.X86_EFLAGS_TEST_SF + X86_EFLAGS_TEST_ZF = C.X86_EFLAGS_TEST_ZF + X86_EFLAGS_TEST_PF = C.X86_EFLAGS_TEST_PF + X86_EFLAGS_TEST_CF = C.X86_EFLAGS_TEST_CF + X86_EFLAGS_TEST_NT = C.X86_EFLAGS_TEST_NT + X86_EFLAGS_TEST_DF = C.X86_EFLAGS_TEST_DF + X86_EFLAGS_UNDEFINED_OF = C.X86_EFLAGS_UNDEFINED_OF + X86_EFLAGS_UNDEFINED_SF = C.X86_EFLAGS_UNDEFINED_SF + X86_EFLAGS_UNDEFINED_ZF = C.X86_EFLAGS_UNDEFINED_ZF + X86_EFLAGS_UNDEFINED_PF = C.X86_EFLAGS_UNDEFINED_PF + X86_EFLAGS_UNDEFINED_AF = C.X86_EFLAGS_UNDEFINED_AF + X86_EFLAGS_UNDEFINED_CF = C.X86_EFLAGS_UNDEFINED_CF + X86_EFLAGS_RESET_RF = C.X86_EFLAGS_RESET_RF + X86_EFLAGS_TEST_RF = C.X86_EFLAGS_TEST_RF + X86_EFLAGS_TEST_IF = C.X86_EFLAGS_TEST_IF + X86_EFLAGS_TEST_TF = C.X86_EFLAGS_TEST_TF + X86_EFLAGS_TEST_AF = C.X86_EFLAGS_TEST_AF + X86_EFLAGS_RESET_ZF = C.X86_EFLAGS_RESET_ZF + X86_EFLAGS_SET_OF = C.X86_EFLAGS_SET_OF + X86_EFLAGS_SET_SF = C.X86_EFLAGS_SET_SF + X86_EFLAGS_SET_ZF = C.X86_EFLAGS_SET_ZF + X86_EFLAGS_SET_AF = C.X86_EFLAGS_SET_AF + X86_EFLAGS_SET_PF = C.X86_EFLAGS_SET_PF + X86_EFLAGS_RESET_0F = C.X86_EFLAGS_RESET_0F + X86_EFLAGS_RESET_AC = C.X86_EFLAGS_RESET_AC + X86_FPU_FLAGS_MODIFY_C0 = C.X86_FPU_FLAGS_MODIFY_C0 + X86_FPU_FLAGS_MODIFY_C1 = C.X86_FPU_FLAGS_MODIFY_C1 + X86_FPU_FLAGS_MODIFY_C2 = C.X86_FPU_FLAGS_MODIFY_C2 + X86_FPU_FLAGS_MODIFY_C3 = C.X86_FPU_FLAGS_MODIFY_C3 + X86_FPU_FLAGS_RESET_C0 = C.X86_FPU_FLAGS_RESET_C0 + X86_FPU_FLAGS_RESET_C1 = C.X86_FPU_FLAGS_RESET_C1 + X86_FPU_FLAGS_RESET_C2 = C.X86_FPU_FLAGS_RESET_C2 + X86_FPU_FLAGS_RESET_C3 = C.X86_FPU_FLAGS_RESET_C3 + X86_FPU_FLAGS_SET_C0 = C.X86_FPU_FLAGS_SET_C0 + X86_FPU_FLAGS_SET_C1 = C.X86_FPU_FLAGS_SET_C1 + X86_FPU_FLAGS_SET_C2 = C.X86_FPU_FLAGS_SET_C2 + X86_FPU_FLAGS_SET_C3 = C.X86_FPU_FLAGS_SET_C3 + X86_FPU_FLAGS_UNDEFINED_C0 = C.X86_FPU_FLAGS_UNDEFINED_C0 + X86_FPU_FLAGS_UNDEFINED_C1 = C.X86_FPU_FLAGS_UNDEFINED_C1 + X86_FPU_FLAGS_UNDEFINED_C2 = C.X86_FPU_FLAGS_UNDEFINED_C2 + X86_FPU_FLAGS_UNDEFINED_C3 = C.X86_FPU_FLAGS_UNDEFINED_C3 + X86_FPU_FLAGS_TEST_C0 = C.X86_FPU_FLAGS_TEST_C0 + X86_FPU_FLAGS_TEST_C1 = C.X86_FPU_FLAGS_TEST_C1 + X86_FPU_FLAGS_TEST_C2 = C.X86_FPU_FLAGS_TEST_C2 + X86_FPU_FLAGS_TEST_C3 = C.X86_FPU_FLAGS_TEST_C3 +) + // Operand type for instruction's operands const ( X86_OP_INVALID = C.X86_OP_INVALID X86_OP_REG = C.X86_OP_REG X86_OP_IMM = C.X86_OP_IMM X86_OP_MEM = C.X86_OP_MEM - X86_OP_FP = C.X86_OP_FP +) + +// XOP Code Condition type +const ( + X86_XOP_CC_INVALID = C.X86_XOP_CC_INVALID + X86_XOP_CC_LT = C.X86_XOP_CC_LT + X86_XOP_CC_LE = C.X86_XOP_CC_LE + X86_XOP_CC_GT = C.X86_XOP_CC_GT + X86_XOP_CC_GE = C.X86_XOP_CC_GE + X86_XOP_CC_EQ = C.X86_XOP_CC_EQ + X86_XOP_CC_NEQ = C.X86_XOP_CC_NEQ + X86_XOP_CC_FALSE = C.X86_XOP_CC_FALSE + X86_XOP_CC_TRUE = C.X86_XOP_CC_TRUE ) // AVX broadcast type @@ -291,14 +394,6 @@ const ( X86_SSE_CC_NLT = C.X86_SSE_CC_NLT X86_SSE_CC_NLE = C.X86_SSE_CC_NLE X86_SSE_CC_ORD = C.X86_SSE_CC_ORD - X86_SSE_CC_EQ_UQ = C.X86_SSE_CC_EQ_UQ - X86_SSE_CC_NGE = C.X86_SSE_CC_NGE - X86_SSE_CC_NGT = C.X86_SSE_CC_NGT - X86_SSE_CC_FALSE = C.X86_SSE_CC_FALSE - X86_SSE_CC_NEQ_OQ = C.X86_SSE_CC_NEQ_OQ - X86_SSE_CC_GE = C.X86_SSE_CC_GE - X86_SSE_CC_GT = C.X86_SSE_CC_GT - X86_SSE_CC_TRUE = C.X86_SSE_CC_TRUE ) // AVX Code Condition type @@ -351,6 +446,7 @@ const ( const ( X86_PREFIX_LOCK = C.X86_PREFIX_LOCK X86_PREFIX_REP = C.X86_PREFIX_REP + X86_PREFIX_REPE = C.X86_PREFIX_REPE X86_PREFIX_REPNE = C.X86_PREFIX_REPNE X86_PREFIX_CS = C.X86_PREFIX_CS X86_PREFIX_SS = C.X86_PREFIX_SS @@ -429,9 +525,11 @@ const ( X86_INS_CLC = C.X86_INS_CLC X86_INS_CLD = C.X86_INS_CLD X86_INS_CLFLUSH = C.X86_INS_CLFLUSH + X86_INS_CLFLUSHOPT = C.X86_INS_CLFLUSHOPT X86_INS_CLGI = C.X86_INS_CLGI X86_INS_CLI = C.X86_INS_CLI X86_INS_CLTS = C.X86_INS_CLTS + X86_INS_CLWB = C.X86_INS_CLWB X86_INS_CMC = C.X86_INS_CMC X86_INS_CMOVA = C.X86_INS_CMOVA X86_INS_CMOVAE = C.X86_INS_CMOVAE @@ -458,12 +556,8 @@ const ( X86_INS_FCMOVU = C.X86_INS_FCMOVU X86_INS_CMOVS = C.X86_INS_CMOVS X86_INS_CMP = C.X86_INS_CMP - X86_INS_CMPPD = C.X86_INS_CMPPD - X86_INS_CMPPS = C.X86_INS_CMPPS X86_INS_CMPSB = C.X86_INS_CMPSB - X86_INS_CMPSD = C.X86_INS_CMPSD X86_INS_CMPSQ = C.X86_INS_CMPSQ - X86_INS_CMPSS = C.X86_INS_CMPSS X86_INS_CMPSW = C.X86_INS_CMPSW X86_INS_CMPXCHG16B = C.X86_INS_CMPXCHG16B X86_INS_CMPXCHG = C.X86_INS_CMPXCHG @@ -471,7 +565,7 @@ const ( X86_INS_COMISD = C.X86_INS_COMISD X86_INS_COMISS = C.X86_INS_COMISS X86_INS_FCOMP = C.X86_INS_FCOMP - X86_INS_FCOMPI = C.X86_INS_FCOMPI + X86_INS_FCOMIP = C.X86_INS_FCOMIP X86_INS_FCOMI = C.X86_INS_FCOMI X86_INS_FCOM = C.X86_INS_FCOM X86_INS_FCOS = C.X86_INS_FCOS @@ -547,6 +641,7 @@ const ( X86_INS_FPREM = C.X86_INS_FPREM X86_INS_FPREM1 = C.X86_INS_FPREM1 X86_INS_FPTAN = C.X86_INS_FPTAN + X86_INS_FFREEP = C.X86_INS_FFREEP X86_INS_FRNDINT = C.X86_INS_FRNDINT X86_INS_FRSTOR = C.X86_INS_FRSTOR X86_INS_FNSAVE = C.X86_INS_FNSAVE @@ -604,7 +699,6 @@ const ( X86_INS_FISTP = C.X86_INS_FISTP X86_INS_UCOMISD = C.X86_INS_UCOMISD X86_INS_UCOMISS = C.X86_INS_UCOMISS - X86_INS_VCMP = C.X86_INS_VCMP X86_INS_VCOMISD = C.X86_INS_VCOMISD X86_INS_VCOMISS = C.X86_INS_VCOMISS X86_INS_VCVTSD2SS = C.X86_INS_VCVTSD2SS @@ -658,9 +752,18 @@ const ( X86_INS_KORB = C.X86_INS_KORB X86_INS_KORD = C.X86_INS_KORD X86_INS_KORQ = C.X86_INS_KORQ + X86_INS_KORTESTB = C.X86_INS_KORTESTB + X86_INS_KORTESTD = C.X86_INS_KORTESTD + X86_INS_KORTESTQ = C.X86_INS_KORTESTQ X86_INS_KORTESTW = C.X86_INS_KORTESTW X86_INS_KORW = C.X86_INS_KORW + X86_INS_KSHIFTLB = C.X86_INS_KSHIFTLB + X86_INS_KSHIFTLD = C.X86_INS_KSHIFTLD + X86_INS_KSHIFTLQ = C.X86_INS_KSHIFTLQ X86_INS_KSHIFTLW = C.X86_INS_KSHIFTLW + X86_INS_KSHIFTRB = C.X86_INS_KSHIFTRB + X86_INS_KSHIFTRD = C.X86_INS_KSHIFTRD + X86_INS_KSHIFTRQ = C.X86_INS_KSHIFTRQ X86_INS_KSHIFTRW = C.X86_INS_KSHIFTRW X86_INS_KUNPCKBW = C.X86_INS_KUNPCKBW X86_INS_KXNORB = C.X86_INS_KXNORB @@ -869,6 +972,7 @@ const ( X86_INS_PCMPGTQ = C.X86_INS_PCMPGTQ X86_INS_PCMPISTRI = C.X86_INS_PCMPISTRI X86_INS_PCMPISTRM = C.X86_INS_PCMPISTRM + X86_INS_PCOMMIT = C.X86_INS_PCOMMIT X86_INS_PDEP = C.X86_INS_PDEP X86_INS_PEXT = C.X86_INS_PEXT X86_INS_PEXTRB = C.X86_INS_PEXTRB @@ -1039,6 +1143,7 @@ const ( X86_INS_FST = C.X86_INS_FST X86_INS_FSTP = C.X86_INS_FSTP X86_INS_FSTPNCE = C.X86_INS_FSTPNCE + X86_INS_FXCH = C.X86_INS_FXCH X86_INS_SUBPD = C.X86_INS_SUBPD X86_INS_SUBPS = C.X86_INS_SUBPS X86_INS_FSUBR = C.X86_INS_FSUBR @@ -1060,7 +1165,7 @@ const ( X86_INS_FTST = C.X86_INS_FTST X86_INS_TZCNT = C.X86_INS_TZCNT X86_INS_TZMSK = C.X86_INS_TZMSK - X86_INS_FUCOMPI = C.X86_INS_FUCOMPI + X86_INS_FUCOMIP = C.X86_INS_FUCOMIP X86_INS_FUCOMI = C.X86_INS_FUCOMI X86_INS_FUCOMPP = C.X86_INS_FUCOMPP X86_INS_FUCOMP = C.X86_INS_FUCOMP @@ -1095,15 +1200,12 @@ const ( X86_INS_VBLENDVPD = C.X86_INS_VBLENDVPD X86_INS_VBLENDVPS = C.X86_INS_VBLENDVPS X86_INS_VBROADCASTF128 = C.X86_INS_VBROADCASTF128 - X86_INS_VBROADCASTI128 = C.X86_INS_VBROADCASTI128 X86_INS_VBROADCASTI32X4 = C.X86_INS_VBROADCASTI32X4 X86_INS_VBROADCASTI64X4 = C.X86_INS_VBROADCASTI64X4 X86_INS_VBROADCASTSD = C.X86_INS_VBROADCASTSD X86_INS_VBROADCASTSS = C.X86_INS_VBROADCASTSS - X86_INS_VCMPPD = C.X86_INS_VCMPPD - X86_INS_VCMPPS = C.X86_INS_VCMPPS - X86_INS_VCMPSD = C.X86_INS_VCMPSD - X86_INS_VCMPSS = C.X86_INS_VCMPSS + X86_INS_VCOMPRESSPD = C.X86_INS_VCOMPRESSPD + X86_INS_VCOMPRESSPS = C.X86_INS_VCOMPRESSPS X86_INS_VCVTDQ2PD = C.X86_INS_VCVTDQ2PD X86_INS_VCVTDQ2PS = C.X86_INS_VCVTDQ2PS X86_INS_VCVTPD2DQX = C.X86_INS_VCVTPD2DQX @@ -1135,6 +1237,10 @@ const ( X86_INS_VDPPS = C.X86_INS_VDPPS X86_INS_VERR = C.X86_INS_VERR X86_INS_VERW = C.X86_INS_VERW + X86_INS_VEXP2PD = C.X86_INS_VEXP2PD + X86_INS_VEXP2PS = C.X86_INS_VEXP2PS + X86_INS_VEXPANDPD = C.X86_INS_VEXPANDPD + X86_INS_VEXPANDPS = C.X86_INS_VEXPANDPS X86_INS_VEXTRACTF128 = C.X86_INS_VEXTRACTF128 X86_INS_VEXTRACTF32X4 = C.X86_INS_VEXTRACTF32X4 X86_INS_VEXTRACTF64X4 = C.X86_INS_VEXTRACTF64X4 @@ -1144,11 +1250,11 @@ const ( X86_INS_VEXTRACTPS = C.X86_INS_VEXTRACTPS X86_INS_VFMADD132PD = C.X86_INS_VFMADD132PD X86_INS_VFMADD132PS = C.X86_INS_VFMADD132PS - X86_INS_VFMADD213PD = C.X86_INS_VFMADD213PD - X86_INS_VFMADD213PS = C.X86_INS_VFMADD213PS X86_INS_VFMADDPD = C.X86_INS_VFMADDPD + X86_INS_VFMADD213PD = C.X86_INS_VFMADD213PD X86_INS_VFMADD231PD = C.X86_INS_VFMADD231PD X86_INS_VFMADDPS = C.X86_INS_VFMADDPS + X86_INS_VFMADD213PS = C.X86_INS_VFMADD213PS X86_INS_VFMADD231PS = C.X86_INS_VFMADD231PS X86_INS_VFMADDSD = C.X86_INS_VFMADDSD X86_INS_VFMADD213SD = C.X86_INS_VFMADD213SD @@ -1160,27 +1266,27 @@ const ( X86_INS_VFMADD231SS = C.X86_INS_VFMADD231SS X86_INS_VFMADDSUB132PD = C.X86_INS_VFMADDSUB132PD X86_INS_VFMADDSUB132PS = C.X86_INS_VFMADDSUB132PS - X86_INS_VFMADDSUB213PD = C.X86_INS_VFMADDSUB213PD - X86_INS_VFMADDSUB213PS = C.X86_INS_VFMADDSUB213PS X86_INS_VFMADDSUBPD = C.X86_INS_VFMADDSUBPD + X86_INS_VFMADDSUB213PD = C.X86_INS_VFMADDSUB213PD X86_INS_VFMADDSUB231PD = C.X86_INS_VFMADDSUB231PD X86_INS_VFMADDSUBPS = C.X86_INS_VFMADDSUBPS + X86_INS_VFMADDSUB213PS = C.X86_INS_VFMADDSUB213PS X86_INS_VFMADDSUB231PS = C.X86_INS_VFMADDSUB231PS X86_INS_VFMSUB132PD = C.X86_INS_VFMSUB132PD X86_INS_VFMSUB132PS = C.X86_INS_VFMSUB132PS - X86_INS_VFMSUB213PD = C.X86_INS_VFMSUB213PD - X86_INS_VFMSUB213PS = C.X86_INS_VFMSUB213PS X86_INS_VFMSUBADD132PD = C.X86_INS_VFMSUBADD132PD X86_INS_VFMSUBADD132PS = C.X86_INS_VFMSUBADD132PS - X86_INS_VFMSUBADD213PD = C.X86_INS_VFMSUBADD213PD - X86_INS_VFMSUBADD213PS = C.X86_INS_VFMSUBADD213PS X86_INS_VFMSUBADDPD = C.X86_INS_VFMSUBADDPD + X86_INS_VFMSUBADD213PD = C.X86_INS_VFMSUBADD213PD X86_INS_VFMSUBADD231PD = C.X86_INS_VFMSUBADD231PD X86_INS_VFMSUBADDPS = C.X86_INS_VFMSUBADDPS + X86_INS_VFMSUBADD213PS = C.X86_INS_VFMSUBADD213PS X86_INS_VFMSUBADD231PS = C.X86_INS_VFMSUBADD231PS X86_INS_VFMSUBPD = C.X86_INS_VFMSUBPD + X86_INS_VFMSUB213PD = C.X86_INS_VFMSUB213PD X86_INS_VFMSUB231PD = C.X86_INS_VFMSUB231PD X86_INS_VFMSUBPS = C.X86_INS_VFMSUBPS + X86_INS_VFMSUB213PS = C.X86_INS_VFMSUB213PS X86_INS_VFMSUB231PS = C.X86_INS_VFMSUB231PS X86_INS_VFMSUBSD = C.X86_INS_VFMSUBSD X86_INS_VFMSUB213SD = C.X86_INS_VFMSUB213SD @@ -1192,11 +1298,11 @@ const ( X86_INS_VFMSUB231SS = C.X86_INS_VFMSUB231SS X86_INS_VFNMADD132PD = C.X86_INS_VFNMADD132PD X86_INS_VFNMADD132PS = C.X86_INS_VFNMADD132PS - X86_INS_VFNMADD213PD = C.X86_INS_VFNMADD213PD - X86_INS_VFNMADD213PS = C.X86_INS_VFNMADD213PS X86_INS_VFNMADDPD = C.X86_INS_VFNMADDPD + X86_INS_VFNMADD213PD = C.X86_INS_VFNMADD213PD X86_INS_VFNMADD231PD = C.X86_INS_VFNMADD231PD X86_INS_VFNMADDPS = C.X86_INS_VFNMADDPS + X86_INS_VFNMADD213PS = C.X86_INS_VFNMADD213PS X86_INS_VFNMADD231PS = C.X86_INS_VFNMADD231PS X86_INS_VFNMADDSD = C.X86_INS_VFNMADDSD X86_INS_VFNMADD213SD = C.X86_INS_VFNMADD213SD @@ -1208,11 +1314,11 @@ const ( X86_INS_VFNMADD231SS = C.X86_INS_VFNMADD231SS X86_INS_VFNMSUB132PD = C.X86_INS_VFNMSUB132PD X86_INS_VFNMSUB132PS = C.X86_INS_VFNMSUB132PS - X86_INS_VFNMSUB213PD = C.X86_INS_VFNMSUB213PD - X86_INS_VFNMSUB213PS = C.X86_INS_VFNMSUB213PS X86_INS_VFNMSUBPD = C.X86_INS_VFNMSUBPD + X86_INS_VFNMSUB213PD = C.X86_INS_VFNMSUB213PD X86_INS_VFNMSUB231PD = C.X86_INS_VFNMSUB231PD X86_INS_VFNMSUBPS = C.X86_INS_VFNMSUBPS + X86_INS_VFNMSUB213PS = C.X86_INS_VFNMSUB213PS X86_INS_VFNMSUB231PS = C.X86_INS_VFNMSUB231PS X86_INS_VFNMSUBSD = C.X86_INS_VFNMSUBSD X86_INS_VFNMSUB213SD = C.X86_INS_VFNMSUB213SD @@ -1248,9 +1354,13 @@ const ( X86_INS_VHSUBPS = C.X86_INS_VHSUBPS X86_INS_VINSERTF128 = C.X86_INS_VINSERTF128 X86_INS_VINSERTF32X4 = C.X86_INS_VINSERTF32X4 + X86_INS_VINSERTF32X8 = C.X86_INS_VINSERTF32X8 + X86_INS_VINSERTF64X2 = C.X86_INS_VINSERTF64X2 X86_INS_VINSERTF64X4 = C.X86_INS_VINSERTF64X4 X86_INS_VINSERTI128 = C.X86_INS_VINSERTI128 X86_INS_VINSERTI32X4 = C.X86_INS_VINSERTI32X4 + X86_INS_VINSERTI32X8 = C.X86_INS_VINSERTI32X8 + X86_INS_VINSERTI64X2 = C.X86_INS_VINSERTI64X2 X86_INS_VINSERTI64X4 = C.X86_INS_VINSERTI64X4 X86_INS_VINSERTPS = C.X86_INS_VINSERTPS X86_INS_VLDDQU = C.X86_INS_VLDDQU @@ -1341,8 +1451,10 @@ const ( X86_INS_VPAVGB = C.X86_INS_VPAVGB X86_INS_VPAVGW = C.X86_INS_VPAVGW X86_INS_VPBLENDD = C.X86_INS_VPBLENDD + X86_INS_VPBLENDMB = C.X86_INS_VPBLENDMB X86_INS_VPBLENDMD = C.X86_INS_VPBLENDMD X86_INS_VPBLENDMQ = C.X86_INS_VPBLENDMQ + X86_INS_VPBLENDMW = C.X86_INS_VPBLENDMW X86_INS_VPBLENDVB = C.X86_INS_VPBLENDVB X86_INS_VPBLENDW = C.X86_INS_VPBLENDW X86_INS_VPBROADCASTB = C.X86_INS_VPBROADCASTB @@ -1353,7 +1465,7 @@ const ( X86_INS_VPBROADCASTW = C.X86_INS_VPBROADCASTW X86_INS_VPCLMULQDQ = C.X86_INS_VPCLMULQDQ X86_INS_VPCMOV = C.X86_INS_VPCMOV - X86_INS_VPCMP = C.X86_INS_VPCMP + X86_INS_VPCMPB = C.X86_INS_VPCMPB X86_INS_VPCMPD = C.X86_INS_VPCMPD X86_INS_VPCMPEQB = C.X86_INS_VPCMPEQB X86_INS_VPCMPEQD = C.X86_INS_VPCMPEQD @@ -1368,10 +1480,15 @@ const ( X86_INS_VPCMPISTRI = C.X86_INS_VPCMPISTRI X86_INS_VPCMPISTRM = C.X86_INS_VPCMPISTRM X86_INS_VPCMPQ = C.X86_INS_VPCMPQ + X86_INS_VPCMPUB = C.X86_INS_VPCMPUB X86_INS_VPCMPUD = C.X86_INS_VPCMPUD X86_INS_VPCMPUQ = C.X86_INS_VPCMPUQ + X86_INS_VPCMPUW = C.X86_INS_VPCMPUW + X86_INS_VPCMPW = C.X86_INS_VPCMPW X86_INS_VPCOMB = C.X86_INS_VPCOMB X86_INS_VPCOMD = C.X86_INS_VPCOMD + X86_INS_VPCOMPRESSD = C.X86_INS_VPCOMPRESSD + X86_INS_VPCOMPRESSQ = C.X86_INS_VPCOMPRESSQ X86_INS_VPCOMQ = C.X86_INS_VPCOMQ X86_INS_VPCOMUB = C.X86_INS_VPCOMUB X86_INS_VPCOMUD = C.X86_INS_VPCOMUD @@ -1398,6 +1515,8 @@ const ( X86_INS_VPERMT2PD = C.X86_INS_VPERMT2PD X86_INS_VPERMT2PS = C.X86_INS_VPERMT2PS X86_INS_VPERMT2Q = C.X86_INS_VPERMT2Q + X86_INS_VPEXPANDD = C.X86_INS_VPEXPANDD + X86_INS_VPEXPANDQ = C.X86_INS_VPEXPANDQ X86_INS_VPEXTRB = C.X86_INS_VPEXTRB X86_INS_VPEXTRD = C.X86_INS_VPEXTRD X86_INS_VPEXTRQ = C.X86_INS_VPEXTRQ @@ -1468,6 +1587,10 @@ const ( X86_INS_VPMINUW = C.X86_INS_VPMINUW X86_INS_VPMOVDB = C.X86_INS_VPMOVDB X86_INS_VPMOVDW = C.X86_INS_VPMOVDW + X86_INS_VPMOVM2B = C.X86_INS_VPMOVM2B + X86_INS_VPMOVM2D = C.X86_INS_VPMOVM2D + X86_INS_VPMOVM2Q = C.X86_INS_VPMOVM2Q + X86_INS_VPMOVM2W = C.X86_INS_VPMOVM2W X86_INS_VPMOVMSKB = C.X86_INS_VPMOVMSKB X86_INS_VPMOVQB = C.X86_INS_VPMOVQB X86_INS_VPMOVQD = C.X86_INS_VPMOVQD @@ -1499,6 +1622,7 @@ const ( X86_INS_VPMULHUW = C.X86_INS_VPMULHUW X86_INS_VPMULHW = C.X86_INS_VPMULHW X86_INS_VPMULLD = C.X86_INS_VPMULLD + X86_INS_VPMULLQ = C.X86_INS_VPMULLQ X86_INS_VPMULLW = C.X86_INS_VPMULLW X86_INS_VPMULUDQ = C.X86_INS_VPMULUDQ X86_INS_VPORD = C.X86_INS_VPORD @@ -1638,7 +1762,6 @@ const ( X86_INS_XACQUIRE = C.X86_INS_XACQUIRE X86_INS_XBEGIN = C.X86_INS_XBEGIN X86_INS_XCHG = C.X86_INS_XCHG - X86_INS_FXCH = C.X86_INS_FXCH X86_INS_XCRYPTCBC = C.X86_INS_XCRYPTCBC X86_INS_XCRYPTCFB = C.X86_INS_XCRYPTCFB X86_INS_XCRYPTCTR = C.X86_INS_XCRYPTCTR @@ -1650,15 +1773,194 @@ const ( X86_INS_XRELEASE = C.X86_INS_XRELEASE X86_INS_XRSTOR = C.X86_INS_XRSTOR X86_INS_XRSTOR64 = C.X86_INS_XRSTOR64 + X86_INS_XRSTORS = C.X86_INS_XRSTORS + X86_INS_XRSTORS64 = C.X86_INS_XRSTORS64 X86_INS_XSAVE = C.X86_INS_XSAVE X86_INS_XSAVE64 = C.X86_INS_XSAVE64 + X86_INS_XSAVEC = C.X86_INS_XSAVEC + X86_INS_XSAVEC64 = C.X86_INS_XSAVEC64 X86_INS_XSAVEOPT = C.X86_INS_XSAVEOPT X86_INS_XSAVEOPT64 = C.X86_INS_XSAVEOPT64 + X86_INS_XSAVES = C.X86_INS_XSAVES + X86_INS_XSAVES64 = C.X86_INS_XSAVES64 X86_INS_XSETBV = C.X86_INS_XSETBV X86_INS_XSHA1 = C.X86_INS_XSHA1 X86_INS_XSHA256 = C.X86_INS_XSHA256 X86_INS_XSTORE = C.X86_INS_XSTORE X86_INS_XTEST = C.X86_INS_XTEST + X86_INS_FDISI8087_NOP = C.X86_INS_FDISI8087_NOP + X86_INS_FENI8087_NOP = C.X86_INS_FENI8087_NOP + X86_INS_CMPSS = C.X86_INS_CMPSS + X86_INS_CMPEQSS = C.X86_INS_CMPEQSS + X86_INS_CMPLTSS = C.X86_INS_CMPLTSS + X86_INS_CMPLESS = C.X86_INS_CMPLESS + X86_INS_CMPUNORDSS = C.X86_INS_CMPUNORDSS + X86_INS_CMPNEQSS = C.X86_INS_CMPNEQSS + X86_INS_CMPNLTSS = C.X86_INS_CMPNLTSS + X86_INS_CMPNLESS = C.X86_INS_CMPNLESS + X86_INS_CMPORDSS = C.X86_INS_CMPORDSS + X86_INS_CMPSD = C.X86_INS_CMPSD + X86_INS_CMPEQSD = C.X86_INS_CMPEQSD + X86_INS_CMPLTSD = C.X86_INS_CMPLTSD + X86_INS_CMPLESD = C.X86_INS_CMPLESD + X86_INS_CMPUNORDSD = C.X86_INS_CMPUNORDSD + X86_INS_CMPNEQSD = C.X86_INS_CMPNEQSD + X86_INS_CMPNLTSD = C.X86_INS_CMPNLTSD + X86_INS_CMPNLESD = C.X86_INS_CMPNLESD + X86_INS_CMPORDSD = C.X86_INS_CMPORDSD + X86_INS_CMPPS = C.X86_INS_CMPPS + X86_INS_CMPEQPS = C.X86_INS_CMPEQPS + X86_INS_CMPLTPS = C.X86_INS_CMPLTPS + X86_INS_CMPLEPS = C.X86_INS_CMPLEPS + X86_INS_CMPUNORDPS = C.X86_INS_CMPUNORDPS + X86_INS_CMPNEQPS = C.X86_INS_CMPNEQPS + X86_INS_CMPNLTPS = C.X86_INS_CMPNLTPS + X86_INS_CMPNLEPS = C.X86_INS_CMPNLEPS + X86_INS_CMPORDPS = C.X86_INS_CMPORDPS + X86_INS_CMPPD = C.X86_INS_CMPPD + X86_INS_CMPEQPD = C.X86_INS_CMPEQPD + X86_INS_CMPLTPD = C.X86_INS_CMPLTPD + X86_INS_CMPLEPD = C.X86_INS_CMPLEPD + X86_INS_CMPUNORDPD = C.X86_INS_CMPUNORDPD + X86_INS_CMPNEQPD = C.X86_INS_CMPNEQPD + X86_INS_CMPNLTPD = C.X86_INS_CMPNLTPD + X86_INS_CMPNLEPD = C.X86_INS_CMPNLEPD + X86_INS_CMPORDPD = C.X86_INS_CMPORDPD + X86_INS_VCMPSS = C.X86_INS_VCMPSS + X86_INS_VCMPEQSS = C.X86_INS_VCMPEQSS + X86_INS_VCMPLTSS = C.X86_INS_VCMPLTSS + X86_INS_VCMPLESS = C.X86_INS_VCMPLESS + X86_INS_VCMPUNORDSS = C.X86_INS_VCMPUNORDSS + X86_INS_VCMPNEQSS = C.X86_INS_VCMPNEQSS + X86_INS_VCMPNLTSS = C.X86_INS_VCMPNLTSS + X86_INS_VCMPNLESS = C.X86_INS_VCMPNLESS + X86_INS_VCMPORDSS = C.X86_INS_VCMPORDSS + X86_INS_VCMPEQ_UQSS = C.X86_INS_VCMPEQ_UQSS + X86_INS_VCMPNGESS = C.X86_INS_VCMPNGESS + X86_INS_VCMPNGTSS = C.X86_INS_VCMPNGTSS + X86_INS_VCMPFALSESS = C.X86_INS_VCMPFALSESS + X86_INS_VCMPNEQ_OQSS = C.X86_INS_VCMPNEQ_OQSS + X86_INS_VCMPGESS = C.X86_INS_VCMPGESS + X86_INS_VCMPGTSS = C.X86_INS_VCMPGTSS + X86_INS_VCMPTRUESS = C.X86_INS_VCMPTRUESS + X86_INS_VCMPEQ_OSSS = C.X86_INS_VCMPEQ_OSSS + X86_INS_VCMPLT_OQSS = C.X86_INS_VCMPLT_OQSS + X86_INS_VCMPLE_OQSS = C.X86_INS_VCMPLE_OQSS + X86_INS_VCMPUNORD_SSS = C.X86_INS_VCMPUNORD_SSS + X86_INS_VCMPNEQ_USSS = C.X86_INS_VCMPNEQ_USSS + X86_INS_VCMPNLT_UQSS = C.X86_INS_VCMPNLT_UQSS + X86_INS_VCMPNLE_UQSS = C.X86_INS_VCMPNLE_UQSS + X86_INS_VCMPORD_SSS = C.X86_INS_VCMPORD_SSS + X86_INS_VCMPEQ_USSS = C.X86_INS_VCMPEQ_USSS + X86_INS_VCMPNGE_UQSS = C.X86_INS_VCMPNGE_UQSS + X86_INS_VCMPNGT_UQSS = C.X86_INS_VCMPNGT_UQSS + X86_INS_VCMPFALSE_OSSS = C.X86_INS_VCMPFALSE_OSSS + X86_INS_VCMPNEQ_OSSS = C.X86_INS_VCMPNEQ_OSSS + X86_INS_VCMPGE_OQSS = C.X86_INS_VCMPGE_OQSS + X86_INS_VCMPGT_OQSS = C.X86_INS_VCMPGT_OQSS + X86_INS_VCMPTRUE_USSS = C.X86_INS_VCMPTRUE_USSS + X86_INS_VCMPSD = C.X86_INS_VCMPSD + X86_INS_VCMPEQSD = C.X86_INS_VCMPEQSD + X86_INS_VCMPLTSD = C.X86_INS_VCMPLTSD + X86_INS_VCMPLESD = C.X86_INS_VCMPLESD + X86_INS_VCMPUNORDSD = C.X86_INS_VCMPUNORDSD + X86_INS_VCMPNEQSD = C.X86_INS_VCMPNEQSD + X86_INS_VCMPNLTSD = C.X86_INS_VCMPNLTSD + X86_INS_VCMPNLESD = C.X86_INS_VCMPNLESD + X86_INS_VCMPORDSD = C.X86_INS_VCMPORDSD + X86_INS_VCMPEQ_UQSD = C.X86_INS_VCMPEQ_UQSD + X86_INS_VCMPNGESD = C.X86_INS_VCMPNGESD + X86_INS_VCMPNGTSD = C.X86_INS_VCMPNGTSD + X86_INS_VCMPFALSESD = C.X86_INS_VCMPFALSESD + X86_INS_VCMPNEQ_OQSD = C.X86_INS_VCMPNEQ_OQSD + X86_INS_VCMPGESD = C.X86_INS_VCMPGESD + X86_INS_VCMPGTSD = C.X86_INS_VCMPGTSD + X86_INS_VCMPTRUESD = C.X86_INS_VCMPTRUESD + X86_INS_VCMPEQ_OSSD = C.X86_INS_VCMPEQ_OSSD + X86_INS_VCMPLT_OQSD = C.X86_INS_VCMPLT_OQSD + X86_INS_VCMPLE_OQSD = C.X86_INS_VCMPLE_OQSD + X86_INS_VCMPUNORD_SSD = C.X86_INS_VCMPUNORD_SSD + X86_INS_VCMPNEQ_USSD = C.X86_INS_VCMPNEQ_USSD + X86_INS_VCMPNLT_UQSD = C.X86_INS_VCMPNLT_UQSD + X86_INS_VCMPNLE_UQSD = C.X86_INS_VCMPNLE_UQSD + X86_INS_VCMPORD_SSD = C.X86_INS_VCMPORD_SSD + X86_INS_VCMPEQ_USSD = C.X86_INS_VCMPEQ_USSD + X86_INS_VCMPNGE_UQSD = C.X86_INS_VCMPNGE_UQSD + X86_INS_VCMPNGT_UQSD = C.X86_INS_VCMPNGT_UQSD + X86_INS_VCMPFALSE_OSSD = C.X86_INS_VCMPFALSE_OSSD + X86_INS_VCMPNEQ_OSSD = C.X86_INS_VCMPNEQ_OSSD + X86_INS_VCMPGE_OQSD = C.X86_INS_VCMPGE_OQSD + X86_INS_VCMPGT_OQSD = C.X86_INS_VCMPGT_OQSD + X86_INS_VCMPTRUE_USSD = C.X86_INS_VCMPTRUE_USSD + X86_INS_VCMPPS = C.X86_INS_VCMPPS + X86_INS_VCMPEQPS = C.X86_INS_VCMPEQPS + X86_INS_VCMPLTPS = C.X86_INS_VCMPLTPS + X86_INS_VCMPLEPS = C.X86_INS_VCMPLEPS + X86_INS_VCMPUNORDPS = C.X86_INS_VCMPUNORDPS + X86_INS_VCMPNEQPS = C.X86_INS_VCMPNEQPS + X86_INS_VCMPNLTPS = C.X86_INS_VCMPNLTPS + X86_INS_VCMPNLEPS = C.X86_INS_VCMPNLEPS + X86_INS_VCMPORDPS = C.X86_INS_VCMPORDPS + X86_INS_VCMPEQ_UQPS = C.X86_INS_VCMPEQ_UQPS + X86_INS_VCMPNGEPS = C.X86_INS_VCMPNGEPS + X86_INS_VCMPNGTPS = C.X86_INS_VCMPNGTPS + X86_INS_VCMPFALSEPS = C.X86_INS_VCMPFALSEPS + X86_INS_VCMPNEQ_OQPS = C.X86_INS_VCMPNEQ_OQPS + X86_INS_VCMPGEPS = C.X86_INS_VCMPGEPS + X86_INS_VCMPGTPS = C.X86_INS_VCMPGTPS + X86_INS_VCMPTRUEPS = C.X86_INS_VCMPTRUEPS + X86_INS_VCMPEQ_OSPS = C.X86_INS_VCMPEQ_OSPS + X86_INS_VCMPLT_OQPS = C.X86_INS_VCMPLT_OQPS + X86_INS_VCMPLE_OQPS = C.X86_INS_VCMPLE_OQPS + X86_INS_VCMPUNORD_SPS = C.X86_INS_VCMPUNORD_SPS + X86_INS_VCMPNEQ_USPS = C.X86_INS_VCMPNEQ_USPS + X86_INS_VCMPNLT_UQPS = C.X86_INS_VCMPNLT_UQPS + X86_INS_VCMPNLE_UQPS = C.X86_INS_VCMPNLE_UQPS + X86_INS_VCMPORD_SPS = C.X86_INS_VCMPORD_SPS + X86_INS_VCMPEQ_USPS = C.X86_INS_VCMPEQ_USPS + X86_INS_VCMPNGE_UQPS = C.X86_INS_VCMPNGE_UQPS + X86_INS_VCMPNGT_UQPS = C.X86_INS_VCMPNGT_UQPS + X86_INS_VCMPFALSE_OSPS = C.X86_INS_VCMPFALSE_OSPS + X86_INS_VCMPNEQ_OSPS = C.X86_INS_VCMPNEQ_OSPS + X86_INS_VCMPGE_OQPS = C.X86_INS_VCMPGE_OQPS + X86_INS_VCMPGT_OQPS = C.X86_INS_VCMPGT_OQPS + X86_INS_VCMPTRUE_USPS = C.X86_INS_VCMPTRUE_USPS + X86_INS_VCMPPD = C.X86_INS_VCMPPD + X86_INS_VCMPEQPD = C.X86_INS_VCMPEQPD + X86_INS_VCMPLTPD = C.X86_INS_VCMPLTPD + X86_INS_VCMPLEPD = C.X86_INS_VCMPLEPD + X86_INS_VCMPUNORDPD = C.X86_INS_VCMPUNORDPD + X86_INS_VCMPNEQPD = C.X86_INS_VCMPNEQPD + X86_INS_VCMPNLTPD = C.X86_INS_VCMPNLTPD + X86_INS_VCMPNLEPD = C.X86_INS_VCMPNLEPD + X86_INS_VCMPORDPD = C.X86_INS_VCMPORDPD + X86_INS_VCMPEQ_UQPD = C.X86_INS_VCMPEQ_UQPD + X86_INS_VCMPNGEPD = C.X86_INS_VCMPNGEPD + X86_INS_VCMPNGTPD = C.X86_INS_VCMPNGTPD + X86_INS_VCMPFALSEPD = C.X86_INS_VCMPFALSEPD + X86_INS_VCMPNEQ_OQPD = C.X86_INS_VCMPNEQ_OQPD + X86_INS_VCMPGEPD = C.X86_INS_VCMPGEPD + X86_INS_VCMPGTPD = C.X86_INS_VCMPGTPD + X86_INS_VCMPTRUEPD = C.X86_INS_VCMPTRUEPD + X86_INS_VCMPEQ_OSPD = C.X86_INS_VCMPEQ_OSPD + X86_INS_VCMPLT_OQPD = C.X86_INS_VCMPLT_OQPD + X86_INS_VCMPLE_OQPD = C.X86_INS_VCMPLE_OQPD + X86_INS_VCMPUNORD_SPD = C.X86_INS_VCMPUNORD_SPD + X86_INS_VCMPNEQ_USPD = C.X86_INS_VCMPNEQ_USPD + X86_INS_VCMPNLT_UQPD = C.X86_INS_VCMPNLT_UQPD + X86_INS_VCMPNLE_UQPD = C.X86_INS_VCMPNLE_UQPD + X86_INS_VCMPORD_SPD = C.X86_INS_VCMPORD_SPD + X86_INS_VCMPEQ_USPD = C.X86_INS_VCMPEQ_USPD + X86_INS_VCMPNGE_UQPD = C.X86_INS_VCMPNGE_UQPD + X86_INS_VCMPNGT_UQPD = C.X86_INS_VCMPNGT_UQPD + X86_INS_VCMPFALSE_OSPD = C.X86_INS_VCMPFALSE_OSPD + X86_INS_VCMPNEQ_OSPD = C.X86_INS_VCMPNEQ_OSPD + X86_INS_VCMPGE_OQPD = C.X86_INS_VCMPGE_OQPD + X86_INS_VCMPGT_OQPD = C.X86_INS_VCMPGT_OQPD + X86_INS_VCMPTRUE_USPD = C.X86_INS_VCMPTRUE_USPD + X86_INS_UD0 = C.X86_INS_UD0 + X86_INS_ENDBR32 = C.X86_INS_ENDBR32 + X86_INS_ENDBR64 = C.X86_INS_ENDBR64 X86_INS_ENDING = C.X86_INS_ENDING ) @@ -1669,11 +1971,13 @@ const ( // Generic groups const ( - X86_GRP_JUMP = C.X86_GRP_JUMP - X86_GRP_CALL = C.X86_GRP_CALL - X86_GRP_RET = C.X86_GRP_RET - X86_GRP_INT = C.X86_GRP_INT - X86_GRP_IRET = C.X86_GRP_IRET + X86_GRP_JUMP = C.X86_GRP_JUMP + X86_GRP_CALL = C.X86_GRP_CALL + X86_GRP_RET = C.X86_GRP_RET + X86_GRP_INT = C.X86_GRP_INT + X86_GRP_IRET = C.X86_GRP_IRET + X86_GRP_PRIVILEGE = C.X86_GRP_PRIVILEGE + X86_GRP_BRANCH_RELATIVE = C.X86_GRP_BRANCH_RELATIVE ) // Architecture-specific groups @@ -1719,5 +2023,6 @@ const ( X86_GRP_VLX = C.X86_GRP_VLX X86_GRP_SMAP = C.X86_GRP_SMAP X86_GRP_NOVLX = C.X86_GRP_NOVLX + X86_GRP_FPU = C.X86_GRP_FPU X86_GRP_ENDING = C.X86_GRP_ENDING ) diff --git a/x86_decomposer.go b/x86_decomposer.go index 83da2f2..43a6e90 100644 --- a/x86_decomposer.go +++ b/x86_decomposer.go @@ -30,15 +30,19 @@ type X86Instruction struct { AddrSize byte ModRM byte Sib byte - Disp int32 + Disp int64 SibIndex uint SibScale int8 SibBase uint + XopCC uint SseCC uint AvxCC uint AvxSAE bool AvxRM uint + EFlags uint64 + FPUFlags uint64 Operands []X86Operand + Encoding X86Encoding } // Number of Operands of a given X86_OP_* type @@ -52,13 +56,21 @@ func (insn X86Instruction) OpCount(optype uint) int { return count } +type X86Encoding struct { + ModRMOffset byte + DispOffset byte + DispSize byte + ImmOffset byte + ImmSize byte +} + type X86Operand struct { Type uint // X86_OP_* - determines which field is set below Reg uint Imm int64 - FP float64 Mem X86MemoryOperand Size uint8 + Access uint8 AvxBcast uint AvxZeroOpmask bool } @@ -99,14 +111,32 @@ func fillX86Header(raw C.cs_insn, insn *Instruction) { AddrSize: byte(cs_x86.addr_size), ModRM: byte(cs_x86.modrm), Sib: byte(cs_x86.sib), - Disp: int32(cs_x86.disp), + Disp: int64(cs_x86.disp), SibIndex: uint(cs_x86.sib_index), SibScale: int8(cs_x86.sib_scale), SibBase: uint(cs_x86.sib_base), + XopCC: uint(cs_x86.xop_cc), SseCC: uint(cs_x86.sse_cc), AvxCC: uint(cs_x86.avx_cc), AvxSAE: bool(cs_x86.avx_sae), AvxRM: uint(cs_x86.avx_rm), + Encoding: X86Encoding{ + ModRMOffset: byte(cs_x86.encoding.modrm_offset), + DispOffset: byte(cs_x86.encoding.disp_offset), + DispSize: byte(cs_x86.encoding.disp_size), + ImmOffset: byte(cs_x86.encoding.imm_offset), + ImmSize: byte(cs_x86.encoding.imm_size), + }, + } + + // Handle eflags and fpu_flags union + x86.EFlags = uint64(*(*C.uint64_t)(unsafe.Pointer(&cs_x86.anon0[0]))) + for _, group := range insn.Groups { + if group == X86_GRP_FPU { + x86.EFlags = 0 + x86.FPUFlags = uint64(*(*C.uint64_t)(unsafe.Pointer(&cs_x86.anon0[0]))) + break + } } // Cast the op_info to a []C.cs_x86_op @@ -126,6 +156,7 @@ func fillX86Header(raw C.cs_insn, insn *Instruction) { gop := X86Operand{ Type: uint(cop._type), Size: uint8(cop.size), + Access: uint8(cop.access), AvxBcast: uint(cop.avx_bcast), AvxZeroOpmask: bool(cop.avx_zero_opmask), } @@ -134,8 +165,6 @@ func fillX86Header(raw C.cs_insn, insn *Instruction) { // fake a union by setting only the correct struct member case X86_OP_IMM: gop.Imm = int64(*(*C.int64_t)(unsafe.Pointer(&cop.anon0[0]))) - case X86_OP_FP: - gop.FP = float64(*(*C.double)(unsafe.Pointer(&cop.anon0[0]))) case X86_OP_REG: gop.Reg = uint(*(*C.uint)(unsafe.Pointer(&cop.anon0[0]))) case X86_OP_MEM: @@ -155,11 +184,11 @@ func fillX86Header(raw C.cs_insn, insn *Instruction) { insn.X86 = &x86 } -func decomposeX86(raws []C.cs_insn) []Instruction { +func decomposeX86(e *Engine, raws []C.cs_insn) []Instruction { decomposed := []Instruction{} for _, raw := range raws { decomp := new(Instruction) - fillGenericHeader(raw, decomp) + fillGenericHeader(e, raw, decomp) fillX86Header(raw, decomp) decomposed = append(decomposed, *decomp) } diff --git a/x86_decomposer_test.go b/x86_decomposer_test.go index 82700f0..dfa6294 100644 --- a/x86_decomposer_test.go +++ b/x86_decomposer_test.go @@ -17,6 +17,152 @@ import ( "testing" ) +func getEFlagName(flag uint64) string { + switch flag { + default: + return "" + case X86_EFLAGS_UNDEFINED_OF: + return "UNDEF_OF" + case X86_EFLAGS_UNDEFINED_SF: + return "UNDEF_SF" + case X86_EFLAGS_UNDEFINED_ZF: + return "UNDEF_ZF" + case X86_EFLAGS_MODIFY_AF: + return "MOD_AF" + case X86_EFLAGS_UNDEFINED_PF: + return "UNDEF_PF" + case X86_EFLAGS_MODIFY_CF: + return "MOD_CF" + case X86_EFLAGS_MODIFY_SF: + return "MOD_SF" + case X86_EFLAGS_MODIFY_ZF: + return "MOD_ZF" + case X86_EFLAGS_UNDEFINED_AF: + return "UNDEF_AF" + case X86_EFLAGS_MODIFY_PF: + return "MOD_PF" + case X86_EFLAGS_UNDEFINED_CF: + return "UNDEF_CF" + case X86_EFLAGS_MODIFY_OF: + return "MOD_OF" + case X86_EFLAGS_RESET_OF: + return "RESET_OF" + case X86_EFLAGS_RESET_CF: + return "RESET_CF" + case X86_EFLAGS_RESET_DF: + return "RESET_DF" + case X86_EFLAGS_RESET_IF: + return "RESET_IF" + case X86_EFLAGS_TEST_OF: + return "TEST_OF" + case X86_EFLAGS_TEST_SF: + return "TEST_SF" + case X86_EFLAGS_TEST_ZF: + return "TEST_ZF" + case X86_EFLAGS_TEST_PF: + return "TEST_PF" + case X86_EFLAGS_TEST_CF: + return "TEST_CF" + case X86_EFLAGS_RESET_SF: + return "RESET_SF" + case X86_EFLAGS_RESET_AF: + return "RESET_AF" + case X86_EFLAGS_RESET_TF: + return "RESET_TF" + case X86_EFLAGS_RESET_NT: + return "RESET_NT" + case X86_EFLAGS_PRIOR_OF: + return "PRIOR_OF" + case X86_EFLAGS_PRIOR_SF: + return "PRIOR_SF" + case X86_EFLAGS_PRIOR_ZF: + return "PRIOR_ZF" + case X86_EFLAGS_PRIOR_AF: + return "PRIOR_AF" + case X86_EFLAGS_PRIOR_PF: + return "PRIOR_PF" + case X86_EFLAGS_PRIOR_CF: + return "PRIOR_CF" + case X86_EFLAGS_PRIOR_TF: + return "PRIOR_TF" + case X86_EFLAGS_PRIOR_IF: + return "PRIOR_IF" + case X86_EFLAGS_PRIOR_DF: + return "PRIOR_DF" + case X86_EFLAGS_TEST_NT: + return "TEST_NT" + case X86_EFLAGS_TEST_DF: + return "TEST_DF" + case X86_EFLAGS_RESET_PF: + return "RESET_PF" + case X86_EFLAGS_PRIOR_NT: + return "PRIOR_NT" + case X86_EFLAGS_MODIFY_TF: + return "MOD_TF" + case X86_EFLAGS_MODIFY_IF: + return "MOD_IF" + case X86_EFLAGS_MODIFY_DF: + return "MOD_DF" + case X86_EFLAGS_MODIFY_NT: + return "MOD_NT" + case X86_EFLAGS_MODIFY_RF: + return "MOD_RF" + case X86_EFLAGS_SET_CF: + return "SET_CF" + case X86_EFLAGS_SET_DF: + return "SET_DF" + case X86_EFLAGS_SET_IF: + return "SET_IF" + } +} + +func getFPUFlagName(flag uint64) string { + switch flag { + default: + return "" + case X86_FPU_FLAGS_MODIFY_C0: + return "MOD_C0" + case X86_FPU_FLAGS_MODIFY_C1: + return "MOD_C1" + case X86_FPU_FLAGS_MODIFY_C2: + return "MOD_C2" + case X86_FPU_FLAGS_MODIFY_C3: + return "MOD_C3" + case X86_FPU_FLAGS_RESET_C0: + return "RESET_C0" + case X86_FPU_FLAGS_RESET_C1: + return "RESET_C1" + case X86_FPU_FLAGS_RESET_C2: + return "RESET_C2" + case X86_FPU_FLAGS_RESET_C3: + return "RESET_C3" + case X86_FPU_FLAGS_SET_C0: + return "SET_C0" + case X86_FPU_FLAGS_SET_C1: + return "SET_C1" + case X86_FPU_FLAGS_SET_C2: + return "SET_C2" + case X86_FPU_FLAGS_SET_C3: + return "SET_C3" + case X86_FPU_FLAGS_UNDEFINED_C0: + return "UNDEF_C0" + case X86_FPU_FLAGS_UNDEFINED_C1: + return "UNDEF_C1" + case X86_FPU_FLAGS_UNDEFINED_C2: + return "UNDEF_C2" + case X86_FPU_FLAGS_UNDEFINED_C3: + return "UNDEF_C3" + case X86_FPU_FLAGS_TEST_C0: + return "TEST_C0" + case X86_FPU_FLAGS_TEST_C1: + return "TEST_C1" + case X86_FPU_FLAGS_TEST_C2: + return "TEST_C2" + case X86_FPU_FLAGS_TEST_C3: + return "TEST_C3" + } +} + func x86InsnDetail(insn Instruction, engine *Engine, buf *bytes.Buffer) { fmt.Fprintf(buf, "\tPrefix:") dumpHex(insn.X86.Prefix, buf) @@ -27,7 +173,18 @@ func x86InsnDetail(insn Instruction, engine *Engine, buf *bytes.Buffer) { fmt.Fprintf(buf, "\trex: 0x%x\n", insn.X86.Rex) fmt.Fprintf(buf, "\taddr_size: %v\n", insn.X86.AddrSize) fmt.Fprintf(buf, "\tmodrm: 0x%x\n", insn.X86.ModRM) - fmt.Fprintf(buf, "\tdisp: 0x%x\n", uint32(insn.X86.Disp)) + if insn.X86.Encoding.ModRMOffset != 0 { + fmt.Fprintf(buf, "\tmodrm_offset: 0x%x\n", insn.X86.Encoding.ModRMOffset) + } + + fmt.Fprintf(buf, "\tdisp: 0x%x\n", uint64(insn.X86.Disp)) + if insn.X86.Encoding.DispOffset != 0 { + fmt.Fprintf(buf, "\tdisp_offset: 0x%x\n", insn.X86.Encoding.DispOffset) + } + + if insn.X86.Encoding.DispSize != 0 { + fmt.Fprintf(buf, "\tdisp_size: 0x%x\n", insn.X86.Encoding.DispSize) + } // SIB is not available in 16-bit mode if (engine.Mode() & CS_MODE_16) == 0 { @@ -42,6 +199,12 @@ func x86InsnDetail(insn Instruction, engine *Engine, buf *bytes.Buffer) { ) } } + + // XOP code condition + if insn.X86.XopCC != X86_XOP_CC_INVALID { + fmt.Fprintf(buf, "\txop_cc: %v\n", insn.X86.XopCC) + } + // SSE code condition if insn.X86.SseCC != X86_SSE_CC_INVALID { fmt.Fprintf(buf, "\tsse_cc: %v\n", insn.X86.SseCC) @@ -62,15 +225,20 @@ func x86InsnDetail(insn Instruction, engine *Engine, buf *bytes.Buffer) { fmt.Fprintf(buf, "\tavx_rm: %v\n", insn.X86.AvxRM) } + // Print out all immediate operands if immcount := insn.X86.OpCount(X86_OP_IMM); immcount > 0 { fmt.Fprintf(buf, "\timm_count: %v\n", immcount) pos := 1 for _, op := range insn.X86.Operands { if op.Type == X86_OP_IMM { - fmt.Fprintf( - buf, - "\t\timms[%v]: 0x%x\n", pos, uint64(op.Imm), - ) + fmt.Fprintf(buf, "\t\timms[%v]: 0x%x\n", pos, uint64(op.Imm)) + if insn.X86.Encoding.ImmOffset != 0 { + fmt.Fprintf(buf, "\timm_offset: 0x%x\n", insn.X86.Encoding.ImmOffset) + } + + if insn.X86.Encoding.ImmSize != 0 { + fmt.Fprintf(buf, "\timm_size: 0x%x\n", insn.X86.Encoding.ImmSize) + } pos++ } } @@ -80,14 +248,13 @@ func x86InsnDetail(insn Instruction, engine *Engine, buf *bytes.Buffer) { fmt.Fprintf(buf, "\top_count: %v\n", oplen) } + // Print out all operands for i, op := range insn.X86.Operands { switch op.Type { case X86_OP_REG: fmt.Fprintf(buf, "\t\toperands[%v].type: REG = %v\n", i, engine.RegName(op.Reg)) case X86_OP_IMM: fmt.Fprintf(buf, "\t\toperands[%v].type: IMM = 0x%x\n", i, (uint64(op.Imm))) - case X86_OP_FP: - fmt.Fprintf(buf, "\t\toperands[%v].type: FP = %f\n", i, op.FP) case X86_OP_MEM: fmt.Fprintf(buf, "\t\toperands[%v].type: MEM\n", i) if op.Mem.Segment != X86_REG_INVALID { @@ -121,6 +288,50 @@ func x86InsnDetail(insn Instruction, engine *Engine, buf *bytes.Buffer) { fmt.Fprintf(buf, "\t\toperands[%v].size: %v\n", i, op.Size) + switch op.Access { + case CS_AC_READ: + fmt.Fprintf(buf, "\t\toperands[%v].access: READ\n", i) + case CS_AC_WRITE: + fmt.Fprintf(buf, "\t\toperands[%v].access: WRITE\n", i) + case CS_AC_READ | CS_AC_WRITE: + fmt.Fprintf(buf, "\t\toperands[%v].access: READ | WRITE\n", i) + } + } + + if len(insn.AllRegistersRead) > 0 { + fmt.Fprintf(buf, "\tRegisters read:") + for _, reg := range insn.AllRegistersRead { + fmt.Fprintf(buf, " %s", engine.RegName(reg)) + } + fmt.Fprintf(buf, "\n") + } + + if len(insn.AllRegistersWritten) > 0 { + fmt.Fprintf(buf, "\tRegisters modified:") + for _, reg := range insn.AllRegistersWritten { + fmt.Fprintf(buf, " %s", engine.RegName(reg)) + } + fmt.Fprintf(buf, "\n") + } + + if insn.X86.EFlags != 0 { + fmt.Fprintf(buf, "\tEFLAGS:") + for i := uint(0); i <= 63; i++ { + if insn.X86.EFlags&uint64(1<