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treadmill.map.rpt
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treadmill.map.rpt
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Analysis & Synthesis report for treadmill
Sun Feb 12 23:22:54 2012
Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Registers Removed During Synthesis
9. General Register Statistics
10. Multiplexer Restructuring Statistics (Restructuring Performed)
11. Port Connectivity Checks: "modify_slope:slope_control"
12. Elapsed Time Per Partition
13. Analysis & Synthesis Messages
14. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Feb 12 23:22:54 2012 ;
; Quartus II Version ; 11.0 Build 208 07/03/2011 SP 1 SJ Full Version ;
; Revision Name ; treadmill ;
; Top-level Entity Name ; treadmill ;
; Family ; Cyclone II ;
; Total logic elements ; 291 ;
; Total combinational functions ; 276 ;
; Dedicated logic registers ; 154 ;
; Total registers ; 154 ;
; Total pins ; 107 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C35F672C6 ; ;
; Top-level entity name ; treadmill ; treadmill ;
; Family name ; Cyclone II ; Cyclone IV GX ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 2 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2 processors ; 0.0% ;
+----------------------------+-------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------+
; treadmill.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/Administrator/Desktop/assignment_2/treadmill.v ;
; timer.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/Administrator/Desktop/assignment_2/timer.v ;
; slow_clock.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/Administrator/Desktop/assignment_2/slow_clock.v ;
; distance.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/Administrator/Desktop/assignment_2/distance.v ;
; modify_speed.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/Administrator/Desktop/assignment_2/modify_speed.v ;
; modify_slope.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/Administrator/Desktop/assignment_2/modify_slope.v ;
; dist_clock.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/Administrator/Desktop/assignment_2/dist_clock.v ;
; motor.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/Administrator/Desktop/assignment_2/motor.v ;
; hex_display.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/Administrator/Desktop/assignment_2/hex_display.v ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------+
+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------+
; Resource ; Usage ;
+---------------------------------------------+----------+
; Estimated Total logic elements ; 291 ;
; ; ;
; Total combinational functions ; 276 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 116 ;
; -- 3 input functions ; 44 ;
; -- <=2 input functions ; 116 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 182 ;
; -- arithmetic mode ; 94 ;
; ; ;
; Total registers ; 154 ;
; -- Dedicated logic registers ; 154 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 107 ;
; Maximum fan-out node ; CLOCK_50 ;
; Maximum fan-out ; 136 ;
; Total fan-out ; 1323 ;
; Average fan-out ; 2.46 ;
+---------------------------------------------+----------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------+--------------+
; |treadmill ; 276 (28) ; 154 (29) ; 0 ; 0 ; 0 ; 0 ; 107 ; 0 ; |treadmill ; ;
; |dist_clock:d_clock| ; 42 (42) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |treadmill|dist_clock:d_clock ; ;
; |distance:dist1| ; 1 (1) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |treadmill|distance:dist1 ; ;
; |hex_display:dsp0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |treadmill|hex_display:dsp0 ; ;
; |hex_display:dsp1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |treadmill|hex_display:dsp1 ; ;
; |hex_display:dsp2| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |treadmill|hex_display:dsp2 ; ;
; |hex_display:dsp3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |treadmill|hex_display:dsp3 ; ;
; |hex_display:dsp4| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |treadmill|hex_display:dsp4 ; ;
; |hex_display:dsp6| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |treadmill|hex_display:dsp6 ; ;
; |hex_display:dsp7| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |treadmill|hex_display:dsp7 ; ;
; |modify_slope:slope_control| ; 28 (28) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |treadmill|modify_slope:slope_control ; ;
; |modify_speed:speed_control| ; 51 (51) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |treadmill|modify_speed:speed_control ; ;
; |motor:pmw| ; 16 (16) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |treadmill|motor:pmw ; ;
; |slow_clock:s_clock| ; 35 (35) ; 27 (27) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |treadmill|slow_clock:s_clock ; ;
; |timer:time1| ; 26 (26) ; 15 (15) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |treadmill|timer:time1 ; ;
+---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------+----------------------------------------+
; motor:pmw|lights[8] ; Stuck at GND due to stuck port data_in ;
; display5[0,1,3] ; Stuck at VCC due to stuck port data_in ;
; distance:dist1|distance1[1..3] ; Stuck at GND due to stuck port data_in ;
; distance:dist1|distance1[0] ; Stuck at VCC due to stuck port data_in ;
; timer:time1|second1[3] ; Stuck at GND due to stuck port data_in ;
; distance:dist1|distance2[0,3] ; Stuck at VCC due to stuck port data_in ;
; distance:dist1|distance2[1] ; Stuck at GND due to stuck port data_in ;
; distance:dist1|distance2[2] ; Stuck at VCC due to stuck port data_in ;
; distance:dist1|distance3[3] ; Stuck at VCC due to stuck port data_in ;
; Total Number of Removed Registers = 14 ; ;
+----------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 154 ;
; Number of registers using Synchronous Clear ; 73 ;
; Number of registers using Synchronous Load ; 7 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 40 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+-------------------------------------------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+-------------------------------------------------+----------------------------+
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; |treadmill|timer:time1|second2[0] ; ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; |treadmill|distance:dist1|distance2[1] ; ;
; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; |treadmill|timer:time1|second1[0] ; ;
; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; |treadmill|distance:dist1|distance3[3] ; ;
; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; |treadmill|timer:time1|minute1[0] ; ;
; 6:1 ; 4 bits ; 16 LEs ; 4 LEs ; 12 LEs ; |treadmill|timer:time1|minute2[0] ; ;
; 7:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; |treadmill|modify_slope:slope_control|slope1[1] ; ;
; 8:1 ; 4 bits ; 20 LEs ; 4 LEs ; 16 LEs ; |treadmill|modify_speed:speed_control|speed1[3] ; ;
; 8:1 ; 4 bits ; 20 LEs ; 8 LEs ; 12 LEs ; |treadmill|modify_slope:slope_control|slope2[3] ; ;
; 9:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; |treadmill|modify_speed:speed_control|speed3[2] ; ;
; 9:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; |treadmill|modify_speed:speed_control|speed2[2] ; ;
; 9:1 ; 8 bits ; 48 LEs ; 0 LEs ; 48 LEs ; |treadmill|modify_speed:speed_control|speed[2] ; ;
+--------------------+-----------+---------------+----------------------+------------------------+-------------------------------------------------+----------------------------+
+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "modify_slope:slope_control" ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; slope ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:01 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
Info: Processing started: Sun Feb 12 23:22:47 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off treadmill -c treadmill
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Warning: Can't analyze file -- file hex_7seg.v is missing
Warning (10229): Verilog HDL Expression warning at treadmill.v(103): truncated literal to match 3 bits
Warning (10229): Verilog HDL Expression warning at treadmill.v(114): truncated literal to match 3 bits
Info: Found 1 design units, including 1 entities, in source file treadmill.v
Info: Found entity 1: treadmill
Info: Found 1 design units, including 1 entities, in source file timer.v
Info: Found entity 1: timer
Info: Found 1 design units, including 1 entities, in source file slow_clock.v
Info: Found entity 1: slow_clock
Warning (10229): Verilog HDL Expression warning at distance.v(8): truncated literal to match 3 bits
Info: Found 1 design units, including 1 entities, in source file distance.v
Info: Found entity 1: distance
Info: Found 1 design units, including 1 entities, in source file modify_speed.v
Info: Found entity 1: modify_speed
Info: Found 1 design units, including 1 entities, in source file modify_slope.v
Info: Found entity 1: modify_slope
Info: Found 1 design units, including 1 entities, in source file dist_clock.v
Info: Found entity 1: dist_clock
Info: Found 1 design units, including 1 entities, in source file motor.v
Info: Found entity 1: motor
Info: Found 1 design units, including 1 entities, in source file hex_display.v
Info: Found entity 1: hex_display
Info: Elaborating entity "treadmill" for the top level hierarchy
Warning (10034): Output port "LEDR[17..9]" at treadmill.v(10) has no driver
Info: Elaborating entity "slow_clock" for hierarchy "slow_clock:s_clock"
Warning (10230): Verilog HDL assignment warning at slow_clock.v(12): truncated value with size 32 to match size of target (26)
Info: Elaborating entity "dist_clock" for hierarchy "dist_clock:d_clock"
Warning (10230): Verilog HDL assignment warning at dist_clock.v(11): truncated value with size 32 to match size of target (31)
Info: Elaborating entity "timer" for hierarchy "timer:time1"
Info: Elaborating entity "distance" for hierarchy "distance:dist1"
Warning (10036): Verilog HDL or VHDL warning at distance.v(8): object "dash" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at distance.v(12): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at distance.v(16): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at distance.v(22): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "modify_speed" for hierarchy "modify_speed:speed_control"
Warning (10230): Verilog HDL assignment warning at modify_speed.v(21): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at modify_speed.v(22): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at modify_speed.v(26): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at modify_speed.v(27): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at modify_speed.v(33): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at modify_speed.v(34): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at modify_speed.v(40): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at modify_speed.v(41): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at modify_speed.v(45): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at modify_speed.v(46): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at modify_speed.v(52): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at modify_speed.v(53): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "modify_slope" for hierarchy "modify_slope:slope_control"
Warning (10230): Verilog HDL assignment warning at modify_slope.v(19): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at modify_slope.v(20): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at modify_slope.v(25): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at modify_slope.v(26): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at modify_slope.v(32): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at modify_slope.v(33): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at modify_slope.v(38): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at modify_slope.v(39): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "motor" for hierarchy "motor:pmw"
Warning (10230): Verilog HDL assignment warning at motor.v(11): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "hex_display" for hierarchy "hex_display:dsp0"
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "HEX5[0]" is stuck at VCC
Warning (13410): Pin "HEX5[1]" is stuck at VCC
Warning (13410): Pin "HEX5[5]" is stuck at VCC
Warning (13410): Pin "LEDG[8]" is stuck at GND
Warning (13410): Pin "LEDR[8]" is stuck at GND
Warning (13410): Pin "LEDR[9]" is stuck at GND
Warning (13410): Pin "LEDR[10]" is stuck at GND
Warning (13410): Pin "LEDR[11]" is stuck at GND
Warning (13410): Pin "LEDR[12]" is stuck at GND
Warning (13410): Pin "LEDR[13]" is stuck at GND
Warning (13410): Pin "LEDR[14]" is stuck at GND
Warning (13410): Pin "LEDR[15]" is stuck at GND
Warning (13410): Pin "LEDR[16]" is stuck at GND
Warning (13410): Pin "LEDR[17]" is stuck at GND
Info: Generated suppressed messages file C:/Documents and Settings/Administrator/Desktop/assignment_2/treadmill.map.smsg
Info: Generating hard_block partition "hard_block:auto_generated_inst"
Warning: Design contains 16 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "CLOCK_27"
Warning (15610): No output dependent on input pin "SW[1]"
Warning (15610): No output dependent on input pin "SW[2]"
Warning (15610): No output dependent on input pin "SW[3]"
Warning (15610): No output dependent on input pin "SW[4]"
Warning (15610): No output dependent on input pin "SW[5]"
Warning (15610): No output dependent on input pin "SW[6]"
Warning (15610): No output dependent on input pin "SW[7]"
Warning (15610): No output dependent on input pin "SW[8]"
Warning (15610): No output dependent on input pin "SW[9]"
Warning (15610): No output dependent on input pin "SW[10]"
Warning (15610): No output dependent on input pin "SW[11]"
Warning (15610): No output dependent on input pin "SW[12]"
Warning (15610): No output dependent on input pin "SW[13]"
Warning (15610): No output dependent on input pin "SW[14]"
Warning (15610): No output dependent on input pin "SW[15]"
Info: Implemented 399 device resources after synthesis - the final resource count might be different
Info: Implemented 24 input pins
Info: Implemented 83 output pins
Info: Implemented 292 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 64 warnings
Info: Peak virtual memory: 239 megabytes
Info: Processing ended: Sun Feb 12 23:22:54 2012
Info: Elapsed time: 00:00:07
Info: Total CPU time (on all processors): 00:00:07
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/Documents and Settings/Administrator/Desktop/assignment_2/treadmill.map.smsg.