@@ -2070,13 +2070,13 @@ static void scic_sds_controller_afe_initialization(struct scic_sds_controller *s
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writel (0x00005500 , & scic -> scu_registers -> afe .afe_bias_control );
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else if (is_a2 ())
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writel (0x00005A00 , & scic -> scu_registers -> afe .afe_bias_control );
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- else if (is_b0 ())
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+ else if (is_b0 () || is_c0 () )
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writel (0x00005F00 , & scic -> scu_registers -> afe .afe_bias_control );
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udelay (AFE_REGISTER_WRITE_DELAY );
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/* Enable PLL */
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- if (is_b0 ())
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+ if (is_b0 () || is_c0 () )
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writel (0x80040A08 , & scic -> scu_registers -> afe .afe_pll_control0 );
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else
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writel (0x80040908 , & scic -> scu_registers -> afe .afe_pll_control0 );
@@ -2102,6 +2102,16 @@ static void scic_sds_controller_afe_initialization(struct scic_sds_controller *s
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/* Configure transmitter SSC parameters */
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writel (0x00030000 , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_tx_ssc_control );
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udelay (AFE_REGISTER_WRITE_DELAY );
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+ } else if (is_c0 ()) {
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+ /* Configure transmitter SSC parameters */
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+ writel (0x0003000 , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_tx_ssc_control );
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+ udelay (AFE_REGISTER_WRITE_DELAY );
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+
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+ /*
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+ * All defaults, except the Receive Word Alignament/Comma Detect
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+ * Enable....(0xe800) */
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+ writel (0x00004500 , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_xcvr_control0 );
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+ udelay (AFE_REGISTER_WRITE_DELAY );
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} else {
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/*
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* All defaults, except the Receive Word Alignament/Comma Detect
@@ -2120,15 +2130,23 @@ static void scic_sds_controller_afe_initialization(struct scic_sds_controller *s
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writel (0x000003D4 , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_channel_control );
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else if (is_a2 ())
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writel (0x000003F0 , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_channel_control );
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- else {
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+ else if ( is_b0 ()) {
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/* Power down TX and RX (PWRDNTX and PWRDNRX) */
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- writel (0x000003d7 , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_channel_control );
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+ writel (0x000003D7 , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_channel_control );
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+ udelay (AFE_REGISTER_WRITE_DELAY );
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+
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+ /*
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+ * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
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+ * & increase TX int & ext bias 20%....(0xe85c) */
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+ writel (0x000003D4 , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_channel_control );
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+ } else {
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+ writel (0x000001E7 , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_channel_control );
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udelay (AFE_REGISTER_WRITE_DELAY );
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/*
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* Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
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* & increase TX int & ext bias 20%....(0xe85c) */
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- writel (0x000003d4 , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_channel_control );
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+ writel (0x000001E4 , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_channel_control );
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}
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udelay (AFE_REGISTER_WRITE_DELAY );
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@@ -2149,12 +2167,22 @@ static void scic_sds_controller_afe_initialization(struct scic_sds_controller *s
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writel (0x3F09983F , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_rx_ssc_control0 );
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else if (is_a2 ())
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writel (0x3F11103F , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_rx_ssc_control0 );
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- else {
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+ else if ( is_b0 ()) {
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writel (0x3F11103F , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_rx_ssc_control0 );
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udelay (AFE_REGISTER_WRITE_DELAY );
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+ /* Enable TX equalization (0xe824) */
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+ writel (0x00040000 , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_tx_control );
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+ } else {
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+ writel (0x0140DF0F , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_rx_ssc_control1 );
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+ udelay (AFE_REGISTER_WRITE_DELAY );
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+
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+ writel (0x3F6F103F , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_rx_ssc_control0 );
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+ udelay (AFE_REGISTER_WRITE_DELAY );
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+
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/* Enable TX equalization (0xe824) */
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writel (0x00040000 , & scic -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_tx_control );
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}
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+
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udelay (AFE_REGISTER_WRITE_DELAY );
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writel (oem_phy -> afe_tx_amp_control0 ,
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