Request for developer notes/docs for AVR target backend

[anubane]

This is neither a bug report nor any issue pertaining to the upstream (LLVM) codebase.

I wish to understand the process and implementation workflow for AVR target backend for LLVM. Since the repository itself does not contain any documentation, this is a request for just the same.

an example of things that the docs/notes may explain: in the file AVRRegisterInfo.td

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//===----------------------------------------------------------------------===//
//  Declarations that describe the AVR register file
//===----------------------------------------------------------------------===//

// 8-bit General purpose register definition.
class AVRReg<bits<16> num, string name, list<Register> subregs = [],
             list<string> altNames = []> : RegisterWithSubRegs<name, subregs> {
  field bits<16> Num = num;

  let HWEncoding = num;
  let Namespace = "AVR";
  let SubRegs = subregs;
  let AltNames = altNames;
}
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def R26 : AVRReg<26, "r26", [], ["xl"]>, DwarfRegNum<[26]>;
def R27 : AVRReg<27, "r27", [], ["xh"]>, DwarfRegNum<[27]>;
def R28 : AVRReg<28, "r28", [], ["yl"]>, DwarfRegNum<[28]>;
def R29 : AVRReg<29, "r29", [], ["yh"]>, DwarfRegNum<[29]>;
def R30 : AVRReg<30, "r30", [], ["zl"]>, DwarfRegNum<[30]>;
def R31 : AVRReg<31, "r31", [], ["zh"]>, DwarfRegNum<[31]>;
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Now, as per all architecture documents I can find for Atmel AVR, I do not understand what are the subregisters. So the design process in the TableGen is not clear to me. These details may be covered by some developer notes/documentations.