From 23ecab317127442411fc5ad5c7f9a3ab4f7439b2 Mon Sep 17 00:00:00 2001 From: Xiao <79354981+owlxiao@users.noreply.github.com> Date: Mon, 5 Dec 2022 23:21:11 +0800 Subject: [PATCH] [Capstone2llvmir] Update to Capstone V5 (#1059) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Update Capstone to v4.0 * [Capstone-next] Update to capstone-next branch * [Capstone-next] Update to Capstone-Next Branch -[ARM] -Add ARM_INS_MOVS support -[ARM64] -Remove vess. -It overlaps with ARM64_VAS -Fix A64SysReg_* into ARM64_SYSREG_* -[PowerPC] -Fix PPC_REG_X2 into PPC_REG_XER -[X86] -Remove X86_INS_FADDP -In capstone-next, faddp is actually fadd, both belong to "ID 15(fadd)" * [tests][capstone2llvmir][arm] Fix MOVW Unit Test - In test, "movw r0, #0xabcd" do not read any register and the result is 0xabcd not 0x1234abcd * [tests][capstone2llvmir][arm] Fix Nop test - In arm, the NOP instruction is HINT instruction - Also, in capstone, the cs_insn->id of nop is point to HINT(ID: 63) - So, an error will be occurred when looking for a translate instruction method because it is points to nullptr * [Capstone2llvmir][arm64] Add ADDCS Support * [capstone2llvmir][arm64] Add ADDS Support * [capstone2llvmir][arm64] Add ANDS Support * [capstone2llvmir][arm64] Add SUP Support * [capstone2llvmir][arm64] Add BICS Support * [capstonellvmir][PowerPC] Update Register Name * [capstone2llvmir][PowerPC] Update Register Name * [capstone2llvmir][PowerPC] Fix CMP Support * [capstone2llvmir][PowerPC] Add CMPL Support * [capstone2llvmir][PowerPC] Fix CMPL * [capstone2llvmir][PowerPC] Add BLT Support * [capstone2llvmir][PowerPC] Add Branch mnemonics incorporating conditions Suppport * [capstone2llvmir][PowerPC] Fix RLWINM - RLWINM and clrlwi are same ID * [tests][capstone2llvmir][PowerPC] Fix Crand Tests * [capstone2llvmir][PowerPC] Fix bdzla BUG * [capstone2llvmir][PowerPC] Remove BDZLA TODO * [capstone2llvmir][x86] Fix ud2b * [capstone2llvmir][X86] Fix FADD/FADDP * [capstone2llvmir][x86] Fix FADD/FADDP * [capstone2llvmir][x86] Fix FXCH - when transalte "FXCH instruction, in the value of loadOpFloatingBinaryTop Function, "top" is equal to idx, which causes the value to be written to top twice when exchanging data. * clean code * Update Capstone to v5.0 * [capstone2llvmir][x86][PowerPC] Clean code * [capstone2llvmir][PowerPC] Clean code * [capstone2llvmir][PowerPC] Remove BUN* and BNU* -In CapstoneV5, they are both equivalent to BSO* and BNS* * [capstone2llvmir][PowerPC] Fix rlwinm - In capstone V5, rlwinm is equivalent to to clrlwi * [capstone2llvmir][PowerPC] Fix BNL* * [capstone2llvmir][PowerPC] Add PPC_REG_ZERO * [capstone2llvmir][PowerPC] Add comment * Fix merge conflict * Update YARA to 4.2.X * Add dll_name from export directory to output * llvm/CMakeLists: Manually-specified variables were not used by the project. The following variables were set in CMakeLists, however, they were not used by the LLVM project build: LLVM_USE_CRT_DEBUG LLVM_USE_CRT_RELEASE * CHANGELOG.md: add entries for #1060 #1061 PRs * Fixed loading import directory that is modified by relocations * Fixed comment * Remove useless trailing whitespace There is absolutely no reason for it being in the code. * pelib: Fix a typo in a comment in PeLib::ImageLoader::Load() * Add a CHANGELOG entry for #1063 * Move signing certificate to separate object * Updated authenticode parser to the newest version * Fix uninitialize free, use finer sanity checks in auth. parser * Add a directory for RetDec-related publications The list of publications has been originally placed on https://retdec.com/publications/ (https://retdec.com/ has been redirected to https://github.com/avast/retdec, and we wanted to keep the list somewhere). * Fix the wording for an invalid max-memory error in scripts/retdec-unpacker.py There are the following two reasons for the fix: - The check only verifies whether the passed value is an integer. - The parameter can be 0 (i.e. a non-negative integer). It does not have to a positive integer. * Never try to limit memory on macOS We can't limit memory on macOS. Before macOS 12 limitSystemMemoryOnPOSIX() does not actually do anything on macOS. Anyway, it just succeed, since macOS 12 it returns error and retdec can't start. To be honest Apple can control memmory limit via so-called the ledger() system call which is private. An old verison which was opened to OpenSource (from 10.9-10.10?) using setrlimit() but at some point setrlimit() was broken and not ledger(). Probably at macOS 12 the setrlimit() was completley broken. Because we haven't got any other choose just return true which haven't change anything. See: https://github.com/avast/retdec/issues/379 Fixes: https://github.com/avast/retdec/issues/1045 * Remove a redundant period from CHANGELOG * utils: Improve the wording of a comment in getTotalSystemMemoryOnMacOS() * Add a CHANGELOG entry for #1074 and #1045 * Update authenticode-parser, use-after-free, signedness issues * Using multistage build for Dockerfile, reduces container size by ~1.5G * Check for possible overflow when checking for segment overlaps. Fix incorrect range exception message * Fix parameter and return types for dynamically called functions Calls to dynamically-linked functions go through the procedure linkage table (PLT). RetDec turns a PLT entry into a function, say malloc@plt, that appears to do nothing but call the external function, say malloc (though the assembly code will do a jump rather than a call). User code that logically wants to call malloc instead calls malloc@plt (and sets up arguments as if calling malloc). The malloc@plt code first jumps to the dynamic linker which modifies it so that subsequent calls to malloc@plt will jump directly to malloc. We say that malloc@plt wraps malloc. The call to malloc in malloc@plt will not have any arguments setup, so malloc will appear to have no parameters or returns (unless that information is provided by link-time-information, debug information, or name demangling), but it needs to have the same parameter types and return type as malloc@plt. The propagateWrapped methods copy the argument information from the DataFlowEntry of the wrapping function to the wrapped function. Then, when the calls to the wrapping function are inlined (in connectWrappers), effectively the call to the wrapping function is changed into a call to the wrapped function. The motivation for this change is the programs that analyze the output of RetDec (either the C code, or the LLVM code) want to recognize library functions and treat them specially. This change makes it so that the library function names are used directly (rather than the plt version) and they are passed their parameters correctly. * Upgrade to Capstone release 4.0.2 * Add additional patch on capstone 4.0.2 for PPC Signed 16 bit immediates Capstone version 4.0.2 has a bug when disassembling a powerpc instruction with a signed 16-bit immediate. See https://github.com/capstone-engine/capstone/issues/1746 and https://github.com/capstone-engine/capstone/issues/1746#issuecomment-1186559582. This change adds to the capstone patch to fix this problem. * Treat endbr32/endbr64 instructions as NOPs * capstone2llvmir/powerpc: remove PPC_INS_BDZLA hack fix As Capstone was updated, the fix in https://github.com/capstone-engine/capstone/issues/968 took effect and the original RetDec fix is not needed - in fact, it caused problems. * Handle Procedure Linkage calls for 32bit x86 from gcc This case is for x86 32 bit compiled with GCC. Its PLT entries are in sections .plt.sec or .plt.got. An entry is of the form: jmp *offset(%ebx) When this code is encountered register %ebx has been loaded with the address of the start of the Global Offset Table (.got) section. This change handles that case. * Add ability to process PNG icons for perceptual hash calculation (#1090) * Add ability to process PNG icons for perceptual hash calculation * Use SCOPE_EXIT for deallocation * In generated C, add prototypes for dynamically-linked functions without headers When the program involves dynamically-linked functions like _Znwj (operator new) that return a pointer, it is necessary to have prototypes for them, since otherwise they will be implicitly deduced to return "int" which cannnot be dereferenced. Previously RetDec was emitting comments telling which functions were dynamically linked. This change moves them up before the functions are emitted and instead emits prototypes for the functions. However, RetDec also inserts includes of headers for functions for with know headers. We do not emit prototypes for functions with headers as that would be redundant. As a result, some dynamically-linked functions that used to show in the comments no longer appear as the included header will declare them. The section header comment for dynamically-linked functions is only produced if some prototypes are written for dynamically-linked functions. A related PR will have added tests as well as changes needed for existing tests. * Add printing of analysis time to retdec-fileinfo output * Yara: inherits linker flags * Use provided libtool via `CMAKE_LIBTOOL` * Added missed `${RETDEC_INSTALL_BIN_DIR}` to `pat2yara` * Added sanity check for page index when loading pages from broken samples There are certain samples where page index might go beyond available pages when trying to load them which will be prevented with this patch. * Virtual Size overflow is now handler properly * Fixed error code * Updated yaramod * Fix removeZeroSequences * README.md: add "limited maintenance mode" note Co-authored-by: Peter Kubov Co-authored-by: houndthe Co-authored-by: Peter Matula Co-authored-by: Ladislav Zezula Co-authored-by: Petr Zemek Co-authored-by: Marek Milkovič Co-authored-by: Kirill A. Korinsky Co-authored-by: me Co-authored-by: Richard L Ford Co-authored-by: 未赢 <26459963+neverwin@users.noreply.github.com> --- cmake/deps.cmake | 5 +- deps/capstone/CMakeLists.txt | 1 + .../capstone2llvmir/powerpc/powerpc_defs.h | 46 - src/capstone2llvmir/arm/arm_init.cpp | 1 + src/capstone2llvmir/arm64/arm64.cpp | 26 +- src/capstone2llvmir/arm64/arm64_init.cpp | 2265 +++++++++-------- src/capstone2llvmir/powerpc/powerpc.cpp | 427 ++-- src/capstone2llvmir/powerpc/powerpc_impl.h | 2 +- src/capstone2llvmir/powerpc/powerpc_init.cpp | 370 ++- src/capstone2llvmir/x86/x86.cpp | 22 +- src/capstone2llvmir/x86/x86_init.cpp | 178 +- tests/capstone2llvmir/arm_tests.cpp | 8 +- tests/capstone2llvmir/powerpc_tests.cpp | 1158 ++++----- tests/capstone2llvmir/x86_tests.cpp | 4 + 14 files changed, 2292 insertions(+), 2221 deletions(-) diff --git a/cmake/deps.cmake b/cmake/deps.cmake index a13664279..b88682eee 100644 --- a/cmake/deps.cmake +++ b/cmake/deps.cmake @@ -1,11 +1,10 @@ -# URL is for Capstone release 4.0.2. set(CAPSTONE_URL - "https://github.com/capstone-engine/capstone/archive/1d230532840a37ac032c6ab80128238fc930c6c1.zip" + "https://github.com/aquynh/capstone/archive/f049e65f596bf8b1cbf5f2371067e34715ef1764.zip" CACHE STRING "URL of Capstone archive to use." ) set(CAPSTONE_ARCHIVE_SHA256 - "659097fcda59ce927937f73dd87a4606de6e768b352045a077ed8d2165b7e935" + "87fe97225ee98220dcb5725bc470bc83a67819a6e75000075566c0423599437e" CACHE STRING "" ) diff --git a/deps/capstone/CMakeLists.txt b/deps/capstone/CMakeLists.txt index 32d4e5407..830345706 100644 --- a/deps/capstone/CMakeLists.txt +++ b/deps/capstone/CMakeLists.txt @@ -48,6 +48,7 @@ ExternalProject_Add(capstone-project "${CMAKE_C_COMPILER_OPTION}" "${CMAKE_CXX_COMPILER_OPTION}" -DCMAKE_POSITION_INDEPENDENT_CODE=${CMAKE_POSITION_INDEPENDENT_CODE} + -DCAPSTONE_INSTALL=ON -DCMAKE_LIBTOOL=${CMAKE_LIBTOOL} # Patch the Capstone sources. PATCH_COMMAND diff --git a/include/retdec/capstone2llvmir/powerpc/powerpc_defs.h b/include/retdec/capstone2llvmir/powerpc/powerpc_defs.h index a53d5a35a..fd209f6ef 100644 --- a/include/retdec/capstone2llvmir/powerpc/powerpc_defs.h +++ b/include/retdec/capstone2llvmir/powerpc/powerpc_defs.h @@ -7,52 +7,6 @@ #ifndef RETDEC_CAPSTONE2LLVMIR_POWERPC_POWERPC_DEFS_H #define RETDEC_CAPSTONE2LLVMIR_POWERPC_POWERPC_DEFS_H -enum ppc_reg_cr_flags -{ - /// Negative -- set when result is negative. - PPC_REG_CR0_LT = PPC_REG_ENDING + 1, - /// Positive -- set when result is positive and not zero. - PPC_REG_CR0_GT, - /// Zero -- set when result is zero - PPC_REG_CR0_EQ, - /// Copy of the final state of XER[SO] at the completion of the instruction. - PPC_REG_CR0_SO, - - PPC_REG_CR1_LT, - PPC_REG_CR1_GT, - PPC_REG_CR1_EQ, - PPC_REG_CR1_SO, - - PPC_REG_CR2_LT, - PPC_REG_CR2_GT, - PPC_REG_CR2_EQ, - PPC_REG_CR2_SO, - - PPC_REG_CR3_LT, - PPC_REG_CR3_GT, - PPC_REG_CR3_EQ, - PPC_REG_CR3_SO, - - PPC_REG_CR4_LT, - PPC_REG_CR4_GT, - PPC_REG_CR4_EQ, - PPC_REG_CR4_SO, - - PPC_REG_CR5_LT, - PPC_REG_CR5_GT, - PPC_REG_CR5_EQ, - PPC_REG_CR5_SO, - - PPC_REG_CR6_LT, - PPC_REG_CR6_GT, - PPC_REG_CR6_EQ, - PPC_REG_CR6_SO, - - PPC_REG_CR7_LT, - PPC_REG_CR7_GT, - PPC_REG_CR7_EQ, - PPC_REG_CR7_SO, -}; enum ppc_cr_types { diff --git a/src/capstone2llvmir/arm/arm_init.cpp b/src/capstone2llvmir/arm/arm_init.cpp index 8e5b421fc..7d5c9e935 100644 --- a/src/capstone2llvmir/arm/arm_init.cpp +++ b/src/capstone2llvmir/arm/arm_init.cpp @@ -466,6 +466,7 @@ Capstone2LlvmIrTranslatorArm_impl::_i2fm = {ARM_INS_MLA, &Capstone2LlvmIrTranslatorArm_impl::translateMla}, {ARM_INS_MLS, &Capstone2LlvmIrTranslatorArm_impl::translateMls}, {ARM_INS_MOV, &Capstone2LlvmIrTranslatorArm_impl::translateMov}, + {ARM_INS_MOVS, &Capstone2LlvmIrTranslatorArm_impl::translateMov}, {ARM_INS_MOVT, &Capstone2LlvmIrTranslatorArm_impl::translateMovt}, {ARM_INS_MOVW, &Capstone2LlvmIrTranslatorArm_impl::translateMovw}, {ARM_INS_MRC, nullptr}, diff --git a/src/capstone2llvmir/arm64/arm64.cpp b/src/capstone2llvmir/arm64/arm64.cpp index a5e7c7e8d..090f97f1b 100644 --- a/src/capstone2llvmir/arm64/arm64.cpp +++ b/src/capstone2llvmir/arm64/arm64.cpp @@ -378,23 +378,35 @@ llvm::Value* Capstone2LlvmIrTranslatorArm64_impl::extractVectorValue( } // Vector element size specifier - switch(op.vess) + switch(op.vas) { - case ARM64_VESS_B: + case ARM64_VAS_16B: + case ARM64_VAS_8B : + case ARM64_VAS_4B : + case ARM64_VAS_1B : val = irb.CreateLShr(val, llvm::ConstantInt::get(val->getType(), 8 * op.vector_index)); return irb.CreateZExtOrTrunc(val, llvm::IntegerType::getInt8Ty(_module->getContext())); - case ARM64_VESS_H: + case ARM64_VAS_8H: + case ARM64_VAS_4H: + case ARM64_VAS_2H: + case ARM64_VAS_1H: val = irb.CreateLShr(val, llvm::ConstantInt::get(val->getType(), 16 * op.vector_index)); return irb.CreateZExtOrTrunc(val, llvm::IntegerType::getInt16Ty(_module->getContext())); - case ARM64_VESS_S: + case ARM64_VAS_4S: + case ARM64_VAS_2S: + case ARM64_VAS_1S: val = irb.CreateLShr(val, llvm::ConstantInt::get(val->getType(), 32 * op.vector_index)); val = irb.CreateZExtOrTrunc(val, llvm::IntegerType::getInt32Ty(_module->getContext())); return irb.CreateBitCast(val, llvm::Type::getFloatTy(_module->getContext())); - case ARM64_VESS_D: + case ARM64_VAS_1D: val = irb.CreateLShr(val, llvm::ConstantInt::get(val->getType(), 64 * op.vector_index)); val = irb.CreateZExtOrTrunc(val, llvm::IntegerType::getInt64Ty(_module->getContext())); return irb.CreateBitCast(val, llvm::Type::getDoubleTy(_module->getContext())); - case ARM64_VESS_INVALID: + case ARM64_VAS_1Q: + val = irb.CreateLShr(val, llvm::ConstantInt::get(val->getType(), 128 * op.vector_index)); + val = irb.CreateZExtOrTrunc(val, llvm::IntegerType::getInt128Ty(_module->getContext())); + return irb.CreateBitCast(val, llvm::Type::getFP128Ty(_module->getContext())); + case ARM64_VAS_INVALID: return val; default: throw GenericError("Arm64: extractVectorValue(): Unknown VESS type"); @@ -1775,7 +1787,7 @@ void Capstone2LlvmIrTranslatorArm64_impl::translateAnd(cs_insn* i, cs_arm64* ai, std::tie(op1, op2) = loadOpBinaryOrTernaryOp1Op2(ai, irb); op2 = irb.CreateZExtOrTrunc(op2, op1->getType()); - if (i->id == ARM64_INS_BIC) + if (i->id == ARM64_INS_BIC || i->id == ARM64_INS_BICS) { op2 = generateValueNegate(irb, op2); } diff --git a/src/capstone2llvmir/arm64/arm64_init.cpp b/src/capstone2llvmir/arm64/arm64_init.cpp index d0b0dbf4e..15e27198d 100644 --- a/src/capstone2llvmir/arm64/arm64_init.cpp +++ b/src/capstone2llvmir/arm64/arm64_init.cpp @@ -7,7 +7,6 @@ #include "capstone2llvmir/arm64/arm64_impl.h" #include -#include namespace retdec { namespace capstone2llvmir { @@ -34,578 +33,578 @@ void Capstone2LlvmIrTranslatorArm64_impl::initializeRegNameMap() {ARM64_REG_PC, "pc"}, // Program counter // SYSREGS - {A64SysReg_OSDTRRX_EL1, "osdtrrx_el1"}, - {A64SysReg_OSDTRTX_EL1, "osdtrtx_el1"}, - {A64SysReg_TEECR32_EL1, "teecr32_el1"}, - {A64SysReg_MDCCINT_EL1, "mdccint_el1"}, - {A64SysReg_MDSCR_EL1, "mdscr_el1"}, - {A64SysReg_DBGDTR_EL0, "dbgdtr_el0"}, - {A64SysReg_OSECCR_EL1, "oseccr_el1"}, - {A64SysReg_DBGVCR32_EL2, "dbgvcr32_el2"}, - {A64SysReg_DBGBVR0_EL1, "dbgbvr0_el1"}, - {A64SysReg_DBGBVR1_EL1, "dbgbvr1_el1"}, - {A64SysReg_DBGBVR2_EL1, "dbgbvr2_el1"}, - {A64SysReg_DBGBVR3_EL1, "dbgbvr3_el1"}, - {A64SysReg_DBGBVR4_EL1, "dbgbvr4_el1"}, - {A64SysReg_DBGBVR5_EL1, "dbgbvr5_el1"}, - {A64SysReg_DBGBVR6_EL1, "dbgbvr6_el1"}, - {A64SysReg_DBGBVR7_EL1, "dbgbvr7_el1"}, - {A64SysReg_DBGBVR8_EL1, "dbgbvr8_el1"}, - {A64SysReg_DBGBVR9_EL1, "dbgbvr9_el1"}, - {A64SysReg_DBGBVR10_EL1, "dbgbvr10_el1"}, - {A64SysReg_DBGBVR11_EL1, "dbgbvr11_el1"}, - {A64SysReg_DBGBVR12_EL1, "dbgbvr12_el1"}, - {A64SysReg_DBGBVR13_EL1, "dbgbvr13_el1"}, - {A64SysReg_DBGBVR14_EL1, "dbgbvr14_el1"}, - {A64SysReg_DBGBVR15_EL1, "dbgbvr15_el1"}, - {A64SysReg_DBGBCR0_EL1, "dbgbcr0_el1"}, - {A64SysReg_DBGBCR1_EL1, "dbgbcr1_el1"}, - {A64SysReg_DBGBCR2_EL1, "dbgbcr2_el1"}, - {A64SysReg_DBGBCR3_EL1, "dbgbcr3_el1"}, - {A64SysReg_DBGBCR4_EL1, "dbgbcr4_el1"}, - {A64SysReg_DBGBCR5_EL1, "dbgbcr5_el1"}, - {A64SysReg_DBGBCR6_EL1, "dbgbcr6_el1"}, - {A64SysReg_DBGBCR7_EL1, "dbgbcr7_el1"}, - {A64SysReg_DBGBCR8_EL1, "dbgbcr8_el1"}, - {A64SysReg_DBGBCR9_EL1, "dbgbcr9_el1"}, - {A64SysReg_DBGBCR10_EL1, "dbgbcr10_el1"}, - {A64SysReg_DBGBCR11_EL1, "dbgbcr11_el1"}, - {A64SysReg_DBGBCR12_EL1, "dbgbcr12_el1"}, - {A64SysReg_DBGBCR13_EL1, "dbgbcr13_el1"}, - {A64SysReg_DBGBCR14_EL1, "dbgbcr14_el1"}, - {A64SysReg_DBGBCR15_EL1, "dbgbcr15_el1"}, - {A64SysReg_DBGWVR0_EL1, "dbgwvr0_el1"}, - {A64SysReg_DBGWVR1_EL1, "dbgwvr1_el1"}, - {A64SysReg_DBGWVR2_EL1, "dbgwvr2_el1"}, - {A64SysReg_DBGWVR3_EL1, "dbgwvr3_el1"}, - {A64SysReg_DBGWVR4_EL1, "dbgwvr4_el1"}, - {A64SysReg_DBGWVR5_EL1, "dbgwvr5_el1"}, - {A64SysReg_DBGWVR6_EL1, "dbgwvr6_el1"}, - {A64SysReg_DBGWVR7_EL1, "dbgwvr7_el1"}, - {A64SysReg_DBGWVR8_EL1, "dbgwvr8_el1"}, - {A64SysReg_DBGWVR9_EL1, "dbgwvr9_el1"}, - {A64SysReg_DBGWVR10_EL1, "dbgwvr10_el1"}, - {A64SysReg_DBGWVR11_EL1, "dbgwvr11_el1"}, - {A64SysReg_DBGWVR12_EL1, "dbgwvr12_el1"}, - {A64SysReg_DBGWVR13_EL1, "dbgwvr13_el1"}, - {A64SysReg_DBGWVR14_EL1, "dbgwvr14_el1"}, - {A64SysReg_DBGWVR15_EL1, "dbgwvr15_el1"}, - {A64SysReg_DBGWCR0_EL1, "dbgwcr0_el1"}, - {A64SysReg_DBGWCR1_EL1, "dbgwcr1_el1"}, - {A64SysReg_DBGWCR2_EL1, "dbgwcr2_el1"}, - {A64SysReg_DBGWCR3_EL1, "dbgwcr3_el1"}, - {A64SysReg_DBGWCR4_EL1, "dbgwcr4_el1"}, - {A64SysReg_DBGWCR5_EL1, "dbgwcr5_el1"}, - {A64SysReg_DBGWCR6_EL1, "dbgwcr6_el1"}, - {A64SysReg_DBGWCR7_EL1, "dbgwcr7_el1"}, - {A64SysReg_DBGWCR8_EL1, "dbgwcr8_el1"}, - {A64SysReg_DBGWCR9_EL1, "dbgwcr9_el1"}, - {A64SysReg_DBGWCR10_EL1, "dbgwcr10_el1"}, - {A64SysReg_DBGWCR11_EL1, "dbgwcr11_el1"}, - {A64SysReg_DBGWCR12_EL1, "dbgwcr12_el1"}, - {A64SysReg_DBGWCR13_EL1, "dbgwcr13_el1"}, - {A64SysReg_DBGWCR14_EL1, "dbgwcr14_el1"}, - {A64SysReg_DBGWCR15_EL1, "dbgwcr15_el1"}, - {A64SysReg_TEEHBR32_EL1, "teehbr32_el1"}, - {A64SysReg_OSDLR_EL1, "osdlr_el1"}, - {A64SysReg_DBGPRCR_EL1, "dbgprcr_el1"}, - {A64SysReg_DBGCLAIMSET_EL1, "dbgclaimset_el1"}, - {A64SysReg_DBGCLAIMCLR_EL1, "dbgclaimclr_el1"}, - {A64SysReg_CSSELR_EL1, "csselr_el1"}, - {A64SysReg_VPIDR_EL2, "vpidr_el2"}, - {A64SysReg_VMPIDR_EL2, "vmpidr_el2"}, - {A64SysReg_SCTLR_EL1, "sctlr_el1"}, - {A64SysReg_SCTLR_EL2, "sctlr_el2"}, - {A64SysReg_SCTLR_EL3, "sctlr_el3"}, - {A64SysReg_ACTLR_EL1, "actlr_el1"}, - {A64SysReg_ACTLR_EL2, "actlr_el2"}, - {A64SysReg_ACTLR_EL3, "actlr_el3"}, - {A64SysReg_CPACR_EL1, "cpacr_el1"}, - {A64SysReg_HCR_EL2, "hcr_el2"}, - {A64SysReg_SCR_EL3, "scr_el3"}, - {A64SysReg_MDCR_EL2, "mdcr_el2"}, - {A64SysReg_SDER32_EL3, "sder32_el3"}, - {A64SysReg_CPTR_EL2, "cptr_el2"}, - {A64SysReg_CPTR_EL3, "cptr_el3"}, - {A64SysReg_HSTR_EL2, "hstr_el2"}, - {A64SysReg_HACR_EL2, "hacr_el2"}, - {A64SysReg_MDCR_EL3, "mdcr_el3"}, - {A64SysReg_TTBR0_EL1, "ttbr0_el1"}, - {A64SysReg_TTBR0_EL2, "ttbr0_el2"}, - {A64SysReg_TTBR0_EL3, "ttbr0_el3"}, - {A64SysReg_TTBR1_EL1, "ttbr1_el1"}, - {A64SysReg_TCR_EL1, "tcr_el1"}, - {A64SysReg_TCR_EL2, "tcr_el2"}, - {A64SysReg_TCR_EL3, "tcr_el3"}, - {A64SysReg_VTTBR_EL2, "vttbr_el2"}, - {A64SysReg_VTCR_EL2, "vtcr_el2"}, - {A64SysReg_DACR32_EL2, "dacr32_el2"}, - {A64SysReg_SPSR_EL1, "spsr_el1"}, - {A64SysReg_SPSR_EL2, "spsr_el2"}, - {A64SysReg_SPSR_EL3, "spsr_el3"}, - {A64SysReg_ELR_EL1, "elr_el1"}, - {A64SysReg_ELR_EL2, "elr_el2"}, - {A64SysReg_ELR_EL3, "elr_el3"}, - {A64SysReg_SP_EL0, "sp_el0"}, - {A64SysReg_SP_EL1, "sp_el1"}, - {A64SysReg_SP_EL2, "sp_el2"}, - {A64SysReg_SPSel, "spsel"}, - {A64SysReg_NZCV, "nzcv"}, - {A64SysReg_DAIF, "daif"}, - {A64SysReg_CurrentEL, "currentel"}, - {A64SysReg_SPSR_irq, "spsr_irq"}, - {A64SysReg_SPSR_abt, "spsr_abt"}, - {A64SysReg_SPSR_und, "spsr_und"}, - {A64SysReg_SPSR_fiq, "spsr_fiq"}, - {A64SysReg_FPCR, "fpcr"}, - {A64SysReg_FPSR, "fpsr"}, - {A64SysReg_DSPSR_EL0, "dspsr_el0"}, - {A64SysReg_DLR_EL0, "dlr_el0"}, - {A64SysReg_IFSR32_EL2, "ifsr32_el2"}, - {A64SysReg_AFSR0_EL1, "afsr0_el1"}, - {A64SysReg_AFSR0_EL2, "afsr0_el2"}, - {A64SysReg_AFSR0_EL3, "afsr0_el3"}, - {A64SysReg_AFSR1_EL1, "afsr1_el1"}, - {A64SysReg_AFSR1_EL2, "afsr1_el2"}, - {A64SysReg_AFSR1_EL3, "afsr1_el3"}, - {A64SysReg_ESR_EL1, "esr_el1"}, - {A64SysReg_ESR_EL2, "esr_el2"}, - {A64SysReg_ESR_EL3, "esr_el3"}, - {A64SysReg_FPEXC32_EL2, "fpexc32_el2"}, - {A64SysReg_FAR_EL1, "far_el1"}, - {A64SysReg_FAR_EL2, "far_el2"}, - {A64SysReg_FAR_EL3, "far_el3"}, - {A64SysReg_HPFAR_EL2, "hpfar_el2"}, - {A64SysReg_PAR_EL1, "par_el1"}, - {A64SysReg_PMCR_EL0, "pmcr_el0"}, - {A64SysReg_PMCNTENSET_EL0, "pmcntenset_el0"}, - {A64SysReg_PMCNTENCLR_EL0, "pmcntenclr_el0"}, - {A64SysReg_PMOVSCLR_EL0, "pmovsclr_el0"}, - {A64SysReg_PMSELR_EL0, "pmselr_el0"}, - {A64SysReg_PMCCNTR_EL0, "pmccntr_el0"}, - {A64SysReg_PMXEVTYPER_EL0, "pmxevtyper_el0"}, - {A64SysReg_PMXEVCNTR_EL0, "pmxevcntr_el0"}, - {A64SysReg_PMUSERENR_EL0, "pmuserenr_el0"}, - {A64SysReg_PMINTENSET_EL1, "pmintenset_el1"}, - {A64SysReg_PMINTENCLR_EL1, "pmintenclr_el1"}, - {A64SysReg_PMOVSSET_EL0, "pmovsset_el0"}, - {A64SysReg_MAIR_EL1, "mair_el1"}, - {A64SysReg_MAIR_EL2, "mair_el2"}, - {A64SysReg_MAIR_EL3, "mair_el3"}, - {A64SysReg_AMAIR_EL1, "amair_el1"}, - {A64SysReg_AMAIR_EL2, "amair_el2"}, - {A64SysReg_AMAIR_EL3, "amair_el3"}, - {A64SysReg_VBAR_EL1, "vbar_el1"}, - {A64SysReg_VBAR_EL2, "vbar_el2"}, - {A64SysReg_VBAR_EL3, "vbar_el3"}, - {A64SysReg_RMR_EL1, "rmr_el1"}, - {A64SysReg_RMR_EL2, "rmr_el2"}, - {A64SysReg_RMR_EL3, "rmr_el3"}, - {A64SysReg_CONTEXTIDR_EL1, "contextidr_el1"}, - {A64SysReg_TPIDR_EL0, "tpidr_el0"}, - {A64SysReg_TPIDR_EL2, "tpidr_el2"}, - {A64SysReg_TPIDR_EL3, "tpidr_el3"}, - {A64SysReg_TPIDRRO_EL0, "tpidrro_el0"}, - {A64SysReg_TPIDR_EL1, "tpidr_el1"}, - {A64SysReg_CNTFRQ_EL0, "cntfrq_el0"}, - {A64SysReg_CNTVOFF_EL2, "cntvoff_el2"}, - {A64SysReg_CNTKCTL_EL1, "cntkctl_el1"}, - {A64SysReg_CNTHCTL_EL2, "cnthctl_el2"}, - {A64SysReg_CNTP_TVAL_EL0, "cntp_tval_el0"}, - {A64SysReg_CNTHP_TVAL_EL2, "cnthp_tval_el2"}, - {A64SysReg_CNTPS_TVAL_EL1, "cntps_tval_el1"}, - {A64SysReg_CNTP_CTL_EL0, "cntp_ctl_el0"}, - {A64SysReg_CNTHP_CTL_EL2, "cnthp_ctl_el2"}, - {A64SysReg_CNTPS_CTL_EL1, "cntps_ctl_el1"}, - {A64SysReg_CNTP_CVAL_EL0, "cntp_cval_el0"}, - {A64SysReg_CNTHP_CVAL_EL2, "cnthp_cval_el2"}, - {A64SysReg_CNTPS_CVAL_EL1, "cntps_cval_el1"}, - {A64SysReg_CNTV_TVAL_EL0, "cntv_tval_el0"}, - {A64SysReg_CNTV_CTL_EL0, "cntv_ctl_el0"}, - {A64SysReg_CNTV_CVAL_EL0, "cntv_cval_el0"}, - {A64SysReg_PMEVCNTR0_EL0, "pmevcntr0_el0"}, - {A64SysReg_PMEVCNTR1_EL0, "pmevcntr1_el0"}, - {A64SysReg_PMEVCNTR2_EL0, "pmevcntr2_el0"}, - {A64SysReg_PMEVCNTR3_EL0, "pmevcntr3_el0"}, - {A64SysReg_PMEVCNTR4_EL0, "pmevcntr4_el0"}, - {A64SysReg_PMEVCNTR5_EL0, "pmevcntr5_el0"}, - {A64SysReg_PMEVCNTR6_EL0, "pmevcntr6_el0"}, - {A64SysReg_PMEVCNTR7_EL0, "pmevcntr7_el0"}, - {A64SysReg_PMEVCNTR8_EL0, "pmevcntr8_el0"}, - {A64SysReg_PMEVCNTR9_EL0, "pmevcntr9_el0"}, - {A64SysReg_PMEVCNTR10_EL0, "pmevcntr10_el0"}, - {A64SysReg_PMEVCNTR11_EL0, "pmevcntr11_el0"}, - {A64SysReg_PMEVCNTR12_EL0, "pmevcntr12_el0"}, - {A64SysReg_PMEVCNTR13_EL0, "pmevcntr13_el0"}, - {A64SysReg_PMEVCNTR14_EL0, "pmevcntr14_el0"}, - {A64SysReg_PMEVCNTR15_EL0, "pmevcntr15_el0"}, - {A64SysReg_PMEVCNTR16_EL0, "pmevcntr16_el0"}, - {A64SysReg_PMEVCNTR17_EL0, "pmevcntr17_el0"}, - {A64SysReg_PMEVCNTR18_EL0, "pmevcntr18_el0"}, - {A64SysReg_PMEVCNTR19_EL0, "pmevcntr19_el0"}, - {A64SysReg_PMEVCNTR20_EL0, "pmevcntr20_el0"}, - {A64SysReg_PMEVCNTR21_EL0, "pmevcntr21_el0"}, - {A64SysReg_PMEVCNTR22_EL0, "pmevcntr22_el0"}, - {A64SysReg_PMEVCNTR23_EL0, "pmevcntr23_el0"}, - {A64SysReg_PMEVCNTR24_EL0, "pmevcntr24_el0"}, - {A64SysReg_PMEVCNTR25_EL0, "pmevcntr25_el0"}, - {A64SysReg_PMEVCNTR26_EL0, "pmevcntr26_el0"}, - {A64SysReg_PMEVCNTR27_EL0, "pmevcntr27_el0"}, - {A64SysReg_PMEVCNTR28_EL0, "pmevcntr28_el0"}, - {A64SysReg_PMEVCNTR29_EL0, "pmevcntr29_el0"}, - {A64SysReg_PMEVCNTR30_EL0, "pmevcntr30_el0"}, - {A64SysReg_PMCCFILTR_EL0, "pmccfiltr_el0"}, - {A64SysReg_PMEVTYPER0_EL0, "pmevtyper0_el0"}, - {A64SysReg_PMEVTYPER1_EL0, "pmevtyper1_el0"}, - {A64SysReg_PMEVTYPER2_EL0, "pmevtyper2_el0"}, - {A64SysReg_PMEVTYPER3_EL0, "pmevtyper3_el0"}, - {A64SysReg_PMEVTYPER4_EL0, "pmevtyper4_el0"}, - {A64SysReg_PMEVTYPER5_EL0, "pmevtyper5_el0"}, - {A64SysReg_PMEVTYPER6_EL0, "pmevtyper6_el0"}, - {A64SysReg_PMEVTYPER7_EL0, "pmevtyper7_el0"}, - {A64SysReg_PMEVTYPER8_EL0, "pmevtyper8_el0"}, - {A64SysReg_PMEVTYPER9_EL0, "pmevtyper9_el0"}, - {A64SysReg_PMEVTYPER10_EL0, "pmevtyper10_el0"}, - {A64SysReg_PMEVTYPER11_EL0, "pmevtyper11_el0"}, - {A64SysReg_PMEVTYPER12_EL0, "pmevtyper12_el0"}, - {A64SysReg_PMEVTYPER13_EL0, "pmevtyper13_el0"}, - {A64SysReg_PMEVTYPER14_EL0, "pmevtyper14_el0"}, - {A64SysReg_PMEVTYPER15_EL0, "pmevtyper15_el0"}, - {A64SysReg_PMEVTYPER16_EL0, "pmevtyper16_el0"}, - {A64SysReg_PMEVTYPER17_EL0, "pmevtyper17_el0"}, - {A64SysReg_PMEVTYPER18_EL0, "pmevtyper18_el0"}, - {A64SysReg_PMEVTYPER19_EL0, "pmevtyper19_el0"}, - {A64SysReg_PMEVTYPER20_EL0, "pmevtyper20_el0"}, - {A64SysReg_PMEVTYPER21_EL0, "pmevtyper21_el0"}, - {A64SysReg_PMEVTYPER22_EL0, "pmevtyper22_el0"}, - {A64SysReg_PMEVTYPER23_EL0, "pmevtyper23_el0"}, - {A64SysReg_PMEVTYPER24_EL0, "pmevtyper24_el0"}, - {A64SysReg_PMEVTYPER25_EL0, "pmevtyper25_el0"}, - {A64SysReg_PMEVTYPER26_EL0, "pmevtyper26_el0"}, - {A64SysReg_PMEVTYPER27_EL0, "pmevtyper27_el0"}, - {A64SysReg_PMEVTYPER28_EL0, "pmevtyper28_el0"}, - {A64SysReg_PMEVTYPER29_EL0, "pmevtyper29_el0"}, - {A64SysReg_PMEVTYPER30_EL0, "pmevtyper30_el0"}, + {ARM64_SYSREG_OSDTRRX_EL1, "osdtrrx_el1"}, + {ARM64_SYSREG_OSDTRTX_EL1, "osdtrtx_el1"}, + {ARM64_SYSREG_TEECR32_EL1, "teecr32_el1"}, + {ARM64_SYSREG_MDCCINT_EL1, "mdccint_el1"}, + {ARM64_SYSREG_MDSCR_EL1, "mdscr_el1"}, + {ARM64_SYSREG_DBGDTR_EL0, "dbgdtr_el0"}, + {ARM64_SYSREG_OSECCR_EL1, "oseccr_el1"}, + {ARM64_SYSREG_DBGVCR32_EL2, "dbgvcr32_el2"}, + {ARM64_SYSREG_DBGBVR0_EL1, "dbgbvr0_el1"}, + {ARM64_SYSREG_DBGBVR1_EL1, "dbgbvr1_el1"}, + {ARM64_SYSREG_DBGBVR2_EL1, "dbgbvr2_el1"}, + {ARM64_SYSREG_DBGBVR3_EL1, "dbgbvr3_el1"}, + {ARM64_SYSREG_DBGBVR4_EL1, "dbgbvr4_el1"}, + {ARM64_SYSREG_DBGBVR5_EL1, "dbgbvr5_el1"}, + {ARM64_SYSREG_DBGBVR6_EL1, "dbgbvr6_el1"}, + {ARM64_SYSREG_DBGBVR7_EL1, "dbgbvr7_el1"}, + {ARM64_SYSREG_DBGBVR8_EL1, "dbgbvr8_el1"}, + {ARM64_SYSREG_DBGBVR9_EL1, "dbgbvr9_el1"}, + {ARM64_SYSREG_DBGBVR10_EL1, "dbgbvr10_el1"}, + {ARM64_SYSREG_DBGBVR11_EL1, "dbgbvr11_el1"}, + {ARM64_SYSREG_DBGBVR12_EL1, "dbgbvr12_el1"}, + {ARM64_SYSREG_DBGBVR13_EL1, "dbgbvr13_el1"}, + {ARM64_SYSREG_DBGBVR14_EL1, "dbgbvr14_el1"}, + {ARM64_SYSREG_DBGBVR15_EL1, "dbgbvr15_el1"}, + {ARM64_SYSREG_DBGBCR0_EL1, "dbgbcr0_el1"}, + {ARM64_SYSREG_DBGBCR1_EL1, "dbgbcr1_el1"}, + {ARM64_SYSREG_DBGBCR2_EL1, "dbgbcr2_el1"}, + {ARM64_SYSREG_DBGBCR3_EL1, "dbgbcr3_el1"}, + {ARM64_SYSREG_DBGBCR4_EL1, "dbgbcr4_el1"}, + {ARM64_SYSREG_DBGBCR5_EL1, "dbgbcr5_el1"}, + {ARM64_SYSREG_DBGBCR6_EL1, "dbgbcr6_el1"}, + {ARM64_SYSREG_DBGBCR7_EL1, "dbgbcr7_el1"}, + {ARM64_SYSREG_DBGBCR8_EL1, "dbgbcr8_el1"}, + {ARM64_SYSREG_DBGBCR9_EL1, "dbgbcr9_el1"}, + {ARM64_SYSREG_DBGBCR10_EL1, "dbgbcr10_el1"}, + {ARM64_SYSREG_DBGBCR11_EL1, "dbgbcr11_el1"}, + {ARM64_SYSREG_DBGBCR12_EL1, "dbgbcr12_el1"}, + {ARM64_SYSREG_DBGBCR13_EL1, "dbgbcr13_el1"}, + {ARM64_SYSREG_DBGBCR14_EL1, "dbgbcr14_el1"}, + {ARM64_SYSREG_DBGBCR15_EL1, "dbgbcr15_el1"}, + {ARM64_SYSREG_DBGWVR0_EL1, "dbgwvr0_el1"}, + {ARM64_SYSREG_DBGWVR1_EL1, "dbgwvr1_el1"}, + {ARM64_SYSREG_DBGWVR2_EL1, "dbgwvr2_el1"}, + {ARM64_SYSREG_DBGWVR3_EL1, "dbgwvr3_el1"}, + {ARM64_SYSREG_DBGWVR4_EL1, "dbgwvr4_el1"}, + {ARM64_SYSREG_DBGWVR5_EL1, "dbgwvr5_el1"}, + {ARM64_SYSREG_DBGWVR6_EL1, "dbgwvr6_el1"}, + {ARM64_SYSREG_DBGWVR7_EL1, "dbgwvr7_el1"}, + {ARM64_SYSREG_DBGWVR8_EL1, "dbgwvr8_el1"}, + {ARM64_SYSREG_DBGWVR9_EL1, "dbgwvr9_el1"}, + {ARM64_SYSREG_DBGWVR10_EL1, "dbgwvr10_el1"}, + {ARM64_SYSREG_DBGWVR11_EL1, "dbgwvr11_el1"}, + {ARM64_SYSREG_DBGWVR12_EL1, "dbgwvr12_el1"}, + {ARM64_SYSREG_DBGWVR13_EL1, "dbgwvr13_el1"}, + {ARM64_SYSREG_DBGWVR14_EL1, "dbgwvr14_el1"}, + {ARM64_SYSREG_DBGWVR15_EL1, "dbgwvr15_el1"}, + {ARM64_SYSREG_DBGWCR0_EL1, "dbgwcr0_el1"}, + {ARM64_SYSREG_DBGWCR1_EL1, "dbgwcr1_el1"}, + {ARM64_SYSREG_DBGWCR2_EL1, "dbgwcr2_el1"}, + {ARM64_SYSREG_DBGWCR3_EL1, "dbgwcr3_el1"}, + {ARM64_SYSREG_DBGWCR4_EL1, "dbgwcr4_el1"}, + {ARM64_SYSREG_DBGWCR5_EL1, "dbgwcr5_el1"}, + {ARM64_SYSREG_DBGWCR6_EL1, "dbgwcr6_el1"}, + {ARM64_SYSREG_DBGWCR7_EL1, "dbgwcr7_el1"}, + {ARM64_SYSREG_DBGWCR8_EL1, "dbgwcr8_el1"}, + {ARM64_SYSREG_DBGWCR9_EL1, "dbgwcr9_el1"}, + {ARM64_SYSREG_DBGWCR10_EL1, "dbgwcr10_el1"}, + {ARM64_SYSREG_DBGWCR11_EL1, "dbgwcr11_el1"}, + {ARM64_SYSREG_DBGWCR12_EL1, "dbgwcr12_el1"}, + {ARM64_SYSREG_DBGWCR13_EL1, "dbgwcr13_el1"}, + {ARM64_SYSREG_DBGWCR14_EL1, "dbgwcr14_el1"}, + {ARM64_SYSREG_DBGWCR15_EL1, "dbgwcr15_el1"}, + {ARM64_SYSREG_TEEHBR32_EL1, "teehbr32_el1"}, + {ARM64_SYSREG_OSDLR_EL1, "osdlr_el1"}, + {ARM64_SYSREG_DBGPRCR_EL1, "dbgprcr_el1"}, + {ARM64_SYSREG_DBGCLAIMSET_EL1, "dbgclaimset_el1"}, + {ARM64_SYSREG_DBGCLAIMCLR_EL1, "dbgclaimclr_el1"}, + {ARM64_SYSREG_CSSELR_EL1, "csselr_el1"}, + {ARM64_SYSREG_VPIDR_EL2, "vpidr_el2"}, + {ARM64_SYSREG_VMPIDR_EL2, "vmpidr_el2"}, + {ARM64_SYSREG_SCTLR_EL1, "sctlr_el1"}, + {ARM64_SYSREG_SCTLR_EL2, "sctlr_el2"}, + {ARM64_SYSREG_SCTLR_EL3, "sctlr_el3"}, + {ARM64_SYSREG_ACTLR_EL1, "actlr_el1"}, + {ARM64_SYSREG_ACTLR_EL2, "actlr_el2"}, + {ARM64_SYSREG_ACTLR_EL3, "actlr_el3"}, + {ARM64_SYSREG_CPACR_EL1, "cpacr_el1"}, + {ARM64_SYSREG_HCR_EL2, "hcr_el2"}, + {ARM64_SYSREG_SCR_EL3, "scr_el3"}, + {ARM64_SYSREG_MDCR_EL2, "mdcr_el2"}, + {ARM64_SYSREG_SDER32_EL3, "sder32_el3"}, + {ARM64_SYSREG_CPTR_EL2, "cptr_el2"}, + {ARM64_SYSREG_CPTR_EL3, "cptr_el3"}, + {ARM64_SYSREG_HSTR_EL2, "hstr_el2"}, + {ARM64_SYSREG_HACR_EL2, "hacr_el2"}, + {ARM64_SYSREG_MDCR_EL3, "mdcr_el3"}, + {ARM64_SYSREG_TTBR0_EL1, "ttbr0_el1"}, + {ARM64_SYSREG_TTBR0_EL2, "ttbr0_el2"}, + {ARM64_SYSREG_TTBR0_EL3, "ttbr0_el3"}, + {ARM64_SYSREG_TTBR1_EL1, "ttbr1_el1"}, + {ARM64_SYSREG_TCR_EL1, "tcr_el1"}, + {ARM64_SYSREG_TCR_EL2, "tcr_el2"}, + {ARM64_SYSREG_TCR_EL3, "tcr_el3"}, + {ARM64_SYSREG_VTTBR_EL2, "vttbr_el2"}, + {ARM64_SYSREG_VTCR_EL2, "vtcr_el2"}, + {ARM64_SYSREG_DACR32_EL2, "dacr32_el2"}, + {ARM64_SYSREG_SPSR_EL1, "spsr_el1"}, + {ARM64_SYSREG_SPSR_EL2, "spsr_el2"}, + {ARM64_SYSREG_SPSR_EL3, "spsr_el3"}, + {ARM64_SYSREG_ELR_EL1, "elr_el1"}, + {ARM64_SYSREG_ELR_EL2, "elr_el2"}, + {ARM64_SYSREG_ELR_EL3, "elr_el3"}, + {ARM64_SYSREG_SP_EL0, "sp_el0"}, + {ARM64_SYSREG_SP_EL1, "sp_el1"}, + {ARM64_SYSREG_SP_EL2, "sp_el2"}, + {ARM64_SYSREG_SPSEL, "spsel"}, + {ARM64_SYSREG_NZCV, "nzcv"}, + {ARM64_SYSREG_DAIF, "daif"}, + {ARM64_SYSREG_CURRENTEL, "currentel"}, + {ARM64_SYSREG_SPSR_IRQ, "spsr_irq"}, + {ARM64_SYSREG_SPSR_ABT, "spsr_abt"}, + {ARM64_SYSREG_SPSR_UND, "spsr_und"}, + {ARM64_SYSREG_SPSR_FIQ, "spsr_fiq"}, + {ARM64_SYSREG_FPCR, "fpcr"}, + {ARM64_SYSREG_FPSR, "fpsr"}, + {ARM64_SYSREG_DSPSR_EL0, "dspsr_el0"}, + {ARM64_SYSREG_DLR_EL0, "dlr_el0"}, + {ARM64_SYSREG_IFSR32_EL2, "ifsr32_el2"}, + {ARM64_SYSREG_AFSR0_EL1, "afsr0_el1"}, + {ARM64_SYSREG_AFSR0_EL2, "afsr0_el2"}, + {ARM64_SYSREG_AFSR0_EL3, "afsr0_el3"}, + {ARM64_SYSREG_AFSR1_EL1, "afsr1_el1"}, + {ARM64_SYSREG_AFSR1_EL2, "afsr1_el2"}, + {ARM64_SYSREG_AFSR1_EL3, "afsr1_el3"}, + {ARM64_SYSREG_ESR_EL1, "esr_el1"}, + {ARM64_SYSREG_ESR_EL2, "esr_el2"}, + {ARM64_SYSREG_ESR_EL3, "esr_el3"}, + {ARM64_SYSREG_FPEXC32_EL2, "fpexc32_el2"}, + {ARM64_SYSREG_FAR_EL1, "far_el1"}, + {ARM64_SYSREG_FAR_EL2, "far_el2"}, + {ARM64_SYSREG_FAR_EL3, "far_el3"}, + {ARM64_SYSREG_HPFAR_EL2, "hpfar_el2"}, + {ARM64_SYSREG_PAR_EL1, "par_el1"}, + {ARM64_SYSREG_PMCR_EL0, "pmcr_el0"}, + {ARM64_SYSREG_PMCNTENSET_EL0, "pmcntenset_el0"}, + {ARM64_SYSREG_PMCNTENCLR_EL0, "pmcntenclr_el0"}, + {ARM64_SYSREG_PMOVSCLR_EL0, "pmovsclr_el0"}, + {ARM64_SYSREG_PMSELR_EL0, "pmselr_el0"}, + {ARM64_SYSREG_PMCCNTR_EL0, "pmccntr_el0"}, + {ARM64_SYSREG_PMXEVTYPER_EL0, "pmxevtyper_el0"}, + {ARM64_SYSREG_PMXEVCNTR_EL0, "pmxevcntr_el0"}, + {ARM64_SYSREG_PMUSERENR_EL0, "pmuserenr_el0"}, + {ARM64_SYSREG_PMINTENSET_EL1, "pmintenset_el1"}, + {ARM64_SYSREG_PMINTENCLR_EL1, "pmintenclr_el1"}, + {ARM64_SYSREG_PMOVSSET_EL0, "pmovsset_el0"}, + {ARM64_SYSREG_MAIR_EL1, "mair_el1"}, + {ARM64_SYSREG_MAIR_EL2, "mair_el2"}, + {ARM64_SYSREG_MAIR_EL3, "mair_el3"}, + {ARM64_SYSREG_AMAIR_EL1, "amair_el1"}, + {ARM64_SYSREG_AMAIR_EL2, "amair_el2"}, + {ARM64_SYSREG_AMAIR_EL3, "amair_el3"}, + {ARM64_SYSREG_VBAR_EL1, "vbar_el1"}, + {ARM64_SYSREG_VBAR_EL2, "vbar_el2"}, + {ARM64_SYSREG_VBAR_EL3, "vbar_el3"}, + {ARM64_SYSREG_RMR_EL1, "rmr_el1"}, + {ARM64_SYSREG_RMR_EL2, "rmr_el2"}, + {ARM64_SYSREG_RMR_EL3, "rmr_el3"}, + {ARM64_SYSREG_CONTEXTIDR_EL1, "contextidr_el1"}, + {ARM64_SYSREG_TPIDR_EL0, "tpidr_el0"}, + {ARM64_SYSREG_TPIDR_EL2, "tpidr_el2"}, + {ARM64_SYSREG_TPIDR_EL3, "tpidr_el3"}, + {ARM64_SYSREG_TPIDRRO_EL0, "tpidrro_el0"}, + {ARM64_SYSREG_TPIDR_EL1, "tpidr_el1"}, + {ARM64_SYSREG_CNTFRQ_EL0, "cntfrq_el0"}, + {ARM64_SYSREG_CNTVOFF_EL2, "cntvoff_el2"}, + {ARM64_SYSREG_CNTKCTL_EL1, "cntkctl_el1"}, + {ARM64_SYSREG_CNTHCTL_EL2, "cnthctl_el2"}, + {ARM64_SYSREG_CNTP_TVAL_EL0, "cntp_tval_el0"}, + {ARM64_SYSREG_CNTHP_TVAL_EL2, "cnthp_tval_el2"}, + {ARM64_SYSREG_CNTPS_TVAL_EL1, "cntps_tval_el1"}, + {ARM64_SYSREG_CNTP_CTL_EL0, "cntp_ctl_el0"}, + {ARM64_SYSREG_CNTHP_CTL_EL2, "cnthp_ctl_el2"}, + {ARM64_SYSREG_CNTPS_CTL_EL1, "cntps_ctl_el1"}, + {ARM64_SYSREG_CNTP_CVAL_EL0, "cntp_cval_el0"}, + {ARM64_SYSREG_CNTHP_CVAL_EL2, "cnthp_cval_el2"}, + {ARM64_SYSREG_CNTPS_CVAL_EL1, "cntps_cval_el1"}, + {ARM64_SYSREG_CNTV_TVAL_EL0, "cntv_tval_el0"}, + {ARM64_SYSREG_CNTV_CTL_EL0, "cntv_ctl_el0"}, + {ARM64_SYSREG_CNTV_CVAL_EL0, "cntv_cval_el0"}, + {ARM64_SYSREG_PMEVCNTR0_EL0, "pmevcntr0_el0"}, + {ARM64_SYSREG_PMEVCNTR1_EL0, "pmevcntr1_el0"}, + {ARM64_SYSREG_PMEVCNTR2_EL0, "pmevcntr2_el0"}, + {ARM64_SYSREG_PMEVCNTR3_EL0, "pmevcntr3_el0"}, + {ARM64_SYSREG_PMEVCNTR4_EL0, "pmevcntr4_el0"}, + {ARM64_SYSREG_PMEVCNTR5_EL0, "pmevcntr5_el0"}, + {ARM64_SYSREG_PMEVCNTR6_EL0, "pmevcntr6_el0"}, + {ARM64_SYSREG_PMEVCNTR7_EL0, "pmevcntr7_el0"}, + {ARM64_SYSREG_PMEVCNTR8_EL0, "pmevcntr8_el0"}, + {ARM64_SYSREG_PMEVCNTR9_EL0, "pmevcntr9_el0"}, + {ARM64_SYSREG_PMEVCNTR10_EL0, "pmevcntr10_el0"}, + {ARM64_SYSREG_PMEVCNTR11_EL0, "pmevcntr11_el0"}, + {ARM64_SYSREG_PMEVCNTR12_EL0, "pmevcntr12_el0"}, + {ARM64_SYSREG_PMEVCNTR13_EL0, "pmevcntr13_el0"}, + {ARM64_SYSREG_PMEVCNTR14_EL0, "pmevcntr14_el0"}, + {ARM64_SYSREG_PMEVCNTR15_EL0, "pmevcntr15_el0"}, + {ARM64_SYSREG_PMEVCNTR16_EL0, "pmevcntr16_el0"}, + {ARM64_SYSREG_PMEVCNTR17_EL0, "pmevcntr17_el0"}, + {ARM64_SYSREG_PMEVCNTR18_EL0, "pmevcntr18_el0"}, + {ARM64_SYSREG_PMEVCNTR19_EL0, "pmevcntr19_el0"}, + {ARM64_SYSREG_PMEVCNTR20_EL0, "pmevcntr20_el0"}, + {ARM64_SYSREG_PMEVCNTR21_EL0, "pmevcntr21_el0"}, + {ARM64_SYSREG_PMEVCNTR22_EL0, "pmevcntr22_el0"}, + {ARM64_SYSREG_PMEVCNTR23_EL0, "pmevcntr23_el0"}, + {ARM64_SYSREG_PMEVCNTR24_EL0, "pmevcntr24_el0"}, + {ARM64_SYSREG_PMEVCNTR25_EL0, "pmevcntr25_el0"}, + {ARM64_SYSREG_PMEVCNTR26_EL0, "pmevcntr26_el0"}, + {ARM64_SYSREG_PMEVCNTR27_EL0, "pmevcntr27_el0"}, + {ARM64_SYSREG_PMEVCNTR28_EL0, "pmevcntr28_el0"}, + {ARM64_SYSREG_PMEVCNTR29_EL0, "pmevcntr29_el0"}, + {ARM64_SYSREG_PMEVCNTR30_EL0, "pmevcntr30_el0"}, + {ARM64_SYSREG_PMCCFILTR_EL0, "pmccfiltr_el0"}, + {ARM64_SYSREG_PMEVTYPER0_EL0, "pmevtyper0_el0"}, + {ARM64_SYSREG_PMEVTYPER1_EL0, "pmevtyper1_el0"}, + {ARM64_SYSREG_PMEVTYPER2_EL0, "pmevtyper2_el0"}, + {ARM64_SYSREG_PMEVTYPER3_EL0, "pmevtyper3_el0"}, + {ARM64_SYSREG_PMEVTYPER4_EL0, "pmevtyper4_el0"}, + {ARM64_SYSREG_PMEVTYPER5_EL0, "pmevtyper5_el0"}, + {ARM64_SYSREG_PMEVTYPER6_EL0, "pmevtyper6_el0"}, + {ARM64_SYSREG_PMEVTYPER7_EL0, "pmevtyper7_el0"}, + {ARM64_SYSREG_PMEVTYPER8_EL0, "pmevtyper8_el0"}, + {ARM64_SYSREG_PMEVTYPER9_EL0, "pmevtyper9_el0"}, + {ARM64_SYSREG_PMEVTYPER10_EL0, "pmevtyper10_el0"}, + {ARM64_SYSREG_PMEVTYPER11_EL0, "pmevtyper11_el0"}, + {ARM64_SYSREG_PMEVTYPER12_EL0, "pmevtyper12_el0"}, + {ARM64_SYSREG_PMEVTYPER13_EL0, "pmevtyper13_el0"}, + {ARM64_SYSREG_PMEVTYPER14_EL0, "pmevtyper14_el0"}, + {ARM64_SYSREG_PMEVTYPER15_EL0, "pmevtyper15_el0"}, + {ARM64_SYSREG_PMEVTYPER16_EL0, "pmevtyper16_el0"}, + {ARM64_SYSREG_PMEVTYPER17_EL0, "pmevtyper17_el0"}, + {ARM64_SYSREG_PMEVTYPER18_EL0, "pmevtyper18_el0"}, + {ARM64_SYSREG_PMEVTYPER19_EL0, "pmevtyper19_el0"}, + {ARM64_SYSREG_PMEVTYPER20_EL0, "pmevtyper20_el0"}, + {ARM64_SYSREG_PMEVTYPER21_EL0, "pmevtyper21_el0"}, + {ARM64_SYSREG_PMEVTYPER22_EL0, "pmevtyper22_el0"}, + {ARM64_SYSREG_PMEVTYPER23_EL0, "pmevtyper23_el0"}, + {ARM64_SYSREG_PMEVTYPER24_EL0, "pmevtyper24_el0"}, + {ARM64_SYSREG_PMEVTYPER25_EL0, "pmevtyper25_el0"}, + {ARM64_SYSREG_PMEVTYPER26_EL0, "pmevtyper26_el0"}, + {ARM64_SYSREG_PMEVTYPER27_EL0, "pmevtyper27_el0"}, + {ARM64_SYSREG_PMEVTYPER28_EL0, "pmevtyper28_el0"}, + {ARM64_SYSREG_PMEVTYPER29_EL0, "pmevtyper29_el0"}, + {ARM64_SYSREG_PMEVTYPER30_EL0, "pmevtyper30_el0"}, // Trace registers - {A64SysReg_TRCPRGCTLR, "trcprgctlr"}, - {A64SysReg_TRCPROCSELR, "trcprocselr"}, - {A64SysReg_TRCCONFIGR, "trcconfigr"}, - {A64SysReg_TRCAUXCTLR, "trcauxctlr"}, - {A64SysReg_TRCEVENTCTL0R, "trceventctl0r"}, - {A64SysReg_TRCEVENTCTL1R, "trceventctl1r"}, - {A64SysReg_TRCSTALLCTLR, "trcstallctlr"}, - {A64SysReg_TRCTSCTLR, "trctsctlr"}, - {A64SysReg_TRCSYNCPR, "trcsyncpr"}, - {A64SysReg_TRCCCCTLR, "trcccctlr"}, - {A64SysReg_TRCBBCTLR, "trcbbctlr"}, - {A64SysReg_TRCTRACEIDR, "trctraceidr"}, - {A64SysReg_TRCQCTLR, "trcqctlr"}, - {A64SysReg_TRCVICTLR, "trcvictlr"}, - {A64SysReg_TRCVIIECTLR, "trcviiectlr"}, - {A64SysReg_TRCVISSCTLR, "trcvissctlr"}, - {A64SysReg_TRCVIPCSSCTLR, "trcvipcssctlr"}, - {A64SysReg_TRCVDCTLR, "trcvdctlr"}, - {A64SysReg_TRCVDSACCTLR, "trcvdsacctlr"}, - {A64SysReg_TRCVDARCCTLR, "trcvdarcctlr"}, - {A64SysReg_TRCSEQEVR0, "trcseqevr0"}, - {A64SysReg_TRCSEQEVR1, "trcseqevr1"}, - {A64SysReg_TRCSEQEVR2, "trcseqevr2"}, - {A64SysReg_TRCSEQRSTEVR, "trcseqrstevr"}, - {A64SysReg_TRCSEQSTR, "trcseqstr"}, - {A64SysReg_TRCEXTINSELR, "trcextinselr"}, - {A64SysReg_TRCCNTRLDVR0, "trccntrldvr0"}, - {A64SysReg_TRCCNTRLDVR1, "trccntrldvr1"}, - {A64SysReg_TRCCNTRLDVR2, "trccntrldvr2"}, - {A64SysReg_TRCCNTRLDVR3, "trccntrldvr3"}, - {A64SysReg_TRCCNTCTLR0, "trccntctlr0"}, - {A64SysReg_TRCCNTCTLR1, "trccntctlr1"}, - {A64SysReg_TRCCNTCTLR2, "trccntctlr2"}, - {A64SysReg_TRCCNTCTLR3, "trccntctlr3"}, - {A64SysReg_TRCCNTVR0, "trccntvr0"}, - {A64SysReg_TRCCNTVR1, "trccntvr1"}, - {A64SysReg_TRCCNTVR2, "trccntvr2"}, - {A64SysReg_TRCCNTVR3, "trccntvr3"}, - {A64SysReg_TRCIMSPEC0, "trcimspec0"}, - {A64SysReg_TRCIMSPEC1, "trcimspec1"}, - {A64SysReg_TRCIMSPEC2, "trcimspec2"}, - {A64SysReg_TRCIMSPEC3, "trcimspec3"}, - {A64SysReg_TRCIMSPEC4, "trcimspec4"}, - {A64SysReg_TRCIMSPEC5, "trcimspec5"}, - {A64SysReg_TRCIMSPEC6, "trcimspec6"}, - {A64SysReg_TRCIMSPEC7, "trcimspec7"}, - {A64SysReg_TRCRSCTLR2, "trcrsctlr2"}, - {A64SysReg_TRCRSCTLR3, "trcrsctlr3"}, - {A64SysReg_TRCRSCTLR4, "trcrsctlr4"}, - {A64SysReg_TRCRSCTLR5, "trcrsctlr5"}, - {A64SysReg_TRCRSCTLR6, "trcrsctlr6"}, - {A64SysReg_TRCRSCTLR7, "trcrsctlr7"}, - {A64SysReg_TRCRSCTLR8, "trcrsctlr8"}, - {A64SysReg_TRCRSCTLR9, "trcrsctlr9"}, - {A64SysReg_TRCRSCTLR10, "trcrsctlr10"}, - {A64SysReg_TRCRSCTLR11, "trcrsctlr11"}, - {A64SysReg_TRCRSCTLR12, "trcrsctlr12"}, - {A64SysReg_TRCRSCTLR13, "trcrsctlr13"}, - {A64SysReg_TRCRSCTLR14, "trcrsctlr14"}, - {A64SysReg_TRCRSCTLR15, "trcrsctlr15"}, - {A64SysReg_TRCRSCTLR16, "trcrsctlr16"}, - {A64SysReg_TRCRSCTLR17, "trcrsctlr17"}, - {A64SysReg_TRCRSCTLR18, "trcrsctlr18"}, - {A64SysReg_TRCRSCTLR19, "trcrsctlr19"}, - {A64SysReg_TRCRSCTLR20, "trcrsctlr20"}, - {A64SysReg_TRCRSCTLR21, "trcrsctlr21"}, - {A64SysReg_TRCRSCTLR22, "trcrsctlr22"}, - {A64SysReg_TRCRSCTLR23, "trcrsctlr23"}, - {A64SysReg_TRCRSCTLR24, "trcrsctlr24"}, - {A64SysReg_TRCRSCTLR25, "trcrsctlr25"}, - {A64SysReg_TRCRSCTLR26, "trcrsctlr26"}, - {A64SysReg_TRCRSCTLR27, "trcrsctlr27"}, - {A64SysReg_TRCRSCTLR28, "trcrsctlr28"}, - {A64SysReg_TRCRSCTLR29, "trcrsctlr29"}, - {A64SysReg_TRCRSCTLR30, "trcrsctlr30"}, - {A64SysReg_TRCRSCTLR31, "trcrsctlr31"}, - {A64SysReg_TRCSSCCR0, "trcssccr0"}, - {A64SysReg_TRCSSCCR1, "trcssccr1"}, - {A64SysReg_TRCSSCCR2, "trcssccr2"}, - {A64SysReg_TRCSSCCR3, "trcssccr3"}, - {A64SysReg_TRCSSCCR4, "trcssccr4"}, - {A64SysReg_TRCSSCCR5, "trcssccr5"}, - {A64SysReg_TRCSSCCR6, "trcssccr6"}, - {A64SysReg_TRCSSCCR7, "trcssccr7"}, - {A64SysReg_TRCSSCSR0, "trcsscsr0"}, - {A64SysReg_TRCSSCSR1, "trcsscsr1"}, - {A64SysReg_TRCSSCSR2, "trcsscsr2"}, - {A64SysReg_TRCSSCSR3, "trcsscsr3"}, - {A64SysReg_TRCSSCSR4, "trcsscsr4"}, - {A64SysReg_TRCSSCSR5, "trcsscsr5"}, - {A64SysReg_TRCSSCSR6, "trcsscsr6"}, - {A64SysReg_TRCSSCSR7, "trcsscsr7"}, - {A64SysReg_TRCSSPCICR0, "trcsspcicr0"}, - {A64SysReg_TRCSSPCICR1, "trcsspcicr1"}, - {A64SysReg_TRCSSPCICR2, "trcsspcicr2"}, - {A64SysReg_TRCSSPCICR3, "trcsspcicr3"}, - {A64SysReg_TRCSSPCICR4, "trcsspcicr4"}, - {A64SysReg_TRCSSPCICR5, "trcsspcicr5"}, - {A64SysReg_TRCSSPCICR6, "trcsspcicr6"}, - {A64SysReg_TRCSSPCICR7, "trcsspcicr7"}, - {A64SysReg_TRCPDCR, "trcpdcr"}, - {A64SysReg_TRCACVR0, "trcacvr0"}, - {A64SysReg_TRCACVR1, "trcacvr1"}, - {A64SysReg_TRCACVR2, "trcacvr2"}, - {A64SysReg_TRCACVR3, "trcacvr3"}, - {A64SysReg_TRCACVR4, "trcacvr4"}, - {A64SysReg_TRCACVR5, "trcacvr5"}, - {A64SysReg_TRCACVR6, "trcacvr6"}, - {A64SysReg_TRCACVR7, "trcacvr7"}, - {A64SysReg_TRCACVR8, "trcacvr8"}, - {A64SysReg_TRCACVR9, "trcacvr9"}, - {A64SysReg_TRCACVR10, "trcacvr10"}, - {A64SysReg_TRCACVR11, "trcacvr11"}, - {A64SysReg_TRCACVR12, "trcacvr12"}, - {A64SysReg_TRCACVR13, "trcacvr13"}, - {A64SysReg_TRCACVR14, "trcacvr14"}, - {A64SysReg_TRCACVR15, "trcacvr15"}, - {A64SysReg_TRCACATR0, "trcacatr0"}, - {A64SysReg_TRCACATR1, "trcacatr1"}, - {A64SysReg_TRCACATR2, "trcacatr2"}, - {A64SysReg_TRCACATR3, "trcacatr3"}, - {A64SysReg_TRCACATR4, "trcacatr4"}, - {A64SysReg_TRCACATR5, "trcacatr5"}, - {A64SysReg_TRCACATR6, "trcacatr6"}, - {A64SysReg_TRCACATR7, "trcacatr7"}, - {A64SysReg_TRCACATR8, "trcacatr8"}, - {A64SysReg_TRCACATR9, "trcacatr9"}, - {A64SysReg_TRCACATR10, "trcacatr10"}, - {A64SysReg_TRCACATR11, "trcacatr11"}, - {A64SysReg_TRCACATR12, "trcacatr12"}, - {A64SysReg_TRCACATR13, "trcacatr13"}, - {A64SysReg_TRCACATR14, "trcacatr14"}, - {A64SysReg_TRCACATR15, "trcacatr15"}, - {A64SysReg_TRCDVCVR0, "trcdvcvr0"}, - {A64SysReg_TRCDVCVR1, "trcdvcvr1"}, - {A64SysReg_TRCDVCVR2, "trcdvcvr2"}, - {A64SysReg_TRCDVCVR3, "trcdvcvr3"}, - {A64SysReg_TRCDVCVR4, "trcdvcvr4"}, - {A64SysReg_TRCDVCVR5, "trcdvcvr5"}, - {A64SysReg_TRCDVCVR6, "trcdvcvr6"}, - {A64SysReg_TRCDVCVR7, "trcdvcvr7"}, - {A64SysReg_TRCDVCMR0, "trcdvcmr0"}, - {A64SysReg_TRCDVCMR1, "trcdvcmr1"}, - {A64SysReg_TRCDVCMR2, "trcdvcmr2"}, - {A64SysReg_TRCDVCMR3, "trcdvcmr3"}, - {A64SysReg_TRCDVCMR4, "trcdvcmr4"}, - {A64SysReg_TRCDVCMR5, "trcdvcmr5"}, - {A64SysReg_TRCDVCMR6, "trcdvcmr6"}, - {A64SysReg_TRCDVCMR7, "trcdvcmr7"}, - {A64SysReg_TRCCIDCVR0, "trccidcvr0"}, - {A64SysReg_TRCCIDCVR1, "trccidcvr1"}, - {A64SysReg_TRCCIDCVR2, "trccidcvr2"}, - {A64SysReg_TRCCIDCVR3, "trccidcvr3"}, - {A64SysReg_TRCCIDCVR4, "trccidcvr4"}, - {A64SysReg_TRCCIDCVR5, "trccidcvr5"}, - {A64SysReg_TRCCIDCVR6, "trccidcvr6"}, - {A64SysReg_TRCCIDCVR7, "trccidcvr7"}, - {A64SysReg_TRCVMIDCVR0, "trcvmidcvr0"}, - {A64SysReg_TRCVMIDCVR1, "trcvmidcvr1"}, - {A64SysReg_TRCVMIDCVR2, "trcvmidcvr2"}, - {A64SysReg_TRCVMIDCVR3, "trcvmidcvr3"}, - {A64SysReg_TRCVMIDCVR4, "trcvmidcvr4"}, - {A64SysReg_TRCVMIDCVR5, "trcvmidcvr5"}, - {A64SysReg_TRCVMIDCVR6, "trcvmidcvr6"}, - {A64SysReg_TRCVMIDCVR7, "trcvmidcvr7"}, - {A64SysReg_TRCCIDCCTLR0, "trccidcctlr0"}, - {A64SysReg_TRCCIDCCTLR1, "trccidcctlr1"}, - {A64SysReg_TRCVMIDCCTLR0, "trcvmidcctlr0"}, - {A64SysReg_TRCVMIDCCTLR1, "trcvmidcctlr1"}, - {A64SysReg_TRCITCTRL, "trcitctrl"}, - {A64SysReg_TRCCLAIMSET, "trcclaimset"}, - {A64SysReg_TRCCLAIMCLR, "trcclaimclr"}, + {ARM64_SYSREG_TRCPRGCTLR, "trcprgctlr"}, + {ARM64_SYSREG_TRCPROCSELR, "trcprocselr"}, + {ARM64_SYSREG_TRCCONFIGR, "trcconfigr"}, + {ARM64_SYSREG_TRCAUXCTLR, "trcauxctlr"}, + {ARM64_SYSREG_TRCEVENTCTL0R, "trceventctl0r"}, + {ARM64_SYSREG_TRCEVENTCTL1R, "trceventctl1r"}, + {ARM64_SYSREG_TRCSTALLCTLR, "trcstallctlr"}, + {ARM64_SYSREG_TRCTSCTLR, "trctsctlr"}, + {ARM64_SYSREG_TRCSYNCPR, "trcsyncpr"}, + {ARM64_SYSREG_TRCCCCTLR, "trcccctlr"}, + {ARM64_SYSREG_TRCBBCTLR, "trcbbctlr"}, + {ARM64_SYSREG_TRCTRACEIDR, "trctraceidr"}, + {ARM64_SYSREG_TRCQCTLR, "trcqctlr"}, + {ARM64_SYSREG_TRCVICTLR, "trcvictlr"}, + {ARM64_SYSREG_TRCVIIECTLR, "trcviiectlr"}, + {ARM64_SYSREG_TRCVISSCTLR, "trcvissctlr"}, + {ARM64_SYSREG_TRCVIPCSSCTLR, "trcvipcssctlr"}, + {ARM64_SYSREG_TRCVDCTLR, "trcvdctlr"}, + {ARM64_SYSREG_TRCVDSACCTLR, "trcvdsacctlr"}, + {ARM64_SYSREG_TRCVDARCCTLR, "trcvdarcctlr"}, + {ARM64_SYSREG_TRCSEQEVR0, "trcseqevr0"}, + {ARM64_SYSREG_TRCSEQEVR1, "trcseqevr1"}, + {ARM64_SYSREG_TRCSEQEVR2, "trcseqevr2"}, + {ARM64_SYSREG_TRCSEQRSTEVR, "trcseqrstevr"}, + {ARM64_SYSREG_TRCSEQSTR, "trcseqstr"}, + {ARM64_SYSREG_TRCEXTINSELR, "trcextinselr"}, + {ARM64_SYSREG_TRCCNTRLDVR0, "trccntrldvr0"}, + {ARM64_SYSREG_TRCCNTRLDVR1, "trccntrldvr1"}, + {ARM64_SYSREG_TRCCNTRLDVR2, "trccntrldvr2"}, + {ARM64_SYSREG_TRCCNTRLDVR3, "trccntrldvr3"}, + {ARM64_SYSREG_TRCCNTCTLR0, "trccntctlr0"}, + {ARM64_SYSREG_TRCCNTCTLR1, "trccntctlr1"}, + {ARM64_SYSREG_TRCCNTCTLR2, "trccntctlr2"}, + {ARM64_SYSREG_TRCCNTCTLR3, "trccntctlr3"}, + {ARM64_SYSREG_TRCCNTVR0, "trccntvr0"}, + {ARM64_SYSREG_TRCCNTVR1, "trccntvr1"}, + {ARM64_SYSREG_TRCCNTVR2, "trccntvr2"}, + {ARM64_SYSREG_TRCCNTVR3, "trccntvr3"}, + {ARM64_SYSREG_TRCIMSPEC0, "trcimspec0"}, + {ARM64_SYSREG_TRCIMSPEC1, "trcimspec1"}, + {ARM64_SYSREG_TRCIMSPEC2, "trcimspec2"}, + {ARM64_SYSREG_TRCIMSPEC3, "trcimspec3"}, + {ARM64_SYSREG_TRCIMSPEC4, "trcimspec4"}, + {ARM64_SYSREG_TRCIMSPEC5, "trcimspec5"}, + {ARM64_SYSREG_TRCIMSPEC6, "trcimspec6"}, + {ARM64_SYSREG_TRCIMSPEC7, "trcimspec7"}, + {ARM64_SYSREG_TRCRSCTLR2, "trcrsctlr2"}, + {ARM64_SYSREG_TRCRSCTLR3, "trcrsctlr3"}, + {ARM64_SYSREG_TRCRSCTLR4, "trcrsctlr4"}, + {ARM64_SYSREG_TRCRSCTLR5, "trcrsctlr5"}, + {ARM64_SYSREG_TRCRSCTLR6, "trcrsctlr6"}, + {ARM64_SYSREG_TRCRSCTLR7, "trcrsctlr7"}, + {ARM64_SYSREG_TRCRSCTLR8, "trcrsctlr8"}, + {ARM64_SYSREG_TRCRSCTLR9, "trcrsctlr9"}, + {ARM64_SYSREG_TRCRSCTLR10, "trcrsctlr10"}, + {ARM64_SYSREG_TRCRSCTLR11, "trcrsctlr11"}, + {ARM64_SYSREG_TRCRSCTLR12, "trcrsctlr12"}, + {ARM64_SYSREG_TRCRSCTLR13, "trcrsctlr13"}, + {ARM64_SYSREG_TRCRSCTLR14, "trcrsctlr14"}, + {ARM64_SYSREG_TRCRSCTLR15, "trcrsctlr15"}, + {ARM64_SYSREG_TRCRSCTLR16, "trcrsctlr16"}, + {ARM64_SYSREG_TRCRSCTLR17, "trcrsctlr17"}, + {ARM64_SYSREG_TRCRSCTLR18, "trcrsctlr18"}, + {ARM64_SYSREG_TRCRSCTLR19, "trcrsctlr19"}, + {ARM64_SYSREG_TRCRSCTLR20, "trcrsctlr20"}, + {ARM64_SYSREG_TRCRSCTLR21, "trcrsctlr21"}, + {ARM64_SYSREG_TRCRSCTLR22, "trcrsctlr22"}, + {ARM64_SYSREG_TRCRSCTLR23, "trcrsctlr23"}, + {ARM64_SYSREG_TRCRSCTLR24, "trcrsctlr24"}, + {ARM64_SYSREG_TRCRSCTLR25, "trcrsctlr25"}, + {ARM64_SYSREG_TRCRSCTLR26, "trcrsctlr26"}, + {ARM64_SYSREG_TRCRSCTLR27, "trcrsctlr27"}, + {ARM64_SYSREG_TRCRSCTLR28, "trcrsctlr28"}, + {ARM64_SYSREG_TRCRSCTLR29, "trcrsctlr29"}, + {ARM64_SYSREG_TRCRSCTLR30, "trcrsctlr30"}, + {ARM64_SYSREG_TRCRSCTLR31, "trcrsctlr31"}, + {ARM64_SYSREG_TRCSSCCR0, "trcssccr0"}, + {ARM64_SYSREG_TRCSSCCR1, "trcssccr1"}, + {ARM64_SYSREG_TRCSSCCR2, "trcssccr2"}, + {ARM64_SYSREG_TRCSSCCR3, "trcssccr3"}, + {ARM64_SYSREG_TRCSSCCR4, "trcssccr4"}, + {ARM64_SYSREG_TRCSSCCR5, "trcssccr5"}, + {ARM64_SYSREG_TRCSSCCR6, "trcssccr6"}, + {ARM64_SYSREG_TRCSSCCR7, "trcssccr7"}, + {ARM64_SYSREG_TRCSSCSR0, "trcsscsr0"}, + {ARM64_SYSREG_TRCSSCSR1, "trcsscsr1"}, + {ARM64_SYSREG_TRCSSCSR2, "trcsscsr2"}, + {ARM64_SYSREG_TRCSSCSR3, "trcsscsr3"}, + {ARM64_SYSREG_TRCSSCSR4, "trcsscsr4"}, + {ARM64_SYSREG_TRCSSCSR5, "trcsscsr5"}, + {ARM64_SYSREG_TRCSSCSR6, "trcsscsr6"}, + {ARM64_SYSREG_TRCSSCSR7, "trcsscsr7"}, + {ARM64_SYSREG_TRCSSPCICR0, "trcsspcicr0"}, + {ARM64_SYSREG_TRCSSPCICR1, "trcsspcicr1"}, + {ARM64_SYSREG_TRCSSPCICR2, "trcsspcicr2"}, + {ARM64_SYSREG_TRCSSPCICR3, "trcsspcicr3"}, + {ARM64_SYSREG_TRCSSPCICR4, "trcsspcicr4"}, + {ARM64_SYSREG_TRCSSPCICR5, "trcsspcicr5"}, + {ARM64_SYSREG_TRCSSPCICR6, "trcsspcicr6"}, + {ARM64_SYSREG_TRCSSPCICR7, "trcsspcicr7"}, + {ARM64_SYSREG_TRCPDCR, "trcpdcr"}, + {ARM64_SYSREG_TRCACVR0, "trcacvr0"}, + {ARM64_SYSREG_TRCACVR1, "trcacvr1"}, + {ARM64_SYSREG_TRCACVR2, "trcacvr2"}, + {ARM64_SYSREG_TRCACVR3, "trcacvr3"}, + {ARM64_SYSREG_TRCACVR4, "trcacvr4"}, + {ARM64_SYSREG_TRCACVR5, "trcacvr5"}, + {ARM64_SYSREG_TRCACVR6, "trcacvr6"}, + {ARM64_SYSREG_TRCACVR7, "trcacvr7"}, + {ARM64_SYSREG_TRCACVR8, "trcacvr8"}, + {ARM64_SYSREG_TRCACVR9, "trcacvr9"}, + {ARM64_SYSREG_TRCACVR10, "trcacvr10"}, + {ARM64_SYSREG_TRCACVR11, "trcacvr11"}, + {ARM64_SYSREG_TRCACVR12, "trcacvr12"}, + {ARM64_SYSREG_TRCACVR13, "trcacvr13"}, + {ARM64_SYSREG_TRCACVR14, "trcacvr14"}, + {ARM64_SYSREG_TRCACVR15, "trcacvr15"}, + {ARM64_SYSREG_TRCACATR0, "trcacatr0"}, + {ARM64_SYSREG_TRCACATR1, "trcacatr1"}, + {ARM64_SYSREG_TRCACATR2, "trcacatr2"}, + {ARM64_SYSREG_TRCACATR3, "trcacatr3"}, + {ARM64_SYSREG_TRCACATR4, "trcacatr4"}, + {ARM64_SYSREG_TRCACATR5, "trcacatr5"}, + {ARM64_SYSREG_TRCACATR6, "trcacatr6"}, + {ARM64_SYSREG_TRCACATR7, "trcacatr7"}, + {ARM64_SYSREG_TRCACATR8, "trcacatr8"}, + {ARM64_SYSREG_TRCACATR9, "trcacatr9"}, + {ARM64_SYSREG_TRCACATR10, "trcacatr10"}, + {ARM64_SYSREG_TRCACATR11, "trcacatr11"}, + {ARM64_SYSREG_TRCACATR12, "trcacatr12"}, + {ARM64_SYSREG_TRCACATR13, "trcacatr13"}, + {ARM64_SYSREG_TRCACATR14, "trcacatr14"}, + {ARM64_SYSREG_TRCACATR15, "trcacatr15"}, + {ARM64_SYSREG_TRCDVCVR0, "trcdvcvr0"}, + {ARM64_SYSREG_TRCDVCVR1, "trcdvcvr1"}, + {ARM64_SYSREG_TRCDVCVR2, "trcdvcvr2"}, + {ARM64_SYSREG_TRCDVCVR3, "trcdvcvr3"}, + {ARM64_SYSREG_TRCDVCVR4, "trcdvcvr4"}, + {ARM64_SYSREG_TRCDVCVR5, "trcdvcvr5"}, + {ARM64_SYSREG_TRCDVCVR6, "trcdvcvr6"}, + {ARM64_SYSREG_TRCDVCVR7, "trcdvcvr7"}, + {ARM64_SYSREG_TRCDVCMR0, "trcdvcmr0"}, + {ARM64_SYSREG_TRCDVCMR1, "trcdvcmr1"}, + {ARM64_SYSREG_TRCDVCMR2, "trcdvcmr2"}, + {ARM64_SYSREG_TRCDVCMR3, "trcdvcmr3"}, + {ARM64_SYSREG_TRCDVCMR4, "trcdvcmr4"}, + {ARM64_SYSREG_TRCDVCMR5, "trcdvcmr5"}, + {ARM64_SYSREG_TRCDVCMR6, "trcdvcmr6"}, + {ARM64_SYSREG_TRCDVCMR7, "trcdvcmr7"}, + {ARM64_SYSREG_TRCCIDCVR0, "trccidcvr0"}, + {ARM64_SYSREG_TRCCIDCVR1, "trccidcvr1"}, + {ARM64_SYSREG_TRCCIDCVR2, "trccidcvr2"}, + {ARM64_SYSREG_TRCCIDCVR3, "trccidcvr3"}, + {ARM64_SYSREG_TRCCIDCVR4, "trccidcvr4"}, + {ARM64_SYSREG_TRCCIDCVR5, "trccidcvr5"}, + {ARM64_SYSREG_TRCCIDCVR6, "trccidcvr6"}, + {ARM64_SYSREG_TRCCIDCVR7, "trccidcvr7"}, + {ARM64_SYSREG_TRCVMIDCVR0, "trcvmidcvr0"}, + {ARM64_SYSREG_TRCVMIDCVR1, "trcvmidcvr1"}, + {ARM64_SYSREG_TRCVMIDCVR2, "trcvmidcvr2"}, + {ARM64_SYSREG_TRCVMIDCVR3, "trcvmidcvr3"}, + {ARM64_SYSREG_TRCVMIDCVR4, "trcvmidcvr4"}, + {ARM64_SYSREG_TRCVMIDCVR5, "trcvmidcvr5"}, + {ARM64_SYSREG_TRCVMIDCVR6, "trcvmidcvr6"}, + {ARM64_SYSREG_TRCVMIDCVR7, "trcvmidcvr7"}, + {ARM64_SYSREG_TRCCIDCCTLR0, "trccidcctlr0"}, + {ARM64_SYSREG_TRCCIDCCTLR1, "trccidcctlr1"}, + {ARM64_SYSREG_TRCVMIDCCTLR0, "trcvmidcctlr0"}, + {ARM64_SYSREG_TRCVMIDCCTLR1, "trcvmidcctlr1"}, + {ARM64_SYSREG_TRCITCTRL, "trcitctrl"}, + {ARM64_SYSREG_TRCCLAIMSET, "trcclaimset"}, + {ARM64_SYSREG_TRCCLAIMCLR, "trcclaimclr"}, // GICv3 registers - {A64SysReg_ICC_BPR1_EL1, "icc_bpr1_el1"}, - {A64SysReg_ICC_BPR0_EL1, "icc_bpr0_el1"}, - {A64SysReg_ICC_PMR_EL1, "icc_pmr_el1"}, - {A64SysReg_ICC_CTLR_EL1, "icc_ctlr_el1"}, - {A64SysReg_ICC_CTLR_EL3, "icc_ctlr_el3"}, - {A64SysReg_ICC_SRE_EL1, "icc_sre_el1"}, - {A64SysReg_ICC_SRE_EL2, "icc_sre_el2"}, - {A64SysReg_ICC_SRE_EL3, "icc_sre_el3"}, - {A64SysReg_ICC_IGRPEN0_EL1, "icc_igrpen0_el1"}, - {A64SysReg_ICC_IGRPEN1_EL1, "icc_igrpen1_el1"}, - {A64SysReg_ICC_IGRPEN1_EL3, "icc_igrpen1_el3"}, - {A64SysReg_ICC_SEIEN_EL1, "icc_seien_el1"}, - {A64SysReg_ICC_AP0R0_EL1, "icc_ap0r0_el1"}, - {A64SysReg_ICC_AP0R1_EL1, "icc_ap0r1_el1"}, - {A64SysReg_ICC_AP0R2_EL1, "icc_ap0r2_el1"}, - {A64SysReg_ICC_AP0R3_EL1, "icc_ap0r3_el1"}, - {A64SysReg_ICC_AP1R0_EL1, "icc_ap1r0_el1"}, - {A64SysReg_ICC_AP1R1_EL1, "icc_ap1r1_el1"}, - {A64SysReg_ICC_AP1R2_EL1, "icc_ap1r2_el1"}, - {A64SysReg_ICC_AP1R3_EL1, "icc_ap1r3_el1"}, - {A64SysReg_ICH_AP0R0_EL2, "ich_ap0r0_el2"}, - {A64SysReg_ICH_AP0R1_EL2, "ich_ap0r1_el2"}, - {A64SysReg_ICH_AP0R2_EL2, "ich_ap0r2_el2"}, - {A64SysReg_ICH_AP0R3_EL2, "ich_ap0r3_el2"}, - {A64SysReg_ICH_AP1R0_EL2, "ich_ap1r0_el2"}, - {A64SysReg_ICH_AP1R1_EL2, "ich_ap1r1_el2"}, - {A64SysReg_ICH_AP1R2_EL2, "ich_ap1r2_el2"}, - {A64SysReg_ICH_AP1R3_EL2, "ich_ap1r3_el2"}, - {A64SysReg_ICH_HCR_EL2, "ich_hcr_el2"}, - {A64SysReg_ICH_MISR_EL2, "ich_misr_el2"}, - {A64SysReg_ICH_VMCR_EL2, "ich_vmcr_el2"}, - {A64SysReg_ICH_VSEIR_EL2, "ich_vseir_el2"}, - {A64SysReg_ICH_LR0_EL2, "ich_lr0_el2"}, - {A64SysReg_ICH_LR1_EL2, "ich_lr1_el2"}, - {A64SysReg_ICH_LR2_EL2, "ich_lr2_el2"}, - {A64SysReg_ICH_LR3_EL2, "ich_lr3_el2"}, - {A64SysReg_ICH_LR4_EL2, "ich_lr4_el2"}, - {A64SysReg_ICH_LR5_EL2, "ich_lr5_el2"}, - {A64SysReg_ICH_LR6_EL2, "ich_lr6_el2"}, - {A64SysReg_ICH_LR7_EL2, "ich_lr7_el2"}, - {A64SysReg_ICH_LR8_EL2, "ich_lr8_el2"}, - {A64SysReg_ICH_LR9_EL2, "ich_lr9_el2"}, - {A64SysReg_ICH_LR10_EL2, "ich_lr10_el2"}, - {A64SysReg_ICH_LR11_EL2, "ich_lr11_el2"}, - {A64SysReg_ICH_LR12_EL2, "ich_lr12_el2"}, - {A64SysReg_ICH_LR13_EL2, "ich_lr13_el2"}, - {A64SysReg_ICH_LR14_EL2, "ich_lr14_el2"}, - {A64SysReg_ICH_LR15_EL2, "ich_lr15_el2"}, - {A64SysReg_MDCCSR_EL0, "mdccsr_el0"}, - {A64SysReg_DBGDTRRX_EL0, "dbgdtrrx_el0"}, - {A64SysReg_MDRAR_EL1, "mdrar_el1"}, - {A64SysReg_OSLSR_EL1, "oslsr_el1"}, - {A64SysReg_DBGAUTHSTATUS_EL1, "dbgauthstatus_el1"}, - {A64SysReg_PMCEID0_EL0, "pmceid0_el0"}, - {A64SysReg_PMCEID1_EL0, "pmceid1_el0"}, - {A64SysReg_MIDR_EL1, "midr_el1"}, - {A64SysReg_CCSIDR_EL1, "ccsidr_el1"}, - {A64SysReg_CLIDR_EL1, "clidr_el1"}, - {A64SysReg_CTR_EL0, "ctr_el0"}, - {A64SysReg_MPIDR_EL1, "mpidr_el1"}, - {A64SysReg_REVIDR_EL1, "revidr_el1"}, - {A64SysReg_AIDR_EL1, "aidr_el1"}, - {A64SysReg_DCZID_EL0, "dczid_el0"}, - {A64SysReg_ID_PFR0_EL1, "id_pfr0_el1"}, - {A64SysReg_ID_PFR1_EL1, "id_pfr1_el1"}, - {A64SysReg_ID_DFR0_EL1, "id_dfr0_el1"}, - {A64SysReg_ID_AFR0_EL1, "id_afr0_el1"}, - {A64SysReg_ID_MMFR0_EL1, "id_mmfr0_el1"}, - {A64SysReg_ID_MMFR1_EL1, "id_mmfr1_el1"}, - {A64SysReg_ID_MMFR2_EL1, "id_mmfr2_el1"}, - {A64SysReg_ID_MMFR3_EL1, "id_mmfr3_el1"}, - {A64SysReg_ID_ISAR0_EL1, "id_isar0_el1"}, - {A64SysReg_ID_ISAR1_EL1, "id_isar1_el1"}, - {A64SysReg_ID_ISAR2_EL1, "id_isar2_el1"}, - {A64SysReg_ID_ISAR3_EL1, "id_isar3_el1"}, - {A64SysReg_ID_ISAR4_EL1, "id_isar4_el1"}, - {A64SysReg_ID_ISAR5_EL1, "id_isar5_el1"}, - {A64SysReg_ID_A64PFR0_EL1, "id_aa64pfr0_el1"}, - {A64SysReg_ID_A64PFR1_EL1, "id_aa64pfr1_el1"}, - {A64SysReg_ID_A64DFR0_EL1, "id_aa64dfr0_el1"}, - {A64SysReg_ID_A64DFR1_EL1, "id_aa64dfr1_el1"}, - {A64SysReg_ID_A64AFR0_EL1, "id_aa64afr0_el1"}, - {A64SysReg_ID_A64AFR1_EL1, "id_aa64afr1_el1"}, - {A64SysReg_ID_A64ISAR0_EL1, "id_aa64isar0_el1"}, - {A64SysReg_ID_A64ISAR1_EL1, "id_aa64isar1_el1"}, - {A64SysReg_ID_A64MMFR0_EL1, "id_aa64mmfr0_el1"}, - {A64SysReg_ID_A64MMFR1_EL1, "id_aa64mmfr1_el1"}, - {A64SysReg_MVFR0_EL1, "mvfr0_el1"}, - {A64SysReg_MVFR1_EL1, "mvfr1_el1"}, - {A64SysReg_MVFR2_EL1, "mvfr2_el1"}, - {A64SysReg_RVBAR_EL1, "rvbar_el1"}, - {A64SysReg_RVBAR_EL2, "rvbar_el2"}, - {A64SysReg_RVBAR_EL3, "rvbar_el3"}, - {A64SysReg_ISR_EL1, "isr_el1"}, - {A64SysReg_CNTPCT_EL0, "cntpct_el0"}, - {A64SysReg_CNTVCT_EL0, "cntvct_el0"}, + {ARM64_SYSREG_ICC_BPR1_EL1, "icc_bpr1_el1"}, + {ARM64_SYSREG_ICC_BPR0_EL1, "icc_bpr0_el1"}, + {ARM64_SYSREG_ICC_PMR_EL1, "icc_pmr_el1"}, + {ARM64_SYSREG_ICC_CTLR_EL1, "icc_ctlr_el1"}, + {ARM64_SYSREG_ICC_CTLR_EL3, "icc_ctlr_el3"}, + {ARM64_SYSREG_ICC_SRE_EL1, "icc_sre_el1"}, + {ARM64_SYSREG_ICC_SRE_EL2, "icc_sre_el2"}, + {ARM64_SYSREG_ICC_SRE_EL3, "icc_sre_el3"}, + {ARM64_SYSREG_ICC_IGRPEN0_EL1, "icc_igrpen0_el1"}, + {ARM64_SYSREG_ICC_IGRPEN1_EL1, "icc_igrpen1_el1"}, + {ARM64_SYSREG_ICC_IGRPEN1_EL3, "icc_igrpen1_el3"}, + {ARM64_SYSREG_ICC_SEIEN_EL1, "icc_seien_el1"}, + {ARM64_SYSREG_ICC_AP0R0_EL1, "icc_ap0r0_el1"}, + {ARM64_SYSREG_ICC_AP0R1_EL1, "icc_ap0r1_el1"}, + {ARM64_SYSREG_ICC_AP0R2_EL1, "icc_ap0r2_el1"}, + {ARM64_SYSREG_ICC_AP0R3_EL1, "icc_ap0r3_el1"}, + {ARM64_SYSREG_ICC_AP1R0_EL1, "icc_ap1r0_el1"}, + {ARM64_SYSREG_ICC_AP1R1_EL1, "icc_ap1r1_el1"}, + {ARM64_SYSREG_ICC_AP1R2_EL1, "icc_ap1r2_el1"}, + {ARM64_SYSREG_ICC_AP1R3_EL1, "icc_ap1r3_el1"}, + {ARM64_SYSREG_ICH_AP0R0_EL2, "ich_ap0r0_el2"}, + {ARM64_SYSREG_ICH_AP0R1_EL2, "ich_ap0r1_el2"}, + {ARM64_SYSREG_ICH_AP0R2_EL2, "ich_ap0r2_el2"}, + {ARM64_SYSREG_ICH_AP0R3_EL2, "ich_ap0r3_el2"}, + {ARM64_SYSREG_ICH_AP1R0_EL2, "ich_ap1r0_el2"}, + {ARM64_SYSREG_ICH_AP1R1_EL2, "ich_ap1r1_el2"}, + {ARM64_SYSREG_ICH_AP1R2_EL2, "ich_ap1r2_el2"}, + {ARM64_SYSREG_ICH_AP1R3_EL2, "ich_ap1r3_el2"}, + {ARM64_SYSREG_ICH_HCR_EL2, "ich_hcr_el2"}, + {ARM64_SYSREG_ICH_MISR_EL2, "ich_misr_el2"}, + {ARM64_SYSREG_ICH_VMCR_EL2, "ich_vmcr_el2"}, + {ARM64_SYSREG_ICH_VSEIR_EL2, "ich_vseir_el2"}, + {ARM64_SYSREG_ICH_LR0_EL2, "ich_lr0_el2"}, + {ARM64_SYSREG_ICH_LR1_EL2, "ich_lr1_el2"}, + {ARM64_SYSREG_ICH_LR2_EL2, "ich_lr2_el2"}, + {ARM64_SYSREG_ICH_LR3_EL2, "ich_lr3_el2"}, + {ARM64_SYSREG_ICH_LR4_EL2, "ich_lr4_el2"}, + {ARM64_SYSREG_ICH_LR5_EL2, "ich_lr5_el2"}, + {ARM64_SYSREG_ICH_LR6_EL2, "ich_lr6_el2"}, + {ARM64_SYSREG_ICH_LR7_EL2, "ich_lr7_el2"}, + {ARM64_SYSREG_ICH_LR8_EL2, "ich_lr8_el2"}, + {ARM64_SYSREG_ICH_LR9_EL2, "ich_lr9_el2"}, + {ARM64_SYSREG_ICH_LR10_EL2, "ich_lr10_el2"}, + {ARM64_SYSREG_ICH_LR11_EL2, "ich_lr11_el2"}, + {ARM64_SYSREG_ICH_LR12_EL2, "ich_lr12_el2"}, + {ARM64_SYSREG_ICH_LR13_EL2, "ich_lr13_el2"}, + {ARM64_SYSREG_ICH_LR14_EL2, "ich_lr14_el2"}, + {ARM64_SYSREG_ICH_LR15_EL2, "ich_lr15_el2"}, + {ARM64_SYSREG_MDCCSR_EL0, "mdccsr_el0"}, + {ARM64_SYSREG_DBGDTRRX_EL0, "dbgdtrrx_el0"}, + {ARM64_SYSREG_MDRAR_EL1, "mdrar_el1"}, + {ARM64_SYSREG_OSLSR_EL1, "oslsr_el1"}, + {ARM64_SYSREG_DBGAUTHSTATUS_EL1, "dbgauthstatus_el1"}, + {ARM64_SYSREG_PMCEID0_EL0, "pmceid0_el0"}, + {ARM64_SYSREG_PMCEID1_EL0, "pmceid1_el0"}, + {ARM64_SYSREG_MIDR_EL1, "midr_el1"}, + {ARM64_SYSREG_CCSIDR_EL1, "ccsidr_el1"}, + {ARM64_SYSREG_CLIDR_EL1, "clidr_el1"}, + {ARM64_SYSREG_CTR_EL0, "ctr_el0"}, + {ARM64_SYSREG_MPIDR_EL1, "mpidr_el1"}, + {ARM64_SYSREG_REVIDR_EL1, "revidr_el1"}, + {ARM64_SYSREG_AIDR_EL1, "aidr_el1"}, + {ARM64_SYSREG_DCZID_EL0, "dczid_el0"}, + {ARM64_SYSREG_ID_PFR0_EL1, "id_pfr0_el1"}, + {ARM64_SYSREG_ID_PFR1_EL1, "id_pfr1_el1"}, + {ARM64_SYSREG_ID_DFR0_EL1, "id_dfr0_el1"}, + {ARM64_SYSREG_ID_AFR0_EL1, "id_afr0_el1"}, + {ARM64_SYSREG_ID_MMFR0_EL1, "id_mmfr0_el1"}, + {ARM64_SYSREG_ID_MMFR1_EL1, "id_mmfr1_el1"}, + {ARM64_SYSREG_ID_MMFR2_EL1, "id_mmfr2_el1"}, + {ARM64_SYSREG_ID_MMFR3_EL1, "id_mmfr3_el1"}, + {ARM64_SYSREG_ID_ISAR0_EL1, "id_isar0_el1"}, + {ARM64_SYSREG_ID_ISAR1_EL1, "id_isar1_el1"}, + {ARM64_SYSREG_ID_ISAR2_EL1, "id_isar2_el1"}, + {ARM64_SYSREG_ID_ISAR3_EL1, "id_isar3_el1"}, + {ARM64_SYSREG_ID_ISAR4_EL1, "id_isar4_el1"}, + {ARM64_SYSREG_ID_ISAR5_EL1, "id_isar5_el1"}, + {ARM64_SYSREG_ID_AA64PFR0_EL1, "id_aa64pfr0_el1"}, + {ARM64_SYSREG_ID_AA64PFR1_EL1, "id_aa64pfr1_el1"}, + {ARM64_SYSREG_ID_AA64DFR0_EL1, "id_aa64dfr0_el1"}, + {ARM64_SYSREG_ID_AA64DFR1_EL1, "id_aa64dfr1_el1"}, + {ARM64_SYSREG_ID_AA64AFR0_EL1, "id_aa64afr0_el1"}, + {ARM64_SYSREG_ID_AA64AFR1_EL1, "id_aa64afr1_el1"}, + {ARM64_SYSREG_ID_AA64ISAR0_EL1, "id_aa64isar0_el1"}, + {ARM64_SYSREG_ID_AA64ISAR1_EL1, "id_aa64isar1_el1"}, + {ARM64_SYSREG_ID_AA64MMFR0_EL1, "id_aa64mmfr0_el1"}, + {ARM64_SYSREG_ID_AA64MMFR1_EL1, "id_aa64mmfr1_el1"}, + {ARM64_SYSREG_MVFR0_EL1, "mvfr0_el1"}, + {ARM64_SYSREG_MVFR1_EL1, "mvfr1_el1"}, + {ARM64_SYSREG_MVFR2_EL1, "mvfr2_el1"}, + {ARM64_SYSREG_RVBAR_EL1, "rvbar_el1"}, + {ARM64_SYSREG_RVBAR_EL2, "rvbar_el2"}, + {ARM64_SYSREG_RVBAR_EL3, "rvbar_el3"}, + {ARM64_SYSREG_ISR_EL1, "isr_el1"}, + {ARM64_SYSREG_CNTPCT_EL0, "cntpct_el0"}, + {ARM64_SYSREG_CNTVCT_EL0, "cntvct_el0"}, // Trace registers - {A64SysReg_TRCSTATR, "trcstatr"}, - {A64SysReg_TRCIDR8, "trcidr8"}, - {A64SysReg_TRCIDR9, "trcidr9"}, - {A64SysReg_TRCIDR10, "trcidr10"}, - {A64SysReg_TRCIDR11, "trcidr11"}, - {A64SysReg_TRCIDR12, "trcidr12"}, - {A64SysReg_TRCIDR13, "trcidr13"}, - {A64SysReg_TRCIDR0, "trcidr0"}, - {A64SysReg_TRCIDR1, "trcidr1"}, - {A64SysReg_TRCIDR2, "trcidr2"}, - {A64SysReg_TRCIDR3, "trcidr3"}, - {A64SysReg_TRCIDR4, "trcidr4"}, - {A64SysReg_TRCIDR5, "trcidr5"}, - {A64SysReg_TRCIDR6, "trcidr6"}, - {A64SysReg_TRCIDR7, "trcidr7"}, - {A64SysReg_TRCOSLSR, "trcoslsr"}, - {A64SysReg_TRCPDSR, "trcpdsr"}, - {A64SysReg_TRCDEVAFF0, "trcdevaff0"}, - {A64SysReg_TRCDEVAFF1, "trcdevaff1"}, - {A64SysReg_TRCLSR, "trclsr"}, - {A64SysReg_TRCAUTHSTATUS, "trcauthstatus"}, - {A64SysReg_TRCDEVARCH, "trcdevarch"}, - {A64SysReg_TRCDEVID, "trcdevid"}, - {A64SysReg_TRCDEVTYPE, "trcdevtype"}, - {A64SysReg_TRCPIDR4, "trcpidr4"}, - {A64SysReg_TRCPIDR5, "trcpidr5"}, - {A64SysReg_TRCPIDR6, "trcpidr6"}, - {A64SysReg_TRCPIDR7, "trcpidr7"}, - {A64SysReg_TRCPIDR0, "trcpidr0"}, - {A64SysReg_TRCPIDR1, "trcpidr1"}, - {A64SysReg_TRCPIDR2, "trcpidr2"}, - {A64SysReg_TRCPIDR3, "trcpidr3"}, - {A64SysReg_TRCCIDR0, "trccidr0"}, - {A64SysReg_TRCCIDR1, "trccidr1"}, - {A64SysReg_TRCCIDR2, "trccidr2"}, - {A64SysReg_TRCCIDR3, "trccidr3"}, + {ARM64_SYSREG_TRCSTATR, "trcstatr"}, + {ARM64_SYSREG_TRCIDR8, "trcidr8"}, + {ARM64_SYSREG_TRCIDR9, "trcidr9"}, + {ARM64_SYSREG_TRCIDR10, "trcidr10"}, + {ARM64_SYSREG_TRCIDR11, "trcidr11"}, + {ARM64_SYSREG_TRCIDR12, "trcidr12"}, + {ARM64_SYSREG_TRCIDR13, "trcidr13"}, + {ARM64_SYSREG_TRCIDR0, "trcidr0"}, + {ARM64_SYSREG_TRCIDR1, "trcidr1"}, + {ARM64_SYSREG_TRCIDR2, "trcidr2"}, + {ARM64_SYSREG_TRCIDR3, "trcidr3"}, + {ARM64_SYSREG_TRCIDR4, "trcidr4"}, + {ARM64_SYSREG_TRCIDR5, "trcidr5"}, + {ARM64_SYSREG_TRCIDR6, "trcidr6"}, + {ARM64_SYSREG_TRCIDR7, "trcidr7"}, + {ARM64_SYSREG_TRCOSLSR, "trcoslsr"}, + {ARM64_SYSREG_TRCPDSR, "trcpdsr"}, + {ARM64_SYSREG_TRCDEVAFF0, "trcdevaff0"}, + {ARM64_SYSREG_TRCDEVAFF1, "trcdevaff1"}, + {ARM64_SYSREG_TRCLSR, "trclsr"}, + {ARM64_SYSREG_TRCAUTHSTATUS, "trcauthstatus"}, + {ARM64_SYSREG_TRCDEVARCH, "trcdevarch"}, + {ARM64_SYSREG_TRCDEVID, "trcdevid"}, + {ARM64_SYSREG_TRCDEVTYPE, "trcdevtype"}, + {ARM64_SYSREG_TRCPIDR4, "trcpidr4"}, + {ARM64_SYSREG_TRCPIDR5, "trcpidr5"}, + {ARM64_SYSREG_TRCPIDR6, "trcpidr6"}, + {ARM64_SYSREG_TRCPIDR7, "trcpidr7"}, + {ARM64_SYSREG_TRCPIDR0, "trcpidr0"}, + {ARM64_SYSREG_TRCPIDR1, "trcpidr1"}, + {ARM64_SYSREG_TRCPIDR2, "trcpidr2"}, + {ARM64_SYSREG_TRCPIDR3, "trcpidr3"}, + {ARM64_SYSREG_TRCCIDR0, "trccidr0"}, + {ARM64_SYSREG_TRCCIDR1, "trccidr1"}, + {ARM64_SYSREG_TRCCIDR2, "trccidr2"}, + {ARM64_SYSREG_TRCCIDR3, "trccidr3"}, // GICv3 registers - {A64SysReg_ICC_IAR1_EL1, "icc_iar1_el1"}, - {A64SysReg_ICC_IAR0_EL1, "icc_iar0_el1"}, - {A64SysReg_ICC_HPPIR1_EL1, "icc_hppir1_el1"}, - {A64SysReg_ICC_HPPIR0_EL1, "icc_hppir0_el1"}, - {A64SysReg_ICC_RPR_EL1, "icc_rpr_el1"}, - {A64SysReg_ICH_VTR_EL2, "ich_vtr_el2"}, - {A64SysReg_ICH_EISR_EL2, "ich_eisr_el2"}, - {A64SysReg_ICH_ELSR_EL2, "ich_elsr_el2"}, + {ARM64_SYSREG_ICC_IAR1_EL1, "icc_iar1_el1"}, + {ARM64_SYSREG_ICC_IAR0_EL1, "icc_iar0_el1"}, + {ARM64_SYSREG_ICC_HPPIR1_EL1, "icc_hppir1_el1"}, + {ARM64_SYSREG_ICC_HPPIR0_EL1, "icc_hppir0_el1"}, + {ARM64_SYSREG_ICC_RPR_EL1, "icc_rpr_el1"}, + {ARM64_SYSREG_ICH_VTR_EL2, "ich_vtr_el2"}, + {ARM64_SYSREG_ICH_EISR_EL2, "ich_eisr_el2"}, + {ARM64_SYSREG_ICH_ELRSR_EL2, "ich_elrsr_el2"}, // PSTATE - those are probably not registers {ARM64_PSTATE_SPSEL, "spsel"}, @@ -929,580 +928,580 @@ void Capstone2LlvmIrTranslatorArm64_impl::initializeRegTypeMap() {ARM64_REG_PC, i64}, // System registers. - {A64SysReg_OSDTRRX_EL1, i64}, - {A64SysReg_OSDTRTX_EL1, i64}, - {A64SysReg_TEECR32_EL1, i64}, - {A64SysReg_MDCCINT_EL1, i64}, - {A64SysReg_MDSCR_EL1, i64}, - {A64SysReg_DBGDTR_EL0, i64}, - {A64SysReg_OSECCR_EL1, i64}, - {A64SysReg_DBGVCR32_EL2, i64}, - {A64SysReg_DBGBVR0_EL1, i64}, - {A64SysReg_DBGBVR1_EL1, i64}, - {A64SysReg_DBGBVR2_EL1, i64}, - {A64SysReg_DBGBVR3_EL1, i64}, - {A64SysReg_DBGBVR4_EL1, i64}, - {A64SysReg_DBGBVR5_EL1, i64}, - {A64SysReg_DBGBVR6_EL1, i64}, - {A64SysReg_DBGBVR7_EL1, i64}, - {A64SysReg_DBGBVR8_EL1, i64}, - {A64SysReg_DBGBVR9_EL1, i64}, - {A64SysReg_DBGBVR10_EL1, i64}, - {A64SysReg_DBGBVR11_EL1, i64}, - {A64SysReg_DBGBVR12_EL1, i64}, - {A64SysReg_DBGBVR13_EL1, i64}, - {A64SysReg_DBGBVR14_EL1, i64}, - {A64SysReg_DBGBVR15_EL1, i64}, - {A64SysReg_DBGBCR0_EL1, i64}, - {A64SysReg_DBGBCR1_EL1, i64}, - {A64SysReg_DBGBCR2_EL1, i64}, - {A64SysReg_DBGBCR3_EL1, i64}, - {A64SysReg_DBGBCR4_EL1, i64}, - {A64SysReg_DBGBCR5_EL1, i64}, - {A64SysReg_DBGBCR6_EL1, i64}, - {A64SysReg_DBGBCR7_EL1, i64}, - {A64SysReg_DBGBCR8_EL1, i64}, - {A64SysReg_DBGBCR9_EL1, i64}, - {A64SysReg_DBGBCR10_EL1, i64}, - {A64SysReg_DBGBCR11_EL1, i64}, - {A64SysReg_DBGBCR12_EL1, i64}, - {A64SysReg_DBGBCR13_EL1, i64}, - {A64SysReg_DBGBCR14_EL1, i64}, - {A64SysReg_DBGBCR15_EL1, i64}, - {A64SysReg_DBGWVR0_EL1, i64}, - {A64SysReg_DBGWVR1_EL1, i64}, - {A64SysReg_DBGWVR2_EL1, i64}, - {A64SysReg_DBGWVR3_EL1, i64}, - {A64SysReg_DBGWVR4_EL1, i64}, - {A64SysReg_DBGWVR5_EL1, i64}, - {A64SysReg_DBGWVR6_EL1, i64}, - {A64SysReg_DBGWVR7_EL1, i64}, - {A64SysReg_DBGWVR8_EL1, i64}, - {A64SysReg_DBGWVR9_EL1, i64}, - {A64SysReg_DBGWVR10_EL1, i64}, - {A64SysReg_DBGWVR11_EL1, i64}, - {A64SysReg_DBGWVR12_EL1, i64}, - {A64SysReg_DBGWVR13_EL1, i64}, - {A64SysReg_DBGWVR14_EL1, i64}, - {A64SysReg_DBGWVR15_EL1, i64}, - {A64SysReg_DBGWCR0_EL1, i64}, - {A64SysReg_DBGWCR1_EL1, i64}, - {A64SysReg_DBGWCR2_EL1, i64}, - {A64SysReg_DBGWCR3_EL1, i64}, - {A64SysReg_DBGWCR4_EL1, i64}, - {A64SysReg_DBGWCR5_EL1, i64}, - {A64SysReg_DBGWCR6_EL1, i64}, - {A64SysReg_DBGWCR7_EL1, i64}, - {A64SysReg_DBGWCR8_EL1, i64}, - {A64SysReg_DBGWCR9_EL1, i64}, - {A64SysReg_DBGWCR10_EL1, i64}, - {A64SysReg_DBGWCR11_EL1, i64}, - {A64SysReg_DBGWCR12_EL1, i64}, - {A64SysReg_DBGWCR13_EL1, i64}, - {A64SysReg_DBGWCR14_EL1, i64}, - {A64SysReg_DBGWCR15_EL1, i64}, - {A64SysReg_TEEHBR32_EL1, i64}, - {A64SysReg_OSDLR_EL1, i64}, - {A64SysReg_DBGPRCR_EL1, i64}, - {A64SysReg_DBGCLAIMSET_EL1, i64}, - {A64SysReg_DBGCLAIMCLR_EL1, i64}, - {A64SysReg_CSSELR_EL1, i64}, - {A64SysReg_VPIDR_EL2, i64}, - {A64SysReg_VMPIDR_EL2, i64}, - {A64SysReg_CPACR_EL1, i64}, - {A64SysReg_SCTLR_EL1, i64}, - {A64SysReg_SCTLR_EL2, i64}, - {A64SysReg_SCTLR_EL3, i64}, - {A64SysReg_ACTLR_EL1, i64}, - {A64SysReg_ACTLR_EL2, i64}, - {A64SysReg_ACTLR_EL3, i64}, - {A64SysReg_HCR_EL2, i64}, - {A64SysReg_SCR_EL3, i64}, - {A64SysReg_MDCR_EL2, i64}, - {A64SysReg_SDER32_EL3, i64}, - {A64SysReg_CPTR_EL2, i64}, - {A64SysReg_CPTR_EL3, i64}, - {A64SysReg_HSTR_EL2, i64}, - {A64SysReg_HACR_EL2, i64}, - {A64SysReg_MDCR_EL3, i64}, - {A64SysReg_TTBR0_EL1, i64}, - {A64SysReg_TTBR0_EL2, i64}, - {A64SysReg_TTBR0_EL3, i64}, - {A64SysReg_TTBR1_EL1, i64}, - {A64SysReg_TCR_EL1, i64}, - {A64SysReg_TCR_EL2, i64}, - {A64SysReg_TCR_EL3, i64}, - {A64SysReg_VTTBR_EL2, i64}, - {A64SysReg_VTCR_EL2, i64}, - {A64SysReg_DACR32_EL2, i64}, - {A64SysReg_SPSR_EL1, i64}, - {A64SysReg_SPSR_EL2, i64}, - {A64SysReg_SPSR_EL3, i64}, - {A64SysReg_ELR_EL1, i64}, - {A64SysReg_ELR_EL2, i64}, - {A64SysReg_ELR_EL3, i64}, - {A64SysReg_SP_EL0, i64}, - {A64SysReg_SP_EL1, i64}, - {A64SysReg_SP_EL2, i64}, - {A64SysReg_SPSel, i64}, - {A64SysReg_NZCV, i64}, - {A64SysReg_DAIF, i64}, - {A64SysReg_CurrentEL, i64}, - {A64SysReg_SPSR_irq, i64}, - {A64SysReg_SPSR_abt, i64}, - {A64SysReg_SPSR_und, i64}, - {A64SysReg_SPSR_fiq, i64}, - {A64SysReg_FPCR, i64}, - {A64SysReg_FPSR, i64}, - {A64SysReg_DSPSR_EL0, i64}, - {A64SysReg_DLR_EL0, i64}, - {A64SysReg_IFSR32_EL2, i64}, - {A64SysReg_AFSR0_EL1, i64}, - {A64SysReg_AFSR0_EL2, i64}, - {A64SysReg_AFSR0_EL3, i64}, - {A64SysReg_AFSR1_EL1, i64}, - {A64SysReg_AFSR1_EL2, i64}, - {A64SysReg_AFSR1_EL3, i64}, - {A64SysReg_ESR_EL1, i64}, - {A64SysReg_ESR_EL2, i64}, - {A64SysReg_ESR_EL3, i64}, - {A64SysReg_FPEXC32_EL2, i64}, - {A64SysReg_FAR_EL1, i64}, - {A64SysReg_FAR_EL2, i64}, - {A64SysReg_FAR_EL3, i64}, - {A64SysReg_HPFAR_EL2, i64}, - {A64SysReg_PAR_EL1, i64}, - {A64SysReg_PMCR_EL0, i64}, - {A64SysReg_PMCNTENSET_EL0, i64}, - {A64SysReg_PMCNTENCLR_EL0, i64}, - {A64SysReg_PMOVSCLR_EL0, i64}, - {A64SysReg_PMSELR_EL0, i64}, - {A64SysReg_PMCCNTR_EL0, i64}, - {A64SysReg_PMXEVTYPER_EL0, i64}, - {A64SysReg_PMXEVCNTR_EL0, i64}, - {A64SysReg_PMUSERENR_EL0, i64}, - {A64SysReg_PMINTENSET_EL1, i64}, - {A64SysReg_PMINTENCLR_EL1, i64}, - {A64SysReg_PMOVSSET_EL0, i64}, - {A64SysReg_MAIR_EL1, i64}, - {A64SysReg_MAIR_EL2, i64}, - {A64SysReg_MAIR_EL3, i64}, - {A64SysReg_AMAIR_EL1, i64}, - {A64SysReg_AMAIR_EL2, i64}, - {A64SysReg_AMAIR_EL3, i64}, - {A64SysReg_VBAR_EL1, i64}, - {A64SysReg_VBAR_EL2, i64}, - {A64SysReg_VBAR_EL3, i64}, - {A64SysReg_RMR_EL1, i64}, - {A64SysReg_RMR_EL2, i64}, - {A64SysReg_RMR_EL3, i64}, - {A64SysReg_CONTEXTIDR_EL1, i64}, - {A64SysReg_TPIDR_EL0, i64}, - {A64SysReg_TPIDR_EL2, i64}, - {A64SysReg_TPIDR_EL3, i64}, - {A64SysReg_TPIDRRO_EL0, i64}, - {A64SysReg_TPIDR_EL1, i64}, - {A64SysReg_CNTFRQ_EL0, i64}, - {A64SysReg_CNTVOFF_EL2, i64}, - {A64SysReg_CNTKCTL_EL1, i64}, - {A64SysReg_CNTHCTL_EL2, i64}, - {A64SysReg_CNTP_TVAL_EL0, i64}, - {A64SysReg_CNTHP_TVAL_EL2, i64}, - {A64SysReg_CNTPS_TVAL_EL1, i64}, - {A64SysReg_CNTP_CTL_EL0, i64}, - {A64SysReg_CNTHP_CTL_EL2, i64}, - {A64SysReg_CNTPS_CTL_EL1, i64}, - {A64SysReg_CNTP_CVAL_EL0, i64}, - {A64SysReg_CNTHP_CVAL_EL2, i64}, - {A64SysReg_CNTPS_CVAL_EL1, i64}, - {A64SysReg_CNTV_TVAL_EL0, i64}, - {A64SysReg_CNTV_CTL_EL0, i64}, - {A64SysReg_CNTV_CVAL_EL0, i64}, - {A64SysReg_PMEVCNTR0_EL0, i64}, - {A64SysReg_PMEVCNTR1_EL0, i64}, - {A64SysReg_PMEVCNTR2_EL0, i64}, - {A64SysReg_PMEVCNTR3_EL0, i64}, - {A64SysReg_PMEVCNTR4_EL0, i64}, - {A64SysReg_PMEVCNTR5_EL0, i64}, - {A64SysReg_PMEVCNTR6_EL0, i64}, - {A64SysReg_PMEVCNTR7_EL0, i64}, - {A64SysReg_PMEVCNTR8_EL0, i64}, - {A64SysReg_PMEVCNTR9_EL0, i64}, - {A64SysReg_PMEVCNTR10_EL0, i64}, - {A64SysReg_PMEVCNTR11_EL0, i64}, - {A64SysReg_PMEVCNTR12_EL0, i64}, - {A64SysReg_PMEVCNTR13_EL0, i64}, - {A64SysReg_PMEVCNTR14_EL0, i64}, - {A64SysReg_PMEVCNTR15_EL0, i64}, - {A64SysReg_PMEVCNTR16_EL0, i64}, - {A64SysReg_PMEVCNTR17_EL0, i64}, - {A64SysReg_PMEVCNTR18_EL0, i64}, - {A64SysReg_PMEVCNTR19_EL0, i64}, - {A64SysReg_PMEVCNTR20_EL0, i64}, - {A64SysReg_PMEVCNTR21_EL0, i64}, - {A64SysReg_PMEVCNTR22_EL0, i64}, - {A64SysReg_PMEVCNTR23_EL0, i64}, - {A64SysReg_PMEVCNTR24_EL0, i64}, - {A64SysReg_PMEVCNTR25_EL0, i64}, - {A64SysReg_PMEVCNTR26_EL0, i64}, - {A64SysReg_PMEVCNTR27_EL0, i64}, - {A64SysReg_PMEVCNTR28_EL0, i64}, - {A64SysReg_PMEVCNTR29_EL0, i64}, - {A64SysReg_PMEVCNTR30_EL0, i64}, - {A64SysReg_PMCCFILTR_EL0, i64}, - {A64SysReg_PMEVTYPER0_EL0, i64}, - {A64SysReg_PMEVTYPER1_EL0, i64}, - {A64SysReg_PMEVTYPER2_EL0, i64}, - {A64SysReg_PMEVTYPER3_EL0, i64}, - {A64SysReg_PMEVTYPER4_EL0, i64}, - {A64SysReg_PMEVTYPER5_EL0, i64}, - {A64SysReg_PMEVTYPER6_EL0, i64}, - {A64SysReg_PMEVTYPER7_EL0, i64}, - {A64SysReg_PMEVTYPER8_EL0, i64}, - {A64SysReg_PMEVTYPER9_EL0, i64}, - {A64SysReg_PMEVTYPER10_EL0, i64}, - {A64SysReg_PMEVTYPER11_EL0, i64}, - {A64SysReg_PMEVTYPER12_EL0, i64}, - {A64SysReg_PMEVTYPER13_EL0, i64}, - {A64SysReg_PMEVTYPER14_EL0, i64}, - {A64SysReg_PMEVTYPER15_EL0, i64}, - {A64SysReg_PMEVTYPER16_EL0, i64}, - {A64SysReg_PMEVTYPER17_EL0, i64}, - {A64SysReg_PMEVTYPER18_EL0, i64}, - {A64SysReg_PMEVTYPER19_EL0, i64}, - {A64SysReg_PMEVTYPER20_EL0, i64}, - {A64SysReg_PMEVTYPER21_EL0, i64}, - {A64SysReg_PMEVTYPER22_EL0, i64}, - {A64SysReg_PMEVTYPER23_EL0, i64}, - {A64SysReg_PMEVTYPER24_EL0, i64}, - {A64SysReg_PMEVTYPER25_EL0, i64}, - {A64SysReg_PMEVTYPER26_EL0, i64}, - {A64SysReg_PMEVTYPER27_EL0, i64}, - {A64SysReg_PMEVTYPER28_EL0, i64}, - {A64SysReg_PMEVTYPER29_EL0, i64}, - {A64SysReg_PMEVTYPER30_EL0, i64}, + {ARM64_SYSREG_OSDTRRX_EL1, i64}, + {ARM64_SYSREG_OSDTRTX_EL1, i64}, + {ARM64_SYSREG_TEECR32_EL1, i64}, + {ARM64_SYSREG_MDCCINT_EL1, i64}, + {ARM64_SYSREG_MDSCR_EL1, i64}, + {ARM64_SYSREG_DBGDTR_EL0, i64}, + {ARM64_SYSREG_OSECCR_EL1, i64}, + {ARM64_SYSREG_DBGVCR32_EL2, i64}, + {ARM64_SYSREG_DBGBVR0_EL1, i64}, + {ARM64_SYSREG_DBGBVR1_EL1, i64}, + {ARM64_SYSREG_DBGBVR2_EL1, i64}, + {ARM64_SYSREG_DBGBVR3_EL1, i64}, + {ARM64_SYSREG_DBGBVR4_EL1, i64}, + {ARM64_SYSREG_DBGBVR5_EL1, i64}, + {ARM64_SYSREG_DBGBVR6_EL1, i64}, + {ARM64_SYSREG_DBGBVR7_EL1, i64}, + {ARM64_SYSREG_DBGBVR8_EL1, i64}, + {ARM64_SYSREG_DBGBVR9_EL1, i64}, + {ARM64_SYSREG_DBGBVR10_EL1, i64}, + {ARM64_SYSREG_DBGBVR11_EL1, i64}, + {ARM64_SYSREG_DBGBVR12_EL1, i64}, + {ARM64_SYSREG_DBGBVR13_EL1, i64}, + {ARM64_SYSREG_DBGBVR14_EL1, i64}, + {ARM64_SYSREG_DBGBVR15_EL1, i64}, + {ARM64_SYSREG_DBGBCR0_EL1, i64}, + {ARM64_SYSREG_DBGBCR1_EL1, i64}, + {ARM64_SYSREG_DBGBCR2_EL1, i64}, + {ARM64_SYSREG_DBGBCR3_EL1, i64}, + {ARM64_SYSREG_DBGBCR4_EL1, i64}, + {ARM64_SYSREG_DBGBCR5_EL1, i64}, + {ARM64_SYSREG_DBGBCR6_EL1, i64}, + {ARM64_SYSREG_DBGBCR7_EL1, i64}, + {ARM64_SYSREG_DBGBCR8_EL1, i64}, + {ARM64_SYSREG_DBGBCR9_EL1, i64}, + {ARM64_SYSREG_DBGBCR10_EL1, i64}, + {ARM64_SYSREG_DBGBCR11_EL1, i64}, + {ARM64_SYSREG_DBGBCR12_EL1, i64}, + {ARM64_SYSREG_DBGBCR13_EL1, i64}, + {ARM64_SYSREG_DBGBCR14_EL1, i64}, + {ARM64_SYSREG_DBGBCR15_EL1, i64}, + {ARM64_SYSREG_DBGWVR0_EL1, i64}, + {ARM64_SYSREG_DBGWVR1_EL1, i64}, + {ARM64_SYSREG_DBGWVR2_EL1, i64}, + {ARM64_SYSREG_DBGWVR3_EL1, i64}, + {ARM64_SYSREG_DBGWVR4_EL1, i64}, + {ARM64_SYSREG_DBGWVR5_EL1, i64}, + {ARM64_SYSREG_DBGWVR6_EL1, i64}, + {ARM64_SYSREG_DBGWVR7_EL1, i64}, + {ARM64_SYSREG_DBGWVR8_EL1, i64}, + {ARM64_SYSREG_DBGWVR9_EL1, i64}, + {ARM64_SYSREG_DBGWVR10_EL1, i64}, + {ARM64_SYSREG_DBGWVR11_EL1, i64}, + {ARM64_SYSREG_DBGWVR12_EL1, i64}, + {ARM64_SYSREG_DBGWVR13_EL1, i64}, + {ARM64_SYSREG_DBGWVR14_EL1, i64}, + {ARM64_SYSREG_DBGWVR15_EL1, i64}, + {ARM64_SYSREG_DBGWCR0_EL1, i64}, + {ARM64_SYSREG_DBGWCR1_EL1, i64}, + {ARM64_SYSREG_DBGWCR2_EL1, i64}, + {ARM64_SYSREG_DBGWCR3_EL1, i64}, + {ARM64_SYSREG_DBGWCR4_EL1, i64}, + {ARM64_SYSREG_DBGWCR5_EL1, i64}, + {ARM64_SYSREG_DBGWCR6_EL1, i64}, + {ARM64_SYSREG_DBGWCR7_EL1, i64}, + {ARM64_SYSREG_DBGWCR8_EL1, i64}, + {ARM64_SYSREG_DBGWCR9_EL1, i64}, + {ARM64_SYSREG_DBGWCR10_EL1, i64}, + {ARM64_SYSREG_DBGWCR11_EL1, i64}, + {ARM64_SYSREG_DBGWCR12_EL1, i64}, + {ARM64_SYSREG_DBGWCR13_EL1, i64}, + {ARM64_SYSREG_DBGWCR14_EL1, i64}, + {ARM64_SYSREG_DBGWCR15_EL1, i64}, + {ARM64_SYSREG_TEEHBR32_EL1, i64}, + {ARM64_SYSREG_OSDLR_EL1, i64}, + {ARM64_SYSREG_DBGPRCR_EL1, i64}, + {ARM64_SYSREG_DBGCLAIMSET_EL1, i64}, + {ARM64_SYSREG_DBGCLAIMCLR_EL1, i64}, + {ARM64_SYSREG_CSSELR_EL1, i64}, + {ARM64_SYSREG_VPIDR_EL2, i64}, + {ARM64_SYSREG_VMPIDR_EL2, i64}, + {ARM64_SYSREG_CPACR_EL1, i64}, + {ARM64_SYSREG_SCTLR_EL1, i64}, + {ARM64_SYSREG_SCTLR_EL2, i64}, + {ARM64_SYSREG_SCTLR_EL3, i64}, + {ARM64_SYSREG_ACTLR_EL1, i64}, + {ARM64_SYSREG_ACTLR_EL2, i64}, + {ARM64_SYSREG_ACTLR_EL3, i64}, + {ARM64_SYSREG_HCR_EL2, i64}, + {ARM64_SYSREG_SCR_EL3, i64}, + {ARM64_SYSREG_MDCR_EL2, i64}, + {ARM64_SYSREG_SDER32_EL3, i64}, + {ARM64_SYSREG_CPTR_EL2, i64}, + {ARM64_SYSREG_CPTR_EL3, i64}, + {ARM64_SYSREG_HSTR_EL2, i64}, + {ARM64_SYSREG_HACR_EL2, i64}, + {ARM64_SYSREG_MDCR_EL3, i64}, + {ARM64_SYSREG_TTBR0_EL1, i64}, + {ARM64_SYSREG_TTBR0_EL2, i64}, + {ARM64_SYSREG_TTBR0_EL3, i64}, + {ARM64_SYSREG_TTBR1_EL1, i64}, + {ARM64_SYSREG_TCR_EL1, i64}, + {ARM64_SYSREG_TCR_EL2, i64}, + {ARM64_SYSREG_TCR_EL3, i64}, + {ARM64_SYSREG_VTTBR_EL2, i64}, + {ARM64_SYSREG_VTCR_EL2, i64}, + {ARM64_SYSREG_DACR32_EL2, i64}, + {ARM64_SYSREG_SPSR_EL1, i64}, + {ARM64_SYSREG_SPSR_EL2, i64}, + {ARM64_SYSREG_SPSR_EL3, i64}, + {ARM64_SYSREG_ELR_EL1, i64}, + {ARM64_SYSREG_ELR_EL2, i64}, + {ARM64_SYSREG_ELR_EL3, i64}, + {ARM64_SYSREG_SP_EL0, i64}, + {ARM64_SYSREG_SP_EL1, i64}, + {ARM64_SYSREG_SP_EL2, i64}, + {ARM64_SYSREG_SPSEL, i64}, + {ARM64_SYSREG_NZCV, i64}, + {ARM64_SYSREG_DAIF, i64}, + {ARM64_SYSREG_CURRENTEL, i64}, + {ARM64_SYSREG_SPSR_IRQ, i64}, + {ARM64_SYSREG_SPSR_ABT, i64}, + {ARM64_SYSREG_SPSR_UND, i64}, + {ARM64_SYSREG_SPSR_FIQ, i64}, + {ARM64_SYSREG_FPCR, i64}, + {ARM64_SYSREG_FPSR, i64}, + {ARM64_SYSREG_DSPSR_EL0, i64}, + {ARM64_SYSREG_DLR_EL0, i64}, + {ARM64_SYSREG_IFSR32_EL2, i64}, + {ARM64_SYSREG_AFSR0_EL1, i64}, + {ARM64_SYSREG_AFSR0_EL2, i64}, + {ARM64_SYSREG_AFSR0_EL3, i64}, + {ARM64_SYSREG_AFSR1_EL1, i64}, + {ARM64_SYSREG_AFSR1_EL2, i64}, + {ARM64_SYSREG_AFSR1_EL3, i64}, + {ARM64_SYSREG_ESR_EL1, i64}, + {ARM64_SYSREG_ESR_EL2, i64}, + {ARM64_SYSREG_ESR_EL3, i64}, + {ARM64_SYSREG_FPEXC32_EL2, i64}, + {ARM64_SYSREG_FAR_EL1, i64}, + {ARM64_SYSREG_FAR_EL2, i64}, + {ARM64_SYSREG_FAR_EL3, i64}, + {ARM64_SYSREG_HPFAR_EL2, i64}, + {ARM64_SYSREG_PAR_EL1, i64}, + {ARM64_SYSREG_PMCR_EL0, i64}, + {ARM64_SYSREG_PMCNTENSET_EL0, i64}, + {ARM64_SYSREG_PMCNTENCLR_EL0, i64}, + {ARM64_SYSREG_PMOVSCLR_EL0, i64}, + {ARM64_SYSREG_PMSELR_EL0, i64}, + {ARM64_SYSREG_PMCCNTR_EL0, i64}, + {ARM64_SYSREG_PMXEVTYPER_EL0, i64}, + {ARM64_SYSREG_PMXEVCNTR_EL0, i64}, + {ARM64_SYSREG_PMUSERENR_EL0, i64}, + {ARM64_SYSREG_PMINTENSET_EL1, i64}, + {ARM64_SYSREG_PMINTENCLR_EL1, i64}, + {ARM64_SYSREG_PMOVSSET_EL0, i64}, + {ARM64_SYSREG_MAIR_EL1, i64}, + {ARM64_SYSREG_MAIR_EL2, i64}, + {ARM64_SYSREG_MAIR_EL3, i64}, + {ARM64_SYSREG_AMAIR_EL1, i64}, + {ARM64_SYSREG_AMAIR_EL2, i64}, + {ARM64_SYSREG_AMAIR_EL3, i64}, + {ARM64_SYSREG_VBAR_EL1, i64}, + {ARM64_SYSREG_VBAR_EL2, i64}, + {ARM64_SYSREG_VBAR_EL3, i64}, + {ARM64_SYSREG_RMR_EL1, i64}, + {ARM64_SYSREG_RMR_EL2, i64}, + {ARM64_SYSREG_RMR_EL3, i64}, + {ARM64_SYSREG_CONTEXTIDR_EL1, i64}, + {ARM64_SYSREG_TPIDR_EL0, i64}, + {ARM64_SYSREG_TPIDR_EL2, i64}, + {ARM64_SYSREG_TPIDR_EL3, i64}, + {ARM64_SYSREG_TPIDRRO_EL0, i64}, + {ARM64_SYSREG_TPIDR_EL1, i64}, + {ARM64_SYSREG_CNTFRQ_EL0, i64}, + {ARM64_SYSREG_CNTVOFF_EL2, i64}, + {ARM64_SYSREG_CNTKCTL_EL1, i64}, + {ARM64_SYSREG_CNTHCTL_EL2, i64}, + {ARM64_SYSREG_CNTP_TVAL_EL0, i64}, + {ARM64_SYSREG_CNTHP_TVAL_EL2, i64}, + {ARM64_SYSREG_CNTPS_TVAL_EL1, i64}, + {ARM64_SYSREG_CNTP_CTL_EL0, i64}, + {ARM64_SYSREG_CNTHP_CTL_EL2, i64}, + {ARM64_SYSREG_CNTPS_CTL_EL1, i64}, + {ARM64_SYSREG_CNTP_CVAL_EL0, i64}, + {ARM64_SYSREG_CNTHP_CVAL_EL2, i64}, + {ARM64_SYSREG_CNTPS_CVAL_EL1, i64}, + {ARM64_SYSREG_CNTV_TVAL_EL0, i64}, + {ARM64_SYSREG_CNTV_CTL_EL0, i64}, + {ARM64_SYSREG_CNTV_CVAL_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR0_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR1_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR2_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR3_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR4_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR5_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR6_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR7_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR8_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR9_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR10_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR11_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR12_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR13_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR14_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR15_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR16_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR17_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR18_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR19_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR20_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR21_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR22_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR23_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR24_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR25_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR26_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR27_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR28_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR29_EL0, i64}, + {ARM64_SYSREG_PMEVCNTR30_EL0, i64}, + {ARM64_SYSREG_PMCCFILTR_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER0_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER1_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER2_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER3_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER4_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER5_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER6_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER7_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER8_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER9_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER10_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER11_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER12_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER13_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER14_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER15_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER16_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER17_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER18_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER19_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER20_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER21_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER22_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER23_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER24_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER25_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER26_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER27_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER28_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER29_EL0, i64}, + {ARM64_SYSREG_PMEVTYPER30_EL0, i64}, // Trace registers - {A64SysReg_TRCPRGCTLR, i64}, - {A64SysReg_TRCPROCSELR, i64}, - {A64SysReg_TRCCONFIGR, i64}, - {A64SysReg_TRCAUXCTLR, i64}, - {A64SysReg_TRCEVENTCTL0R, i64}, - {A64SysReg_TRCEVENTCTL1R, i64}, - {A64SysReg_TRCSTALLCTLR, i64}, - {A64SysReg_TRCTSCTLR, i64}, - {A64SysReg_TRCSYNCPR, i64}, - {A64SysReg_TRCCCCTLR, i64}, - {A64SysReg_TRCBBCTLR, i64}, - {A64SysReg_TRCTRACEIDR, i64}, - {A64SysReg_TRCQCTLR, i64}, - {A64SysReg_TRCVICTLR, i64}, - {A64SysReg_TRCVIIECTLR, i64}, - {A64SysReg_TRCVISSCTLR, i64}, - {A64SysReg_TRCVIPCSSCTLR, i64}, - {A64SysReg_TRCVDCTLR, i64}, - {A64SysReg_TRCVDSACCTLR, i64}, - {A64SysReg_TRCVDARCCTLR, i64}, - {A64SysReg_TRCSEQEVR0, i64}, - {A64SysReg_TRCSEQEVR1, i64}, - {A64SysReg_TRCSEQEVR2, i64}, - {A64SysReg_TRCSEQRSTEVR, i64}, - {A64SysReg_TRCSEQSTR, i64}, - {A64SysReg_TRCEXTINSELR, i64}, - {A64SysReg_TRCCNTRLDVR0, i64}, - {A64SysReg_TRCCNTRLDVR1, i64}, - {A64SysReg_TRCCNTRLDVR2, i64}, - {A64SysReg_TRCCNTRLDVR3, i64}, - {A64SysReg_TRCCNTCTLR0, i64}, - {A64SysReg_TRCCNTCTLR1, i64}, - {A64SysReg_TRCCNTCTLR2, i64}, - {A64SysReg_TRCCNTCTLR3, i64}, - {A64SysReg_TRCCNTVR0, i64}, - {A64SysReg_TRCCNTVR1, i64}, - {A64SysReg_TRCCNTVR2, i64}, - {A64SysReg_TRCCNTVR3, i64}, - {A64SysReg_TRCIMSPEC0, i64}, - {A64SysReg_TRCIMSPEC1, i64}, - {A64SysReg_TRCIMSPEC2, i64}, - {A64SysReg_TRCIMSPEC3, i64}, - {A64SysReg_TRCIMSPEC4, i64}, - {A64SysReg_TRCIMSPEC5, i64}, - {A64SysReg_TRCIMSPEC6, i64}, - {A64SysReg_TRCIMSPEC7, i64}, - {A64SysReg_TRCRSCTLR2, i64}, - {A64SysReg_TRCRSCTLR3, i64}, - {A64SysReg_TRCRSCTLR4, i64}, - {A64SysReg_TRCRSCTLR5, i64}, - {A64SysReg_TRCRSCTLR6, i64}, - {A64SysReg_TRCRSCTLR7, i64}, - {A64SysReg_TRCRSCTLR8, i64}, - {A64SysReg_TRCRSCTLR9, i64}, - {A64SysReg_TRCRSCTLR10, i64}, - {A64SysReg_TRCRSCTLR11, i64}, - {A64SysReg_TRCRSCTLR12, i64}, - {A64SysReg_TRCRSCTLR13, i64}, - {A64SysReg_TRCRSCTLR14, i64}, - {A64SysReg_TRCRSCTLR15, i64}, - {A64SysReg_TRCRSCTLR16, i64}, - {A64SysReg_TRCRSCTLR17, i64}, - {A64SysReg_TRCRSCTLR18, i64}, - {A64SysReg_TRCRSCTLR19, i64}, - {A64SysReg_TRCRSCTLR20, i64}, - {A64SysReg_TRCRSCTLR21, i64}, - {A64SysReg_TRCRSCTLR22, i64}, - {A64SysReg_TRCRSCTLR23, i64}, - {A64SysReg_TRCRSCTLR24, i64}, - {A64SysReg_TRCRSCTLR25, i64}, - {A64SysReg_TRCRSCTLR26, i64}, - {A64SysReg_TRCRSCTLR27, i64}, - {A64SysReg_TRCRSCTLR28, i64}, - {A64SysReg_TRCRSCTLR29, i64}, - {A64SysReg_TRCRSCTLR30, i64}, - {A64SysReg_TRCRSCTLR31, i64}, - {A64SysReg_TRCSSCCR0, i64}, - {A64SysReg_TRCSSCCR1, i64}, - {A64SysReg_TRCSSCCR2, i64}, - {A64SysReg_TRCSSCCR3, i64}, - {A64SysReg_TRCSSCCR4, i64}, - {A64SysReg_TRCSSCCR5, i64}, - {A64SysReg_TRCSSCCR6, i64}, - {A64SysReg_TRCSSCCR7, i64}, - {A64SysReg_TRCSSCSR0, i64}, - {A64SysReg_TRCSSCSR1, i64}, - {A64SysReg_TRCSSCSR2, i64}, - {A64SysReg_TRCSSCSR3, i64}, - {A64SysReg_TRCSSCSR4, i64}, - {A64SysReg_TRCSSCSR5, i64}, - {A64SysReg_TRCSSCSR6, i64}, - {A64SysReg_TRCSSCSR7, i64}, - {A64SysReg_TRCSSPCICR0, i64}, - {A64SysReg_TRCSSPCICR1, i64}, - {A64SysReg_TRCSSPCICR2, i64}, - {A64SysReg_TRCSSPCICR3, i64}, - {A64SysReg_TRCSSPCICR4, i64}, - {A64SysReg_TRCSSPCICR5, i64}, - {A64SysReg_TRCSSPCICR6, i64}, - {A64SysReg_TRCSSPCICR7, i64}, - {A64SysReg_TRCPDCR, i64}, - {A64SysReg_TRCACVR0, i64}, - {A64SysReg_TRCACVR1, i64}, - {A64SysReg_TRCACVR2, i64}, - {A64SysReg_TRCACVR3, i64}, - {A64SysReg_TRCACVR4, i64}, - {A64SysReg_TRCACVR5, i64}, - {A64SysReg_TRCACVR6, i64}, - {A64SysReg_TRCACVR7, i64}, - {A64SysReg_TRCACVR8, i64}, - {A64SysReg_TRCACVR9, i64}, - {A64SysReg_TRCACVR10, i64}, - {A64SysReg_TRCACVR11, i64}, - {A64SysReg_TRCACVR12, i64}, - {A64SysReg_TRCACVR13, i64}, - {A64SysReg_TRCACVR14, i64}, - {A64SysReg_TRCACVR15, i64}, - {A64SysReg_TRCACATR0, i64}, - {A64SysReg_TRCACATR1, i64}, - {A64SysReg_TRCACATR2, i64}, - {A64SysReg_TRCACATR3, i64}, - {A64SysReg_TRCACATR4, i64}, - {A64SysReg_TRCACATR5, i64}, - {A64SysReg_TRCACATR6, i64}, - {A64SysReg_TRCACATR7, i64}, - {A64SysReg_TRCACATR8, i64}, - {A64SysReg_TRCACATR9, i64}, - {A64SysReg_TRCACATR10, i64}, - {A64SysReg_TRCACATR11, i64}, - {A64SysReg_TRCACATR12, i64}, - {A64SysReg_TRCACATR13, i64}, - {A64SysReg_TRCACATR14, i64}, - {A64SysReg_TRCACATR15, i64}, - {A64SysReg_TRCDVCVR0, i64}, - {A64SysReg_TRCDVCVR1, i64}, - {A64SysReg_TRCDVCVR2, i64}, - {A64SysReg_TRCDVCVR3, i64}, - {A64SysReg_TRCDVCVR4, i64}, - {A64SysReg_TRCDVCVR5, i64}, - {A64SysReg_TRCDVCVR6, i64}, - {A64SysReg_TRCDVCVR7, i64}, - {A64SysReg_TRCDVCMR0, i64}, - {A64SysReg_TRCDVCMR1, i64}, - {A64SysReg_TRCDVCMR2, i64}, - {A64SysReg_TRCDVCMR3, i64}, - {A64SysReg_TRCDVCMR4, i64}, - {A64SysReg_TRCDVCMR5, i64}, - {A64SysReg_TRCDVCMR6, i64}, - {A64SysReg_TRCDVCMR7, i64}, - {A64SysReg_TRCCIDCVR0, i64}, - {A64SysReg_TRCCIDCVR1, i64}, - {A64SysReg_TRCCIDCVR2, i64}, - {A64SysReg_TRCCIDCVR3, i64}, - {A64SysReg_TRCCIDCVR4, i64}, - {A64SysReg_TRCCIDCVR5, i64}, - {A64SysReg_TRCCIDCVR6, i64}, - {A64SysReg_TRCCIDCVR7, i64}, - {A64SysReg_TRCVMIDCVR0, i64}, - {A64SysReg_TRCVMIDCVR1, i64}, - {A64SysReg_TRCVMIDCVR2, i64}, - {A64SysReg_TRCVMIDCVR3, i64}, - {A64SysReg_TRCVMIDCVR4, i64}, - {A64SysReg_TRCVMIDCVR5, i64}, - {A64SysReg_TRCVMIDCVR6, i64}, - {A64SysReg_TRCVMIDCVR7, i64}, - {A64SysReg_TRCCIDCCTLR0, i64}, - {A64SysReg_TRCCIDCCTLR1, i64}, - {A64SysReg_TRCVMIDCCTLR0, i64}, - {A64SysReg_TRCVMIDCCTLR1, i64}, - {A64SysReg_TRCITCTRL, i64}, - {A64SysReg_TRCCLAIMSET, i64}, - {A64SysReg_TRCCLAIMCLR, i64}, + {ARM64_SYSREG_TRCPRGCTLR, i64}, + {ARM64_SYSREG_TRCPROCSELR, i64}, + {ARM64_SYSREG_TRCCONFIGR, i64}, + {ARM64_SYSREG_TRCAUXCTLR, i64}, + {ARM64_SYSREG_TRCEVENTCTL0R, i64}, + {ARM64_SYSREG_TRCEVENTCTL1R, i64}, + {ARM64_SYSREG_TRCSTALLCTLR, i64}, + {ARM64_SYSREG_TRCTSCTLR, i64}, + {ARM64_SYSREG_TRCSYNCPR, i64}, + {ARM64_SYSREG_TRCCCCTLR, i64}, + {ARM64_SYSREG_TRCBBCTLR, i64}, + {ARM64_SYSREG_TRCTRACEIDR, i64}, + {ARM64_SYSREG_TRCQCTLR, i64}, + {ARM64_SYSREG_TRCVICTLR, i64}, + {ARM64_SYSREG_TRCVIIECTLR, i64}, + {ARM64_SYSREG_TRCVISSCTLR, i64}, + {ARM64_SYSREG_TRCVIPCSSCTLR, i64}, + {ARM64_SYSREG_TRCVDCTLR, i64}, + {ARM64_SYSREG_TRCVDSACCTLR, i64}, + {ARM64_SYSREG_TRCVDARCCTLR, i64}, + {ARM64_SYSREG_TRCSEQEVR0, i64}, + {ARM64_SYSREG_TRCSEQEVR1, i64}, + {ARM64_SYSREG_TRCSEQEVR2, i64}, + {ARM64_SYSREG_TRCSEQRSTEVR, i64}, + {ARM64_SYSREG_TRCSEQSTR, i64}, + {ARM64_SYSREG_TRCEXTINSELR, i64}, + {ARM64_SYSREG_TRCCNTRLDVR0, i64}, + {ARM64_SYSREG_TRCCNTRLDVR1, i64}, + {ARM64_SYSREG_TRCCNTRLDVR2, i64}, + {ARM64_SYSREG_TRCCNTRLDVR3, i64}, + {ARM64_SYSREG_TRCCNTCTLR0, i64}, + {ARM64_SYSREG_TRCCNTCTLR1, i64}, + {ARM64_SYSREG_TRCCNTCTLR2, i64}, + {ARM64_SYSREG_TRCCNTCTLR3, i64}, + {ARM64_SYSREG_TRCCNTVR0, i64}, + {ARM64_SYSREG_TRCCNTVR1, i64}, + {ARM64_SYSREG_TRCCNTVR2, i64}, + {ARM64_SYSREG_TRCCNTVR3, i64}, + {ARM64_SYSREG_TRCIMSPEC0, i64}, + {ARM64_SYSREG_TRCIMSPEC1, i64}, + {ARM64_SYSREG_TRCIMSPEC2, i64}, + {ARM64_SYSREG_TRCIMSPEC3, i64}, + {ARM64_SYSREG_TRCIMSPEC4, i64}, + {ARM64_SYSREG_TRCIMSPEC5, i64}, + {ARM64_SYSREG_TRCIMSPEC6, i64}, + {ARM64_SYSREG_TRCIMSPEC7, i64}, + {ARM64_SYSREG_TRCRSCTLR2, i64}, + {ARM64_SYSREG_TRCRSCTLR3, i64}, + {ARM64_SYSREG_TRCRSCTLR4, i64}, + {ARM64_SYSREG_TRCRSCTLR5, i64}, + {ARM64_SYSREG_TRCRSCTLR6, i64}, + {ARM64_SYSREG_TRCRSCTLR7, i64}, + {ARM64_SYSREG_TRCRSCTLR8, i64}, + {ARM64_SYSREG_TRCRSCTLR9, i64}, + {ARM64_SYSREG_TRCRSCTLR10, i64}, + {ARM64_SYSREG_TRCRSCTLR11, i64}, + {ARM64_SYSREG_TRCRSCTLR12, i64}, + {ARM64_SYSREG_TRCRSCTLR13, i64}, + {ARM64_SYSREG_TRCRSCTLR14, i64}, + {ARM64_SYSREG_TRCRSCTLR15, i64}, + {ARM64_SYSREG_TRCRSCTLR16, i64}, + {ARM64_SYSREG_TRCRSCTLR17, i64}, + {ARM64_SYSREG_TRCRSCTLR18, i64}, + {ARM64_SYSREG_TRCRSCTLR19, i64}, + {ARM64_SYSREG_TRCRSCTLR20, i64}, + {ARM64_SYSREG_TRCRSCTLR21, i64}, + {ARM64_SYSREG_TRCRSCTLR22, i64}, + {ARM64_SYSREG_TRCRSCTLR23, i64}, + {ARM64_SYSREG_TRCRSCTLR24, i64}, + {ARM64_SYSREG_TRCRSCTLR25, i64}, + {ARM64_SYSREG_TRCRSCTLR26, i64}, + {ARM64_SYSREG_TRCRSCTLR27, i64}, + {ARM64_SYSREG_TRCRSCTLR28, i64}, + {ARM64_SYSREG_TRCRSCTLR29, i64}, + {ARM64_SYSREG_TRCRSCTLR30, i64}, + {ARM64_SYSREG_TRCRSCTLR31, i64}, + {ARM64_SYSREG_TRCSSCCR0, i64}, + {ARM64_SYSREG_TRCSSCCR1, i64}, + {ARM64_SYSREG_TRCSSCCR2, i64}, + {ARM64_SYSREG_TRCSSCCR3, i64}, + {ARM64_SYSREG_TRCSSCCR4, i64}, + {ARM64_SYSREG_TRCSSCCR5, i64}, + {ARM64_SYSREG_TRCSSCCR6, i64}, + {ARM64_SYSREG_TRCSSCCR7, i64}, + {ARM64_SYSREG_TRCSSCSR0, i64}, + {ARM64_SYSREG_TRCSSCSR1, i64}, + {ARM64_SYSREG_TRCSSCSR2, i64}, + {ARM64_SYSREG_TRCSSCSR3, i64}, + {ARM64_SYSREG_TRCSSCSR4, i64}, + {ARM64_SYSREG_TRCSSCSR5, i64}, + {ARM64_SYSREG_TRCSSCSR6, i64}, + {ARM64_SYSREG_TRCSSCSR7, i64}, + {ARM64_SYSREG_TRCSSPCICR0, i64}, + {ARM64_SYSREG_TRCSSPCICR1, i64}, + {ARM64_SYSREG_TRCSSPCICR2, i64}, + {ARM64_SYSREG_TRCSSPCICR3, i64}, + {ARM64_SYSREG_TRCSSPCICR4, i64}, + {ARM64_SYSREG_TRCSSPCICR5, i64}, + {ARM64_SYSREG_TRCSSPCICR6, i64}, + {ARM64_SYSREG_TRCSSPCICR7, i64}, + {ARM64_SYSREG_TRCPDCR, i64}, + {ARM64_SYSREG_TRCACVR0, i64}, + {ARM64_SYSREG_TRCACVR1, i64}, + {ARM64_SYSREG_TRCACVR2, i64}, + {ARM64_SYSREG_TRCACVR3, i64}, + {ARM64_SYSREG_TRCACVR4, i64}, + {ARM64_SYSREG_TRCACVR5, i64}, + {ARM64_SYSREG_TRCACVR6, i64}, + {ARM64_SYSREG_TRCACVR7, i64}, + {ARM64_SYSREG_TRCACVR8, i64}, + {ARM64_SYSREG_TRCACVR9, i64}, + {ARM64_SYSREG_TRCACVR10, i64}, + {ARM64_SYSREG_TRCACVR11, i64}, + {ARM64_SYSREG_TRCACVR12, i64}, + {ARM64_SYSREG_TRCACVR13, i64}, + {ARM64_SYSREG_TRCACVR14, i64}, + {ARM64_SYSREG_TRCACVR15, i64}, + {ARM64_SYSREG_TRCACATR0, i64}, + {ARM64_SYSREG_TRCACATR1, i64}, + {ARM64_SYSREG_TRCACATR2, i64}, + {ARM64_SYSREG_TRCACATR3, i64}, + {ARM64_SYSREG_TRCACATR4, i64}, + {ARM64_SYSREG_TRCACATR5, i64}, + {ARM64_SYSREG_TRCACATR6, i64}, + {ARM64_SYSREG_TRCACATR7, i64}, + {ARM64_SYSREG_TRCACATR8, i64}, + {ARM64_SYSREG_TRCACATR9, i64}, + {ARM64_SYSREG_TRCACATR10, i64}, + {ARM64_SYSREG_TRCACATR11, i64}, + {ARM64_SYSREG_TRCACATR12, i64}, + {ARM64_SYSREG_TRCACATR13, i64}, + {ARM64_SYSREG_TRCACATR14, i64}, + {ARM64_SYSREG_TRCACATR15, i64}, + {ARM64_SYSREG_TRCDVCVR0, i64}, + {ARM64_SYSREG_TRCDVCVR1, i64}, + {ARM64_SYSREG_TRCDVCVR2, i64}, + {ARM64_SYSREG_TRCDVCVR3, i64}, + {ARM64_SYSREG_TRCDVCVR4, i64}, + {ARM64_SYSREG_TRCDVCVR5, i64}, + {ARM64_SYSREG_TRCDVCVR6, i64}, + {ARM64_SYSREG_TRCDVCVR7, i64}, + {ARM64_SYSREG_TRCDVCMR0, i64}, + {ARM64_SYSREG_TRCDVCMR1, i64}, + {ARM64_SYSREG_TRCDVCMR2, i64}, + {ARM64_SYSREG_TRCDVCMR3, i64}, + {ARM64_SYSREG_TRCDVCMR4, i64}, + {ARM64_SYSREG_TRCDVCMR5, i64}, + {ARM64_SYSREG_TRCDVCMR6, i64}, + {ARM64_SYSREG_TRCDVCMR7, i64}, + {ARM64_SYSREG_TRCCIDCVR0, i64}, + {ARM64_SYSREG_TRCCIDCVR1, i64}, + {ARM64_SYSREG_TRCCIDCVR2, i64}, + {ARM64_SYSREG_TRCCIDCVR3, i64}, + {ARM64_SYSREG_TRCCIDCVR4, i64}, + {ARM64_SYSREG_TRCCIDCVR5, i64}, + {ARM64_SYSREG_TRCCIDCVR6, i64}, + {ARM64_SYSREG_TRCCIDCVR7, i64}, + {ARM64_SYSREG_TRCVMIDCVR0, i64}, + {ARM64_SYSREG_TRCVMIDCVR1, i64}, + {ARM64_SYSREG_TRCVMIDCVR2, i64}, + {ARM64_SYSREG_TRCVMIDCVR3, i64}, + {ARM64_SYSREG_TRCVMIDCVR4, i64}, + {ARM64_SYSREG_TRCVMIDCVR5, i64}, + {ARM64_SYSREG_TRCVMIDCVR6, i64}, + {ARM64_SYSREG_TRCVMIDCVR7, i64}, + {ARM64_SYSREG_TRCCIDCCTLR0, i64}, + {ARM64_SYSREG_TRCCIDCCTLR1, i64}, + {ARM64_SYSREG_TRCVMIDCCTLR0, i64}, + {ARM64_SYSREG_TRCVMIDCCTLR1, i64}, + {ARM64_SYSREG_TRCITCTRL, i64}, + {ARM64_SYSREG_TRCCLAIMSET, i64}, + {ARM64_SYSREG_TRCCLAIMCLR, i64}, // GICv3 registers - {A64SysReg_ICC_BPR1_EL1, i64}, - {A64SysReg_ICC_BPR0_EL1, i64}, - {A64SysReg_ICC_PMR_EL1, i64}, - {A64SysReg_ICC_CTLR_EL1, i64}, - {A64SysReg_ICC_CTLR_EL3, i64}, - {A64SysReg_ICC_SRE_EL1, i64}, - {A64SysReg_ICC_SRE_EL2, i64}, - {A64SysReg_ICC_SRE_EL3, i64}, - {A64SysReg_ICC_IGRPEN0_EL1, i64}, - {A64SysReg_ICC_IGRPEN1_EL1, i64}, - {A64SysReg_ICC_IGRPEN1_EL3, i64}, - {A64SysReg_ICC_SEIEN_EL1, i64}, - {A64SysReg_ICC_AP0R0_EL1, i64}, - {A64SysReg_ICC_AP0R1_EL1, i64}, - {A64SysReg_ICC_AP0R2_EL1, i64}, - {A64SysReg_ICC_AP0R3_EL1, i64}, - {A64SysReg_ICC_AP1R0_EL1, i64}, - {A64SysReg_ICC_AP1R1_EL1, i64}, - {A64SysReg_ICC_AP1R2_EL1, i64}, - {A64SysReg_ICC_AP1R3_EL1, i64}, - {A64SysReg_ICH_AP0R0_EL2, i64}, - {A64SysReg_ICH_AP0R1_EL2, i64}, - {A64SysReg_ICH_AP0R2_EL2, i64}, - {A64SysReg_ICH_AP0R3_EL2, i64}, - {A64SysReg_ICH_AP1R0_EL2, i64}, - {A64SysReg_ICH_AP1R1_EL2, i64}, - {A64SysReg_ICH_AP1R2_EL2, i64}, - {A64SysReg_ICH_AP1R3_EL2, i64}, - {A64SysReg_ICH_HCR_EL2, i64}, - {A64SysReg_ICH_MISR_EL2, i64}, - {A64SysReg_ICH_VMCR_EL2, i64}, - {A64SysReg_ICH_VSEIR_EL2, i64}, - {A64SysReg_ICH_LR0_EL2, i64}, - {A64SysReg_ICH_LR1_EL2, i64}, - {A64SysReg_ICH_LR2_EL2, i64}, - {A64SysReg_ICH_LR3_EL2, i64}, - {A64SysReg_ICH_LR4_EL2, i64}, - {A64SysReg_ICH_LR5_EL2, i64}, - {A64SysReg_ICH_LR6_EL2, i64}, - {A64SysReg_ICH_LR7_EL2, i64}, - {A64SysReg_ICH_LR8_EL2, i64}, - {A64SysReg_ICH_LR9_EL2, i64}, - {A64SysReg_ICH_LR10_EL2, i64}, - {A64SysReg_ICH_LR11_EL2, i64}, - {A64SysReg_ICH_LR12_EL2, i64}, - {A64SysReg_ICH_LR13_EL2, i64}, - {A64SysReg_ICH_LR14_EL2, i64}, - {A64SysReg_ICH_LR15_EL2, i64}, + {ARM64_SYSREG_ICC_BPR1_EL1, i64}, + {ARM64_SYSREG_ICC_BPR0_EL1, i64}, + {ARM64_SYSREG_ICC_PMR_EL1, i64}, + {ARM64_SYSREG_ICC_CTLR_EL1, i64}, + {ARM64_SYSREG_ICC_CTLR_EL3, i64}, + {ARM64_SYSREG_ICC_SRE_EL1, i64}, + {ARM64_SYSREG_ICC_SRE_EL2, i64}, + {ARM64_SYSREG_ICC_SRE_EL3, i64}, + {ARM64_SYSREG_ICC_IGRPEN0_EL1, i64}, + {ARM64_SYSREG_ICC_IGRPEN1_EL1, i64}, + {ARM64_SYSREG_ICC_IGRPEN1_EL3, i64}, + {ARM64_SYSREG_ICC_SEIEN_EL1, i64}, + {ARM64_SYSREG_ICC_AP0R0_EL1, i64}, + {ARM64_SYSREG_ICC_AP0R1_EL1, i64}, + {ARM64_SYSREG_ICC_AP0R2_EL1, i64}, + {ARM64_SYSREG_ICC_AP0R3_EL1, i64}, + {ARM64_SYSREG_ICC_AP1R0_EL1, i64}, + {ARM64_SYSREG_ICC_AP1R1_EL1, i64}, + {ARM64_SYSREG_ICC_AP1R2_EL1, i64}, + {ARM64_SYSREG_ICC_AP1R3_EL1, i64}, + {ARM64_SYSREG_ICH_AP0R0_EL2, i64}, + {ARM64_SYSREG_ICH_AP0R1_EL2, i64}, + {ARM64_SYSREG_ICH_AP0R2_EL2, i64}, + {ARM64_SYSREG_ICH_AP0R3_EL2, i64}, + {ARM64_SYSREG_ICH_AP1R0_EL2, i64}, + {ARM64_SYSREG_ICH_AP1R1_EL2, i64}, + {ARM64_SYSREG_ICH_AP1R2_EL2, i64}, + {ARM64_SYSREG_ICH_AP1R3_EL2, i64}, + {ARM64_SYSREG_ICH_HCR_EL2, i64}, + {ARM64_SYSREG_ICH_MISR_EL2, i64}, + {ARM64_SYSREG_ICH_VMCR_EL2, i64}, + {ARM64_SYSREG_ICH_VSEIR_EL2, i64}, + {ARM64_SYSREG_ICH_LR0_EL2, i64}, + {ARM64_SYSREG_ICH_LR1_EL2, i64}, + {ARM64_SYSREG_ICH_LR2_EL2, i64}, + {ARM64_SYSREG_ICH_LR3_EL2, i64}, + {ARM64_SYSREG_ICH_LR4_EL2, i64}, + {ARM64_SYSREG_ICH_LR5_EL2, i64}, + {ARM64_SYSREG_ICH_LR6_EL2, i64}, + {ARM64_SYSREG_ICH_LR7_EL2, i64}, + {ARM64_SYSREG_ICH_LR8_EL2, i64}, + {ARM64_SYSREG_ICH_LR9_EL2, i64}, + {ARM64_SYSREG_ICH_LR10_EL2, i64}, + {ARM64_SYSREG_ICH_LR11_EL2, i64}, + {ARM64_SYSREG_ICH_LR12_EL2, i64}, + {ARM64_SYSREG_ICH_LR13_EL2, i64}, + {ARM64_SYSREG_ICH_LR14_EL2, i64}, + {ARM64_SYSREG_ICH_LR15_EL2, i64}, // enum A64SysRegROValues - {A64SysReg_MDCCSR_EL0, i64}, - {A64SysReg_DBGDTRRX_EL0, i64}, - {A64SysReg_MDRAR_EL1, i64}, - {A64SysReg_OSLSR_EL1, i64}, - {A64SysReg_DBGAUTHSTATUS_EL1, i64}, - {A64SysReg_PMCEID0_EL0, i64}, - {A64SysReg_PMCEID1_EL0, i64}, - {A64SysReg_MIDR_EL1, i64}, - {A64SysReg_CCSIDR_EL1, i64}, - {A64SysReg_CLIDR_EL1, i64}, - {A64SysReg_CTR_EL0, i64}, - {A64SysReg_MPIDR_EL1, i64}, - {A64SysReg_REVIDR_EL1, i64}, - {A64SysReg_AIDR_EL1, i64}, - {A64SysReg_DCZID_EL0, i64}, - {A64SysReg_ID_PFR0_EL1, i64}, - {A64SysReg_ID_PFR1_EL1, i64}, - {A64SysReg_ID_DFR0_EL1, i64}, - {A64SysReg_ID_AFR0_EL1, i64}, - {A64SysReg_ID_MMFR0_EL1, i64}, - {A64SysReg_ID_MMFR1_EL1, i64}, - {A64SysReg_ID_MMFR2_EL1, i64}, - {A64SysReg_ID_MMFR3_EL1, i64}, - {A64SysReg_ID_ISAR0_EL1, i64}, - {A64SysReg_ID_ISAR1_EL1, i64}, - {A64SysReg_ID_ISAR2_EL1, i64}, - {A64SysReg_ID_ISAR3_EL1, i64}, - {A64SysReg_ID_ISAR4_EL1, i64}, - {A64SysReg_ID_ISAR5_EL1, i64}, - {A64SysReg_ID_A64PFR0_EL1, i64}, - {A64SysReg_ID_A64PFR1_EL1, i64}, - {A64SysReg_ID_A64DFR0_EL1, i64}, - {A64SysReg_ID_A64DFR1_EL1, i64}, - {A64SysReg_ID_A64AFR0_EL1, i64}, - {A64SysReg_ID_A64AFR1_EL1, i64}, - {A64SysReg_ID_A64ISAR0_EL1, i64}, - {A64SysReg_ID_A64ISAR1_EL1, i64}, - {A64SysReg_ID_A64MMFR0_EL1, i64}, - {A64SysReg_ID_A64MMFR1_EL1, i64}, - {A64SysReg_MVFR0_EL1, i64}, - {A64SysReg_MVFR1_EL1, i64}, - {A64SysReg_MVFR2_EL1, i64}, - {A64SysReg_RVBAR_EL1, i64}, - {A64SysReg_RVBAR_EL2, i64}, - {A64SysReg_RVBAR_EL3, i64}, - {A64SysReg_ISR_EL1, i64}, - {A64SysReg_CNTPCT_EL0, i64}, - {A64SysReg_CNTVCT_EL0, i64}, + {ARM64_SYSREG_MDCCSR_EL0, i64}, + {ARM64_SYSREG_DBGDTRRX_EL0, i64}, + {ARM64_SYSREG_MDRAR_EL1, i64}, + {ARM64_SYSREG_OSLSR_EL1, i64}, + {ARM64_SYSREG_DBGAUTHSTATUS_EL1, i64}, + {ARM64_SYSREG_PMCEID0_EL0, i64}, + {ARM64_SYSREG_PMCEID1_EL0, i64}, + {ARM64_SYSREG_MIDR_EL1, i64}, + {ARM64_SYSREG_CCSIDR_EL1, i64}, + {ARM64_SYSREG_CLIDR_EL1, i64}, + {ARM64_SYSREG_CTR_EL0, i64}, + {ARM64_SYSREG_MPIDR_EL1, i64}, + {ARM64_SYSREG_REVIDR_EL1, i64}, + {ARM64_SYSREG_AIDR_EL1, i64}, + {ARM64_SYSREG_DCZID_EL0, i64}, + {ARM64_SYSREG_ID_PFR0_EL1, i64}, + {ARM64_SYSREG_ID_PFR1_EL1, i64}, + {ARM64_SYSREG_ID_DFR0_EL1, i64}, + {ARM64_SYSREG_ID_AFR0_EL1, i64}, + {ARM64_SYSREG_ID_MMFR0_EL1, i64}, + {ARM64_SYSREG_ID_MMFR1_EL1, i64}, + {ARM64_SYSREG_ID_MMFR2_EL1, i64}, + {ARM64_SYSREG_ID_MMFR3_EL1, i64}, + {ARM64_SYSREG_ID_ISAR0_EL1, i64}, + {ARM64_SYSREG_ID_ISAR1_EL1, i64}, + {ARM64_SYSREG_ID_ISAR2_EL1, i64}, + {ARM64_SYSREG_ID_ISAR3_EL1, i64}, + {ARM64_SYSREG_ID_ISAR4_EL1, i64}, + {ARM64_SYSREG_ID_ISAR5_EL1, i64}, + {ARM64_SYSREG_ID_AA64PFR0_EL1, i64}, + {ARM64_SYSREG_ID_AA64PFR1_EL1, i64}, + {ARM64_SYSREG_ID_AA64DFR0_EL1, i64}, + {ARM64_SYSREG_ID_AA64DFR1_EL1, i64}, + {ARM64_SYSREG_ID_AA64AFR0_EL1, i64}, + {ARM64_SYSREG_ID_AA64AFR1_EL1, i64}, + {ARM64_SYSREG_ID_AA64ISAR0_EL1, i64}, + {ARM64_SYSREG_ID_AA64ISAR1_EL1, i64}, + {ARM64_SYSREG_ID_AA64MMFR0_EL1, i64}, + {ARM64_SYSREG_ID_AA64MMFR1_EL1, i64}, + {ARM64_SYSREG_MVFR0_EL1, i64}, + {ARM64_SYSREG_MVFR1_EL1, i64}, + {ARM64_SYSREG_MVFR2_EL1, i64}, + {ARM64_SYSREG_RVBAR_EL1, i64}, + {ARM64_SYSREG_RVBAR_EL2, i64}, + {ARM64_SYSREG_RVBAR_EL3, i64}, + {ARM64_SYSREG_ISR_EL1, i64}, + {ARM64_SYSREG_CNTPCT_EL0, i64}, + {ARM64_SYSREG_CNTVCT_EL0, i64}, // Trace registers - {A64SysReg_TRCSTATR, i64}, - {A64SysReg_TRCIDR8, i64}, - {A64SysReg_TRCIDR9, i64}, - {A64SysReg_TRCIDR10, i64}, - {A64SysReg_TRCIDR11, i64}, - {A64SysReg_TRCIDR12, i64}, - {A64SysReg_TRCIDR13, i64}, - {A64SysReg_TRCIDR0, i64}, - {A64SysReg_TRCIDR1, i64}, - {A64SysReg_TRCIDR2, i64}, - {A64SysReg_TRCIDR3, i64}, - {A64SysReg_TRCIDR4, i64}, - {A64SysReg_TRCIDR5, i64}, - {A64SysReg_TRCIDR6, i64}, - {A64SysReg_TRCIDR7, i64}, - {A64SysReg_TRCOSLSR, i64}, - {A64SysReg_TRCPDSR, i64}, - {A64SysReg_TRCDEVAFF0, i64}, - {A64SysReg_TRCDEVAFF1, i64}, - {A64SysReg_TRCLSR, i64}, - {A64SysReg_TRCAUTHSTATUS, i64}, - {A64SysReg_TRCDEVARCH, i64}, - {A64SysReg_TRCDEVID, i64}, - {A64SysReg_TRCDEVTYPE, i64}, - {A64SysReg_TRCPIDR4, i64}, - {A64SysReg_TRCPIDR5, i64}, - {A64SysReg_TRCPIDR6, i64}, - {A64SysReg_TRCPIDR7, i64}, - {A64SysReg_TRCPIDR0, i64}, - {A64SysReg_TRCPIDR1, i64}, - {A64SysReg_TRCPIDR2, i64}, - {A64SysReg_TRCPIDR3, i64}, - {A64SysReg_TRCCIDR0, i64}, - {A64SysReg_TRCCIDR1, i64}, - {A64SysReg_TRCCIDR2, i64}, - {A64SysReg_TRCCIDR3, i64}, + {ARM64_SYSREG_TRCSTATR, i64}, + {ARM64_SYSREG_TRCIDR8, i64}, + {ARM64_SYSREG_TRCIDR9, i64}, + {ARM64_SYSREG_TRCIDR10, i64}, + {ARM64_SYSREG_TRCIDR11, i64}, + {ARM64_SYSREG_TRCIDR12, i64}, + {ARM64_SYSREG_TRCIDR13, i64}, + {ARM64_SYSREG_TRCIDR0, i64}, + {ARM64_SYSREG_TRCIDR1, i64}, + {ARM64_SYSREG_TRCIDR2, i64}, + {ARM64_SYSREG_TRCIDR3, i64}, + {ARM64_SYSREG_TRCIDR4, i64}, + {ARM64_SYSREG_TRCIDR5, i64}, + {ARM64_SYSREG_TRCIDR6, i64}, + {ARM64_SYSREG_TRCIDR7, i64}, + {ARM64_SYSREG_TRCOSLSR, i64}, + {ARM64_SYSREG_TRCPDSR, i64}, + {ARM64_SYSREG_TRCDEVAFF0, i64}, + {ARM64_SYSREG_TRCDEVAFF1, i64}, + {ARM64_SYSREG_TRCLSR, i64}, + {ARM64_SYSREG_TRCAUTHSTATUS, i64}, + {ARM64_SYSREG_TRCDEVARCH, i64}, + {ARM64_SYSREG_TRCDEVID, i64}, + {ARM64_SYSREG_TRCDEVTYPE, i64}, + {ARM64_SYSREG_TRCPIDR4, i64}, + {ARM64_SYSREG_TRCPIDR5, i64}, + {ARM64_SYSREG_TRCPIDR6, i64}, + {ARM64_SYSREG_TRCPIDR7, i64}, + {ARM64_SYSREG_TRCPIDR0, i64}, + {ARM64_SYSREG_TRCPIDR1, i64}, + {ARM64_SYSREG_TRCPIDR2, i64}, + {ARM64_SYSREG_TRCPIDR3, i64}, + {ARM64_SYSREG_TRCCIDR0, i64}, + {ARM64_SYSREG_TRCCIDR1, i64}, + {ARM64_SYSREG_TRCCIDR2, i64}, + {ARM64_SYSREG_TRCCIDR3, i64}, // GICv3 registers - {A64SysReg_ICC_IAR1_EL1, i64}, - {A64SysReg_ICC_IAR0_EL1, i64}, - {A64SysReg_ICC_HPPIR1_EL1, i64}, - {A64SysReg_ICC_HPPIR0_EL1, i64}, - {A64SysReg_ICC_RPR_EL1, i64}, - {A64SysReg_ICH_VTR_EL2, i64}, - {A64SysReg_ICH_EISR_EL2, i64}, - {A64SysReg_ICH_ELSR_EL2, i64}, + {ARM64_SYSREG_ICC_IAR1_EL1, i64}, + {ARM64_SYSREG_ICC_IAR0_EL1, i64}, + {ARM64_SYSREG_ICC_HPPIR1_EL1, i64}, + {ARM64_SYSREG_ICC_HPPIR0_EL1, i64}, + {ARM64_SYSREG_ICC_RPR_EL1, i64}, + {ARM64_SYSREG_ICH_VTR_EL2, i64}, + {ARM64_SYSREG_ICH_EISR_EL2, i64}, + {ARM64_SYSREG_ICH_ELRSR_EL2, i64}, {ARM64_PSTATE_SPSEL, i64}, {ARM64_PSTATE_DAIFSET, i64}, @@ -1622,10 +1621,12 @@ Capstone2LlvmIrTranslatorArm64_impl::_i2fm = {ARM64_INS_ABS, nullptr}, {ARM64_INS_ADC, &Capstone2LlvmIrTranslatorArm64_impl::translateAdc}, + {ARM64_INS_ADCS, &Capstone2LlvmIrTranslatorArm64_impl::translateAdc}, {ARM64_INS_ADDHN, nullptr}, {ARM64_INS_ADDHN2, nullptr}, {ARM64_INS_ADDP, nullptr}, {ARM64_INS_ADD, &Capstone2LlvmIrTranslatorArm64_impl::translateAdd}, + {ARM64_INS_ADDS, &Capstone2LlvmIrTranslatorArm64_impl::translateAdd}, {ARM64_INS_ADDV, nullptr}, {ARM64_INS_ADR, &Capstone2LlvmIrTranslatorArm64_impl::translateAdr}, {ARM64_INS_ADRP, &Capstone2LlvmIrTranslatorArm64_impl::translateAdr}, @@ -1634,10 +1635,12 @@ Capstone2LlvmIrTranslatorArm64_impl::_i2fm = {ARM64_INS_AESIMC, nullptr}, {ARM64_INS_AESMC, nullptr}, {ARM64_INS_AND, &Capstone2LlvmIrTranslatorArm64_impl::translateAnd}, + {ARM64_INS_ANDS, &Capstone2LlvmIrTranslatorArm64_impl::translateAnd}, {ARM64_INS_ASR, &Capstone2LlvmIrTranslatorArm64_impl::translateShifts}, {ARM64_INS_B, &Capstone2LlvmIrTranslatorArm64_impl::translateB}, {ARM64_INS_BFM, nullptr}, {ARM64_INS_BIC, &Capstone2LlvmIrTranslatorArm64_impl::translateAnd}, + {ARM64_INS_BICS, &Capstone2LlvmIrTranslatorArm64_impl::translateAnd}, {ARM64_INS_BIF, nullptr}, {ARM64_INS_BIT, nullptr}, {ARM64_INS_BL, &Capstone2LlvmIrTranslatorArm64_impl::translateBl}, @@ -1680,7 +1683,7 @@ Capstone2LlvmIrTranslatorArm64_impl::_i2fm = {ARM64_INS_DMB, nullptr}, {ARM64_INS_DRPS, nullptr}, {ARM64_INS_DSB, nullptr}, - {ARM64_INS_DUP, nullptr}, + {ARM64_INS_DUP, &Capstone2LlvmIrTranslatorArm64_impl::translateMov}, {ARM64_INS_EON, &Capstone2LlvmIrTranslatorArm64_impl::translateEor}, {ARM64_INS_EOR, &Capstone2LlvmIrTranslatorArm64_impl::translateEor}, {ARM64_INS_ERET, nullptr}, @@ -1856,6 +1859,7 @@ Capstone2LlvmIrTranslatorArm64_impl::_i2fm = {ARM64_INS_SADDW2, nullptr}, {ARM64_INS_SADDW, nullptr}, {ARM64_INS_SBC, &Capstone2LlvmIrTranslatorArm64_impl::translateSbc}, + {ARM64_INS_SBCS, &Capstone2LlvmIrTranslatorArm64_impl::translateSbc}, {ARM64_INS_SBFM, nullptr}, {ARM64_INS_SCVTF, &Capstone2LlvmIrTranslatorArm64_impl::translateFCvtf}, {ARM64_INS_SDIV, &Capstone2LlvmIrTranslatorArm64_impl::translateDiv}, @@ -1964,6 +1968,7 @@ Capstone2LlvmIrTranslatorArm64_impl::_i2fm = {ARM64_INS_SUBHN, nullptr}, {ARM64_INS_SUBHN2, nullptr}, {ARM64_INS_SUB, &Capstone2LlvmIrTranslatorArm64_impl::translateSub}, + {ARM64_INS_SUBS, &Capstone2LlvmIrTranslatorArm64_impl::translateSub}, {ARM64_INS_SUQADD, nullptr}, {ARM64_INS_SVC, nullptr}, {ARM64_INS_SYSL, nullptr}, diff --git a/src/capstone2llvmir/powerpc/powerpc.cpp b/src/capstone2llvmir/powerpc/powerpc.cpp index 40371df70..b0c13ee8a 100644 --- a/src/capstone2llvmir/powerpc/powerpc.cpp +++ b/src/capstone2llvmir/powerpc/powerpc.cpp @@ -308,60 +308,60 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::storeCrX( // PPC_REG_CRx_SO is a copy of XER, which we do not have. auto* so = zero; - uint32_t ltR = PPC_REG_CR0_LT; - uint32_t gtR = PPC_REG_CR0_GT; - uint32_t eqR = PPC_REG_CR0_EQ; - uint32_t soR = PPC_REG_CR0_SO; + uint32_t ltR = PPC_REG_CR0LT; + uint32_t gtR = PPC_REG_CR0GT; + uint32_t eqR = PPC_REG_CR0EQ; + uint32_t soR = PPC_REG_CR0UN; switch (crReg) { case PPC_REG_CR0: - ltR = PPC_REG_CR0_LT; - gtR = PPC_REG_CR0_GT; - eqR = PPC_REG_CR0_EQ; - soR = PPC_REG_CR0_SO; + ltR = PPC_REG_CR0LT; + gtR = PPC_REG_CR0GT; + eqR = PPC_REG_CR0EQ; + soR = PPC_REG_CR0UN; break; case PPC_REG_CR1: - ltR = PPC_REG_CR1_LT; - gtR = PPC_REG_CR1_GT; - eqR = PPC_REG_CR1_EQ; - soR = PPC_REG_CR1_SO; + ltR = PPC_REG_CR1LT; + gtR = PPC_REG_CR1GT; + eqR = PPC_REG_CR1EQ; + soR = PPC_REG_CR1UN; break; case PPC_REG_CR2: - ltR = PPC_REG_CR2_LT; - gtR = PPC_REG_CR2_GT; - eqR = PPC_REG_CR2_EQ; - soR = PPC_REG_CR2_SO; + ltR = PPC_REG_CR2LT; + gtR = PPC_REG_CR2GT; + eqR = PPC_REG_CR2EQ; + soR = PPC_REG_CR2UN; break; case PPC_REG_CR3: - ltR = PPC_REG_CR3_LT; - gtR = PPC_REG_CR3_GT; - eqR = PPC_REG_CR3_EQ; - soR = PPC_REG_CR3_SO; + ltR = PPC_REG_CR3LT; + gtR = PPC_REG_CR3GT; + eqR = PPC_REG_CR3EQ; + soR = PPC_REG_CR3UN; break; case PPC_REG_CR4: - ltR = PPC_REG_CR4_LT; - gtR = PPC_REG_CR4_GT; - eqR = PPC_REG_CR4_EQ; - soR = PPC_REG_CR4_SO; + ltR = PPC_REG_CR4LT; + gtR = PPC_REG_CR4GT; + eqR = PPC_REG_CR4EQ; + soR = PPC_REG_CR4UN; break; case PPC_REG_CR5: - ltR = PPC_REG_CR5_LT; - gtR = PPC_REG_CR5_GT; - eqR = PPC_REG_CR5_EQ; - soR = PPC_REG_CR5_SO; + ltR = PPC_REG_CR5LT; + gtR = PPC_REG_CR5GT; + eqR = PPC_REG_CR5EQ; + soR = PPC_REG_CR5UN; break; case PPC_REG_CR6: - ltR = PPC_REG_CR6_LT; - gtR = PPC_REG_CR6_GT; - eqR = PPC_REG_CR6_EQ; - soR = PPC_REG_CR6_SO; + ltR = PPC_REG_CR6LT; + gtR = PPC_REG_CR6GT; + eqR = PPC_REG_CR6EQ; + soR = PPC_REG_CR6UN; break; case PPC_REG_CR7: - ltR = PPC_REG_CR7_LT; - gtR = PPC_REG_CR7_GT; - eqR = PPC_REG_CR7_EQ; - soR = PPC_REG_CR7_SO; + ltR = PPC_REG_CR7LT; + gtR = PPC_REG_CR7GT; + eqR = PPC_REG_CR7EQ; + soR = PPC_REG_CR7UN; break; default: throw GenericError("Unhandled CR register."); @@ -377,60 +377,60 @@ std::tuple Capstone2Llvm llvm::IRBuilder<>& irb, uint32_t crReg) { - uint32_t ltR = PPC_REG_CR0_LT; - uint32_t gtR = PPC_REG_CR0_GT; - uint32_t eqR = PPC_REG_CR0_EQ; - uint32_t soR = PPC_REG_CR0_SO; + uint32_t ltR = PPC_REG_CR0LT; + uint32_t gtR = PPC_REG_CR0GT; + uint32_t eqR = PPC_REG_CR0EQ; + uint32_t soR = PPC_REG_CR0UN; switch (crReg) { case PPC_REG_CR0: - ltR = PPC_REG_CR0_LT; - gtR = PPC_REG_CR0_GT; - eqR = PPC_REG_CR0_EQ; - soR = PPC_REG_CR0_SO; + ltR = PPC_REG_CR0LT; + gtR = PPC_REG_CR0GT; + eqR = PPC_REG_CR0EQ; + soR = PPC_REG_CR0UN; break; case PPC_REG_CR1: - ltR = PPC_REG_CR1_LT; - gtR = PPC_REG_CR1_GT; - eqR = PPC_REG_CR1_EQ; - soR = PPC_REG_CR1_SO; + ltR = PPC_REG_CR1LT; + gtR = PPC_REG_CR1GT; + eqR = PPC_REG_CR1EQ; + soR = PPC_REG_CR1UN; break; case PPC_REG_CR2: - ltR = PPC_REG_CR2_LT; - gtR = PPC_REG_CR2_GT; - eqR = PPC_REG_CR2_EQ; - soR = PPC_REG_CR2_SO; + ltR = PPC_REG_CR2LT; + gtR = PPC_REG_CR2GT; + eqR = PPC_REG_CR2EQ; + soR = PPC_REG_CR2UN; break; case PPC_REG_CR3: - ltR = PPC_REG_CR3_LT; - gtR = PPC_REG_CR3_GT; - eqR = PPC_REG_CR3_EQ; - soR = PPC_REG_CR3_SO; + ltR = PPC_REG_CR3LT; + gtR = PPC_REG_CR3GT; + eqR = PPC_REG_CR3EQ; + soR = PPC_REG_CR3UN; break; case PPC_REG_CR4: - ltR = PPC_REG_CR4_LT; - gtR = PPC_REG_CR4_GT; - eqR = PPC_REG_CR4_EQ; - soR = PPC_REG_CR4_SO; + ltR = PPC_REG_CR4LT; + gtR = PPC_REG_CR4GT; + eqR = PPC_REG_CR4EQ; + soR = PPC_REG_CR4UN; break; case PPC_REG_CR5: - ltR = PPC_REG_CR5_LT; - gtR = PPC_REG_CR5_GT; - eqR = PPC_REG_CR5_EQ; - soR = PPC_REG_CR5_SO; + ltR = PPC_REG_CR5LT; + gtR = PPC_REG_CR5GT; + eqR = PPC_REG_CR5EQ; + soR = PPC_REG_CR5UN; break; case PPC_REG_CR6: - ltR = PPC_REG_CR6_LT; - gtR = PPC_REG_CR6_GT; - eqR = PPC_REG_CR6_EQ; - soR = PPC_REG_CR6_SO; + ltR = PPC_REG_CR6LT; + gtR = PPC_REG_CR6GT; + eqR = PPC_REG_CR6EQ; + soR = PPC_REG_CR6UN; break; case PPC_REG_CR7: - ltR = PPC_REG_CR7_LT; - gtR = PPC_REG_CR7_GT; - eqR = PPC_REG_CR7_EQ; - soR = PPC_REG_CR7_SO; + ltR = PPC_REG_CR7LT; + gtR = PPC_REG_CR7GT; + eqR = PPC_REG_CR7EQ; + soR = PPC_REG_CR7UN; break; default: throw GenericError("Unhandled CR register."); @@ -449,60 +449,65 @@ llvm::Value* Capstone2LlvmIrTranslatorPowerpc_impl::loadCrX( uint32_t crReg, ppc_cr_types type) { - uint32_t ltR = PPC_REG_CR0_LT; - uint32_t gtR = PPC_REG_CR0_GT; - uint32_t eqR = PPC_REG_CR0_EQ; - uint32_t soR = PPC_REG_CR0_SO; + uint32_t ltR = PPC_REG_CR0LT; + uint32_t gtR = PPC_REG_CR0GT; + uint32_t eqR = PPC_REG_CR0EQ; + uint32_t soR = PPC_REG_CR0UN; + + if (isCrRegister(crReg) && isCrBitRegister(crReg)) + { + return loadRegister(crReg, irb); + } switch (crReg) { case PPC_REG_CR0: - ltR = PPC_REG_CR0_LT; - gtR = PPC_REG_CR0_GT; - eqR = PPC_REG_CR0_EQ; - soR = PPC_REG_CR0_SO; + ltR = PPC_REG_CR0LT; + gtR = PPC_REG_CR0GT; + eqR = PPC_REG_CR0EQ; + soR = PPC_REG_CR0UN; break; case PPC_REG_CR1: - ltR = PPC_REG_CR1_LT; - gtR = PPC_REG_CR1_GT; - eqR = PPC_REG_CR1_EQ; - soR = PPC_REG_CR1_SO; + ltR = PPC_REG_CR1LT; + gtR = PPC_REG_CR1GT; + eqR = PPC_REG_CR1EQ; + soR = PPC_REG_CR1UN; break; case PPC_REG_CR2: - ltR = PPC_REG_CR2_LT; - gtR = PPC_REG_CR2_GT; - eqR = PPC_REG_CR2_EQ; - soR = PPC_REG_CR2_SO; + ltR = PPC_REG_CR2LT; + gtR = PPC_REG_CR2GT; + eqR = PPC_REG_CR2EQ; + soR = PPC_REG_CR2UN; break; case PPC_REG_CR3: - ltR = PPC_REG_CR3_LT; - gtR = PPC_REG_CR3_GT; - eqR = PPC_REG_CR3_EQ; - soR = PPC_REG_CR3_SO; + ltR = PPC_REG_CR3LT; + gtR = PPC_REG_CR3GT; + eqR = PPC_REG_CR3EQ; + soR = PPC_REG_CR3UN; break; case PPC_REG_CR4: - ltR = PPC_REG_CR4_LT; - gtR = PPC_REG_CR4_GT; - eqR = PPC_REG_CR4_EQ; - soR = PPC_REG_CR4_SO; + ltR = PPC_REG_CR4LT; + gtR = PPC_REG_CR4GT; + eqR = PPC_REG_CR4EQ; + soR = PPC_REG_CR4UN; break; case PPC_REG_CR5: - ltR = PPC_REG_CR5_LT; - gtR = PPC_REG_CR5_GT; - eqR = PPC_REG_CR5_EQ; - soR = PPC_REG_CR5_SO; + ltR = PPC_REG_CR5LT; + gtR = PPC_REG_CR5GT; + eqR = PPC_REG_CR5EQ; + soR = PPC_REG_CR5UN; break; case PPC_REG_CR6: - ltR = PPC_REG_CR6_LT; - gtR = PPC_REG_CR6_GT; - eqR = PPC_REG_CR6_EQ; - soR = PPC_REG_CR6_SO; + ltR = PPC_REG_CR6LT; + gtR = PPC_REG_CR6GT; + eqR = PPC_REG_CR6EQ; + soR = PPC_REG_CR6UN; break; case PPC_REG_CR7: - ltR = PPC_REG_CR7_LT; - gtR = PPC_REG_CR7_GT; - eqR = PPC_REG_CR7_EQ; - soR = PPC_REG_CR7_SO; + ltR = PPC_REG_CR7LT; + gtR = PPC_REG_CR7GT; + eqR = PPC_REG_CR7EQ; + soR = PPC_REG_CR7UN; break; default: throw GenericError("Unhandled CR register."); @@ -536,16 +541,16 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::storeCr0( llvm::Value* zero = llvm::ConstantInt::get(val->getType(), 0); auto* ltZero = irb.CreateICmpSLT(val, zero); - storeRegister(PPC_REG_CR0_LT, ltZero, irb); + storeRegister(PPC_REG_CR0LT, ltZero, irb); auto* gtZero = irb.CreateICmpSGT(val, zero); - storeRegister(PPC_REG_CR0_GT, gtZero, irb); + storeRegister(PPC_REG_CR0GT, gtZero, irb); auto* eqZero = irb.CreateICmpEQ(val, zero); - storeRegister(PPC_REG_CR0_EQ, eqZero, irb); + storeRegister(PPC_REG_CR0EQ, eqZero, irb); - // PPC_REG_CR0_SO is a copy of XER, which we do not have. - storeRegister(PPC_REG_CR0_SO, zero, irb); + // PPC_REG_CR0UN is a copy of XER, which we do not have. + storeRegister(PPC_REG_CR0UN, zero, irb); } bool Capstone2LlvmIrTranslatorPowerpc_impl::isGeneralPurposeRegister(uint32_t r) @@ -559,24 +564,25 @@ uint32_t Capstone2LlvmIrTranslatorPowerpc_impl::getGeneralPurposeRegisterIndex(u } /** - * 0 -> PPC_REG_CR0_LT - * 1 -> PPC_REG_CR0_GT - * 2 -> PPC_REG_CR0_EQ - * 3 -> PPC_REG_CR0_SO - * 4 -> PPC_REG_CR1_LT - * 5 -> PPC_REG_CR2_GT + * 0 -> PPC_REG_CR0LT + * 1 -> PPC_REG_CR0GT + * 2 -> PPC_REG_CR0EQ + * 3 -> PPC_REG_CR0UN + * 4 -> PPC_REG_CR1LT + * 5 -> PPC_REG_CR2GT * ... - * 30 -> PPC_REG_CR7_EQ - * 31 -> PPC_REG_CR7_SO + * 30 -> PPC_REG_CR7EQ + * 31 -> PPC_REG_CR7UN */ uint32_t Capstone2LlvmIrTranslatorPowerpc_impl::crBitIndexToCrRegister(uint32_t idx) { - return PPC_REG_CR0_LT + idx; + return PPC_REG_CR0LT + idx; } bool Capstone2LlvmIrTranslatorPowerpc_impl::isCrRegister(uint32_t r) { - return PPC_REG_CR0 <= r && r <= PPC_REG_CR7; + return (PPC_REG_CR0 <= r && r <= PPC_REG_CR7) + || isCrBitRegister(r); } bool Capstone2LlvmIrTranslatorPowerpc_impl::isCrRegister(cs_ppc_op& op) @@ -584,6 +590,10 @@ bool Capstone2LlvmIrTranslatorPowerpc_impl::isCrRegister(cs_ppc_op& op) return op.type == PPC_OP_REG && isCrRegister(op.reg); } +bool Capstone2LlvmIrTranslatorPowerpc_impl::isCrBitRegister(uint32_t r) +{ + return PPC_REG_CR0EQ <= r && r <= PPC_REG_CR5UN; +} bool Capstone2LlvmIrTranslatorPowerpc_impl::isOperandRegister(cs_ppc_op& op) { return op.type == PPC_OP_REG; @@ -744,17 +754,25 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::translateAndis(cs_insn* i, cs_ppc* p /** * PPC_INS_CLRLWI - clrlwi rA, RS, n (n < 32) = rlwinm rA, rS, 0, n, 31 + * PPC_INS_RLWINM - in capstone, rlwinm is equivalent to clrlwi */ void Capstone2LlvmIrTranslatorPowerpc_impl::translateClrlwi(cs_insn* i, cs_ppc* pi, llvm::IRBuilder<>& irb) { - EXPECT_IS_BINARY_OR_TERNARY(i, pi, irb); - - std::tie(op1, op2) = loadOpBinaryOrTernaryOp1Op2(pi, irb, eOpConv::ZEXT_TRUNC_OR_BITCAST); - op2 = irb.CreateAnd(op2, llvm::ConstantInt::get(op2->getType(), 31)); - op1 = irb.CreateShl(op1, op2); - op1 = irb.CreateLShr(op1, op2); - storeOp(pi->operands[0], op1, irb); - storeCr0(irb, pi, op1); + std::set opCountTemp = {3, 5}; + EXPECT_IS_SET(i, pi, irb, opCountTemp) + if(pi->op_count == 3) + { + std::tie(op1, op2) = loadOpBinaryOrTernaryOp1Op2(pi, irb, eOpConv::ZEXT_TRUNC_OR_BITCAST); + op2 = irb.CreateAnd(op2, llvm::ConstantInt::get(op2->getType(), 31)); + op1 = irb.CreateShl(op1, op2); + op1 = irb.CreateLShr(op1, op2); + storeOp(pi->operands[0], op1, irb); + storeCr0(irb, pi, op1); + } + else + { + translateRotateComplex5op(i, pi, irb); + } } /** @@ -767,6 +785,8 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::translateClrlwi(cs_insn* i, cs_ppc* * PPC_INS_CMPW, PPC_INS_CMPWI * PPC_INS_CMPLD, PPC_INS_CMPLDI * PPC_INS_CMPLW, PPC_INS_CMPLWI + * + * PPC_INS_CMP, PPC_INS_CMPL */ void Capstone2LlvmIrTranslatorPowerpc_impl::translateCmp(cs_insn* i, cs_ppc* pi, llvm::IRBuilder<>& irb) { @@ -792,6 +812,7 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::translateCmp(cs_insn* i, cs_ppc* pi, } if (i->id == PPC_INS_CMPW + || i->id == PPC_INS_CMPL || i->id == PPC_INS_CMPWI || i->id == PPC_INS_CMPLW || i->id == PPC_INS_CMPLWI) @@ -802,6 +823,7 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::translateCmp(cs_insn* i, cs_ppc* pi, bool signedCmp = true; if (i->id == PPC_INS_CMPLD + || i->id == PPC_INS_CMPL || i->id == PPC_INS_CMPLDI || i->id == PPC_INS_CMPLW || i->id == PPC_INS_CMPLWI) @@ -1176,10 +1198,10 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::translateMtcrf(cs_insn* i, cs_ppc* p auto* c = irb.CreateCall(fnc, llvm::ArrayRef{op0, op1}); - storeRegister(PPC_REG_CR0_LT, irb.CreateExtractValue(c, {0}), irb); - storeRegister(PPC_REG_CR0_GT, irb.CreateExtractValue(c, {1}), irb); - storeRegister(PPC_REG_CR0_EQ, irb.CreateExtractValue(c, {2}), irb); - storeRegister(PPC_REG_CR0_SO, irb.CreateExtractValue(c, {3}), irb); + storeRegister(PPC_REG_CR0LT, irb.CreateExtractValue(c, {0}), irb); + storeRegister(PPC_REG_CR0GT, irb.CreateExtractValue(c, {1}), irb); + storeRegister(PPC_REG_CR0EQ, irb.CreateExtractValue(c, {2}), irb); + storeRegister(PPC_REG_CR0UN, irb.CreateExtractValue(c, {3}), irb); storeRegister(PPC_REG_CR1, irb.CreateExtractValue(c, {4}), irb); storeRegister(PPC_REG_CR2, irb.CreateExtractValue(c, {5}), irb); @@ -1200,45 +1222,45 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::translateMtcr(cs_insn* i, cs_ppc* pi op0 = loadOpUnary(pi, irb); op0 = irb.CreateZExtOrTrunc(op0, irb.getInt32Ty()); - storeRegister(PPC_REG_CR0_LT, irb.CreateAnd(op0, irb.getInt32(1 << 0)), irb); - storeRegister(PPC_REG_CR0_GT, irb.CreateAnd(op0, irb.getInt32(1 << 1)), irb); - storeRegister(PPC_REG_CR0_EQ, irb.CreateAnd(op0, irb.getInt32(1 << 2)), irb); - storeRegister(PPC_REG_CR0_SO, irb.CreateAnd(op0, irb.getInt32(1 << 3)), irb); + storeRegister(PPC_REG_CR0LT, irb.CreateAnd(op0, irb.getInt32(1 << 0)), irb); + storeRegister(PPC_REG_CR0GT, irb.CreateAnd(op0, irb.getInt32(1 << 1)), irb); + storeRegister(PPC_REG_CR0EQ, irb.CreateAnd(op0, irb.getInt32(1 << 2)), irb); + storeRegister(PPC_REG_CR0UN, irb.CreateAnd(op0, irb.getInt32(1 << 3)), irb); - storeRegister(PPC_REG_CR1_LT, irb.CreateAnd(op0, irb.getInt32(1 << 4)), irb); - storeRegister(PPC_REG_CR1_GT, irb.CreateAnd(op0, irb.getInt32(1 << 5)), irb); - storeRegister(PPC_REG_CR1_EQ, irb.CreateAnd(op0, irb.getInt32(1 << 6)), irb); - storeRegister(PPC_REG_CR1_SO, irb.CreateAnd(op0, irb.getInt32(1 << 7)), irb); + storeRegister(PPC_REG_CR1LT, irb.CreateAnd(op0, irb.getInt32(1 << 4)), irb); + storeRegister(PPC_REG_CR1GT, irb.CreateAnd(op0, irb.getInt32(1 << 5)), irb); + storeRegister(PPC_REG_CR1EQ, irb.CreateAnd(op0, irb.getInt32(1 << 6)), irb); + storeRegister(PPC_REG_CR1UN, irb.CreateAnd(op0, irb.getInt32(1 << 7)), irb); - storeRegister(PPC_REG_CR2_LT, irb.CreateAnd(op0, irb.getInt32(1 << 8)), irb); - storeRegister(PPC_REG_CR2_GT, irb.CreateAnd(op0, irb.getInt32(1 << 9)), irb); - storeRegister(PPC_REG_CR2_EQ, irb.CreateAnd(op0, irb.getInt32(1 << 10)), irb); - storeRegister(PPC_REG_CR2_SO, irb.CreateAnd(op0, irb.getInt32(1 << 11)), irb); + storeRegister(PPC_REG_CR2LT, irb.CreateAnd(op0, irb.getInt32(1 << 8)), irb); + storeRegister(PPC_REG_CR2GT, irb.CreateAnd(op0, irb.getInt32(1 << 9)), irb); + storeRegister(PPC_REG_CR2EQ, irb.CreateAnd(op0, irb.getInt32(1 << 10)), irb); + storeRegister(PPC_REG_CR2UN, irb.CreateAnd(op0, irb.getInt32(1 << 11)), irb); - storeRegister(PPC_REG_CR3_LT, irb.CreateAnd(op0, irb.getInt32(1 << 12)), irb); - storeRegister(PPC_REG_CR3_GT, irb.CreateAnd(op0, irb.getInt32(1 << 13)), irb); - storeRegister(PPC_REG_CR3_EQ, irb.CreateAnd(op0, irb.getInt32(1 << 14)), irb); - storeRegister(PPC_REG_CR3_SO, irb.CreateAnd(op0, irb.getInt32(1 << 15)), irb); + storeRegister(PPC_REG_CR3LT, irb.CreateAnd(op0, irb.getInt32(1 << 12)), irb); + storeRegister(PPC_REG_CR3GT, irb.CreateAnd(op0, irb.getInt32(1 << 13)), irb); + storeRegister(PPC_REG_CR3EQ, irb.CreateAnd(op0, irb.getInt32(1 << 14)), irb); + storeRegister(PPC_REG_CR3UN, irb.CreateAnd(op0, irb.getInt32(1 << 15)), irb); - storeRegister(PPC_REG_CR4_LT, irb.CreateAnd(op0, irb.getInt32(1 << 16)), irb); - storeRegister(PPC_REG_CR4_GT, irb.CreateAnd(op0, irb.getInt32(1 << 17)), irb); - storeRegister(PPC_REG_CR4_EQ, irb.CreateAnd(op0, irb.getInt32(1 << 18)), irb); - storeRegister(PPC_REG_CR4_SO, irb.CreateAnd(op0, irb.getInt32(1 << 19)), irb); + storeRegister(PPC_REG_CR4LT, irb.CreateAnd(op0, irb.getInt32(1 << 16)), irb); + storeRegister(PPC_REG_CR4GT, irb.CreateAnd(op0, irb.getInt32(1 << 17)), irb); + storeRegister(PPC_REG_CR4EQ, irb.CreateAnd(op0, irb.getInt32(1 << 18)), irb); + storeRegister(PPC_REG_CR4UN, irb.CreateAnd(op0, irb.getInt32(1 << 19)), irb); - storeRegister(PPC_REG_CR5_LT, irb.CreateAnd(op0, irb.getInt32(1 << 20)), irb); - storeRegister(PPC_REG_CR5_GT, irb.CreateAnd(op0, irb.getInt32(1 << 21)), irb); - storeRegister(PPC_REG_CR5_EQ, irb.CreateAnd(op0, irb.getInt32(1 << 22)), irb); - storeRegister(PPC_REG_CR5_SO, irb.CreateAnd(op0, irb.getInt32(1 << 23)), irb); + storeRegister(PPC_REG_CR5LT, irb.CreateAnd(op0, irb.getInt32(1 << 20)), irb); + storeRegister(PPC_REG_CR5GT, irb.CreateAnd(op0, irb.getInt32(1 << 21)), irb); + storeRegister(PPC_REG_CR5EQ, irb.CreateAnd(op0, irb.getInt32(1 << 22)), irb); + storeRegister(PPC_REG_CR5UN, irb.CreateAnd(op0, irb.getInt32(1 << 23)), irb); - storeRegister(PPC_REG_CR6_LT, irb.CreateAnd(op0, irb.getInt32(1 << 24)), irb); - storeRegister(PPC_REG_CR6_GT, irb.CreateAnd(op0, irb.getInt32(1 << 25)), irb); - storeRegister(PPC_REG_CR6_EQ, irb.CreateAnd(op0, irb.getInt32(1 << 26)), irb); - storeRegister(PPC_REG_CR6_SO, irb.CreateAnd(op0, irb.getInt32(1 << 27)), irb); + storeRegister(PPC_REG_CR6LT, irb.CreateAnd(op0, irb.getInt32(1 << 24)), irb); + storeRegister(PPC_REG_CR6GT, irb.CreateAnd(op0, irb.getInt32(1 << 25)), irb); + storeRegister(PPC_REG_CR6EQ, irb.CreateAnd(op0, irb.getInt32(1 << 26)), irb); + storeRegister(PPC_REG_CR6UN, irb.CreateAnd(op0, irb.getInt32(1 << 27)), irb); - storeRegister(PPC_REG_CR7_LT, irb.CreateAnd(op0, irb.getInt32(1 << 28)), irb); - storeRegister(PPC_REG_CR7_GT, irb.CreateAnd(op0, irb.getInt32(1 << 29)), irb); - storeRegister(PPC_REG_CR7_EQ, irb.CreateAnd(op0, irb.getInt32(1 << 30)), irb); - storeRegister(PPC_REG_CR7_SO, irb.CreateAnd(op0, irb.getInt32(1 << 31)), irb); + storeRegister(PPC_REG_CR7LT, irb.CreateAnd(op0, irb.getInt32(1 << 28)), irb); + storeRegister(PPC_REG_CR7GT, irb.CreateAnd(op0, irb.getInt32(1 << 29)), irb); + storeRegister(PPC_REG_CR7EQ, irb.CreateAnd(op0, irb.getInt32(1 << 30)), irb); + storeRegister(PPC_REG_CR7UN, irb.CreateAnd(op0, irb.getInt32(1 << 31)), irb); } /** @@ -1286,10 +1308,10 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::translateCrModifTernary(cs_insn* i, auto* c = irb.CreateCall(fnc, llvm::ArrayRef{op0, op1, op2}); - storeRegister(PPC_REG_CR0_LT, irb.CreateExtractValue(c, {0}), irb); - storeRegister(PPC_REG_CR0_GT, irb.CreateExtractValue(c, {1}), irb); - storeRegister(PPC_REG_CR0_EQ, irb.CreateExtractValue(c, {2}), irb); - storeRegister(PPC_REG_CR0_SO, irb.CreateExtractValue(c, {3}), irb); + storeRegister(PPC_REG_CR0LT, irb.CreateExtractValue(c, {0}), irb); + storeRegister(PPC_REG_CR0GT, irb.CreateExtractValue(c, {1}), irb); + storeRegister(PPC_REG_CR0EQ, irb.CreateExtractValue(c, {2}), irb); + storeRegister(PPC_REG_CR0UN, irb.CreateExtractValue(c, {3}), irb); storeRegister(PPC_REG_CR1, irb.CreateExtractValue(c, {4}), irb); storeRegister(PPC_REG_CR2, irb.CreateExtractValue(c, {5}), irb); @@ -1311,14 +1333,14 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::translateCrNotMove(cs_insn* i, cs_pp uint32_t crReg0 = 0; uint32_t crReg1 = 0; if (pi->operands[0].type == PPC_OP_REG - && isGeneralPurposeRegister(pi->operands[0].reg) + && isCrRegister(pi->operands[0].reg) && pi->operands[1].type == PPC_OP_REG - && isGeneralPurposeRegister(pi->operands[1].reg)) + && isCrRegister(pi->operands[1].reg)) { auto r0 = pi->operands[0].reg; - crReg0 = crBitIndexToCrRegister(getGeneralPurposeRegisterIndex(r0)); + crReg0 = r0; auto r1 = pi->operands[1].reg; - crReg1 = crBitIndexToCrRegister(getGeneralPurposeRegisterIndex(r1)); + crReg1 = r1; } else { @@ -1351,10 +1373,10 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::translateCrSetClr(cs_insn* i, cs_ppc uint32_t crReg = 0; if (pi->operands[0].type == PPC_OP_REG - && isGeneralPurposeRegister(pi->operands[0].reg)) + && isCrRegister(pi->operands[0].reg)) { auto r = pi->operands[0].reg; - crReg = crBitIndexToCrRegister(getGeneralPurposeRegisterIndex(r)); + crReg = r; } else { @@ -1390,10 +1412,10 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::translateMcrf(cs_insn* i, cs_ppc* pi if (pi->operands[1].type == PPC_OP_REG && pi->operands[1].reg == PPC_REG_CR0) { - auto* lt = loadRegister(PPC_REG_CR0_LT, irb); - auto* gt = loadRegister(PPC_REG_CR0_GT, irb); - auto* eq = loadRegister(PPC_REG_CR0_EQ, irb); - auto* so = loadRegister(PPC_REG_CR0_SO, irb); + auto* lt = loadRegister(PPC_REG_CR0LT, irb); + auto* gt = loadRegister(PPC_REG_CR0GT, irb); + auto* eq = loadRegister(PPC_REG_CR0EQ, irb); + auto* so = loadRegister(PPC_REG_CR0UN, irb); llvm::Function* fnc = getPseudoAsmFunction( i, @@ -1423,10 +1445,10 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::translateMcrf(cs_insn* i, cs_ppc* pi auto* c = irb.CreateCall(fnc, llvm::ArrayRef{op1}); - storeRegister(PPC_REG_CR0_LT, irb.CreateExtractValue(c, {0}), irb); - storeRegister(PPC_REG_CR0_GT, irb.CreateExtractValue(c, {1}), irb); - storeRegister(PPC_REG_CR0_EQ, irb.CreateExtractValue(c, {2}), irb); - storeRegister(PPC_REG_CR0_SO, irb.CreateExtractValue(c, {3}), irb); + storeRegister(PPC_REG_CR0LT, irb.CreateExtractValue(c, {0}), irb); + storeRegister(PPC_REG_CR0GT, irb.CreateExtractValue(c, {1}), irb); + storeRegister(PPC_REG_CR0EQ, irb.CreateExtractValue(c, {2}), irb); + storeRegister(PPC_REG_CR0UN, irb.CreateExtractValue(c, {3}), irb); } else { @@ -2043,6 +2065,17 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::translateB(cs_insn* i, cs_ppc* pi, l PPC_INS_BDZL, PPC_INS_BDZLA, PPC_INS_BDZLRL, PPC_INS_BDZTL, PPC_INS_BDZTLA, PPC_INS_BDZTLRL, PPC_INS_BDZFL, PPC_INS_BDZFLA, PPC_INS_BDZFLRL, + + PPC_INS_BLTL, PPC_INS_BLTLA, PPC_INS_BLTLRL, PPC_INS_BLTCTRL, + PPC_INS_BLEL, PPC_INS_BLELA, PPC_INS_BLELRL, PPC_INS_BLECTRL, + PPC_INS_BEQL, PPC_INS_BEQLA, PPC_INS_BEQLRL, PPC_INS_BEQCTRL, + PPC_INS_BGEL, PPC_INS_BGELA, PPC_INS_BGELRL, PPC_INS_BGECTRL, + PPC_INS_BGTL, PPC_INS_BGTLA, PPC_INS_BGTLRL, PPC_INS_BGTCTRL, + PPC_INS_BNLL, PPC_INS_BNLLA, PPC_INS_BNLLRL, PPC_INS_BNLCTRL, + PPC_INS_BNEL, PPC_INS_BNELA, PPC_INS_BNELRL, PPC_INS_BNECTRL, + PPC_INS_BNGL, PPC_INS_BNGLA, PPC_INS_BNGLRL, PPC_INS_BNGCTRL, + PPC_INS_BSOL, PPC_INS_BSOLA, PPC_INS_BSOLRL, PPC_INS_BSOCTRL, + PPC_INS_BNSL, PPC_INS_BNSLA, PPC_INS_BNSLRL, PPC_INS_BNSCTRL, }; bool link = linkIds.count(i->id); @@ -2062,6 +2095,17 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::translateB(cs_insn* i, cs_ppc* pi, l PPC_INS_BDZLR, PPC_INS_BDZLRL, PPC_INS_BDZTLR, PPC_INS_BDZTLRL, PPC_INS_BDZFLR, PPC_INS_BDZFLRL, + + PPC_INS_BLTLR, PPC_INS_BLTLRL, + PPC_INS_BLELR, PPC_INS_BLELRL, + PPC_INS_BEQLR, PPC_INS_BEQLRL, + PPC_INS_BGELR, PPC_INS_BGELRL, + PPC_INS_BGTLR, PPC_INS_BGTLRL, + PPC_INS_BNLLR, PPC_INS_BNLLRL, + PPC_INS_BNELR, PPC_INS_BNELRL, + PPC_INS_BNGLR, PPC_INS_BNGLRL, + PPC_INS_BSOLR, PPC_INS_BSOLRL, + PPC_INS_BNSLR, PPC_INS_BNSLRL, }; bool toLR = toLRIds.count(i->id); @@ -2072,7 +2116,18 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::translateB(cs_insn* i, cs_ppc* pi, l PPC_INS_BCCTR, PPC_INS_BCCTRL, PPC_INS_BCTR, PPC_INS_BCTRL, PPC_INS_BTCTR, PPC_INS_BTCTRL, - PPC_INS_BFCTR, PPC_INS_BFCTRL + PPC_INS_BFCTR, PPC_INS_BFCTRL, + + PPC_INS_BLTCTR, PPC_INS_BLTCTRL, + PPC_INS_BLECTR, PPC_INS_BLECTRL, + PPC_INS_BEQCTR, PPC_INS_BEQCTRL, + PPC_INS_BGECTR, PPC_INS_BGECTRL, + PPC_INS_BGTCTR, PPC_INS_BGTCTRL, + PPC_INS_BNLCTR, PPC_INS_BNLCTRL, + PPC_INS_BNECTR, PPC_INS_BNECTRL, + PPC_INS_BNGCTR, PPC_INS_BNGCTRL, + PPC_INS_BSOCTR, PPC_INS_BSOCTRL, + PPC_INS_BNSCTR, PPC_INS_BNSCTRL, }; bool toCTR = toCTRIds.count(i->id); diff --git a/src/capstone2llvmir/powerpc/powerpc_impl.h b/src/capstone2llvmir/powerpc/powerpc_impl.h index 73670ce32..5fb1ea1a5 100644 --- a/src/capstone2llvmir/powerpc/powerpc_impl.h +++ b/src/capstone2llvmir/powerpc/powerpc_impl.h @@ -98,7 +98,7 @@ class Capstone2LlvmIrTranslatorPowerpc_impl : uint32_t crBitIndexToCrRegister(uint32_t idx); bool isCrRegister(uint32_t r); bool isCrRegister(cs_ppc_op& op); - + bool isCrBitRegister(uint32_t r); virtual bool isOperandRegister(cs_ppc_op& op) override; // //============================================================================== diff --git a/src/capstone2llvmir/powerpc/powerpc_init.cpp b/src/capstone2llvmir/powerpc/powerpc_init.cpp index 94bed77df..a33b289f2 100644 --- a/src/capstone2llvmir/powerpc/powerpc_init.cpp +++ b/src/capstone2llvmir/powerpc/powerpc_init.cpp @@ -19,45 +19,45 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::initializeArchSpecific() { std::map r2n = { - {PPC_REG_CR0_LT, "cr0_lt"}, - {PPC_REG_CR0_GT, "cr0_gt"}, - {PPC_REG_CR0_EQ, "cr0_eq"}, - {PPC_REG_CR0_SO, "cr0_so"}, - - {PPC_REG_CR1_LT, "cr1_lt"}, - {PPC_REG_CR1_GT, "cr1_gt"}, - {PPC_REG_CR1_EQ, "cr1_eq"}, - {PPC_REG_CR1_SO, "cr1_so"}, - - {PPC_REG_CR2_LT, "cr2_lt"}, - {PPC_REG_CR2_GT, "cr2_gt"}, - {PPC_REG_CR2_EQ, "cr2_eq"}, - {PPC_REG_CR2_SO, "cr2_so"}, - - {PPC_REG_CR3_LT, "cr3_lt"}, - {PPC_REG_CR3_GT, "cr3_gt"}, - {PPC_REG_CR3_EQ, "cr3_eq"}, - {PPC_REG_CR3_SO, "cr3_so"}, - - {PPC_REG_CR4_LT, "cr4_lt"}, - {PPC_REG_CR4_GT, "cr4_gt"}, - {PPC_REG_CR4_EQ, "cr4_eq"}, - {PPC_REG_CR4_SO, "cr4_so"}, - - {PPC_REG_CR5_LT, "cr5_lt"}, - {PPC_REG_CR5_GT, "cr5_gt"}, - {PPC_REG_CR5_EQ, "cr5_eq"}, - {PPC_REG_CR5_SO, "cr5_so"}, - - {PPC_REG_CR6_LT, "cr6_lt"}, - {PPC_REG_CR6_GT, "cr6_gt"}, - {PPC_REG_CR6_EQ, "cr6_eq"}, - {PPC_REG_CR6_SO, "cr6_so"}, - - {PPC_REG_CR7_LT, "cr7_lt"}, - {PPC_REG_CR7_GT, "cr7_gt"}, - {PPC_REG_CR7_EQ, "cr7_eq"}, - {PPC_REG_CR7_SO, "cr7_so"}, + {PPC_REG_CR0LT, "cr0_lt"}, + {PPC_REG_CR0GT, "cr0_gt"}, + {PPC_REG_CR0EQ, "cr0_eq"}, + {PPC_REG_CR0UN, "cr0_so"}, + + {PPC_REG_CR1LT, "cr1_lt"}, + {PPC_REG_CR1GT, "cr1_gt"}, + {PPC_REG_CR1EQ, "cr1_eq"}, + {PPC_REG_CR1UN, "cr1_so"}, + + {PPC_REG_CR2LT, "cr2_lt"}, + {PPC_REG_CR2GT, "cr2_gt"}, + {PPC_REG_CR2EQ, "cr2_eq"}, + {PPC_REG_CR2UN, "cr2_so"}, + + {PPC_REG_CR3LT, "cr3_lt"}, + {PPC_REG_CR3GT, "cr3_gt"}, + {PPC_REG_CR3EQ, "cr3_eq"}, + {PPC_REG_CR3UN, "cr3_so"}, + + {PPC_REG_CR4LT, "cr4_lt"}, + {PPC_REG_CR4GT, "cr4_gt"}, + {PPC_REG_CR4EQ, "cr4_eq"}, + {PPC_REG_CR4UN, "cr4_so"}, + + {PPC_REG_CR5LT, "cr5_lt"}, + {PPC_REG_CR5GT, "cr5_gt"}, + {PPC_REG_CR5EQ, "cr5_eq"}, + {PPC_REG_CR5UN, "cr5_so"}, + + {PPC_REG_CR6LT, "cr6_lt"}, + {PPC_REG_CR6GT, "cr6_gt"}, + {PPC_REG_CR6EQ, "cr6_eq"}, + {PPC_REG_CR6UN, "cr6_so"}, + + {PPC_REG_CR7LT, "cr7_lt"}, + {PPC_REG_CR7GT, "cr7_gt"}, + {PPC_REG_CR7EQ, "cr7_eq"}, + {PPC_REG_CR7UN, "cr7_so"}, }; _reg2name = std::move(r2n); @@ -87,45 +87,45 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::initializeRegTypeMap() // Condition registers. // 4-bit x 8 = 32-bit CR register. // - {PPC_REG_CR0_LT, i1}, - {PPC_REG_CR0_GT, i1}, - {PPC_REG_CR0_EQ, i1}, - {PPC_REG_CR0_SO, i1}, - - {PPC_REG_CR1_LT, i1}, - {PPC_REG_CR1_GT, i1}, - {PPC_REG_CR1_EQ, i1}, - {PPC_REG_CR1_SO, i1}, - - {PPC_REG_CR2_LT, i1}, - {PPC_REG_CR2_GT, i1}, - {PPC_REG_CR2_EQ, i1}, - {PPC_REG_CR2_SO, i1}, - - {PPC_REG_CR3_LT, i1}, - {PPC_REG_CR3_GT, i1}, - {PPC_REG_CR3_EQ, i1}, - {PPC_REG_CR3_SO, i1}, - - {PPC_REG_CR4_LT, i1}, - {PPC_REG_CR4_GT, i1}, - {PPC_REG_CR4_EQ, i1}, - {PPC_REG_CR4_SO, i1}, - - {PPC_REG_CR5_LT, i1}, - {PPC_REG_CR5_GT, i1}, - {PPC_REG_CR5_EQ, i1}, - {PPC_REG_CR5_SO, i1}, - - {PPC_REG_CR6_LT, i1}, - {PPC_REG_CR6_GT, i1}, - {PPC_REG_CR6_EQ, i1}, - {PPC_REG_CR6_SO, i1}, - - {PPC_REG_CR7_LT, i1}, - {PPC_REG_CR7_GT, i1}, - {PPC_REG_CR7_EQ, i1}, - {PPC_REG_CR7_SO, i1}, + {PPC_REG_CR0LT, i1}, + {PPC_REG_CR0GT, i1}, + {PPC_REG_CR0EQ, i1}, + {PPC_REG_CR0UN, i1}, + + {PPC_REG_CR1LT, i1}, + {PPC_REG_CR1GT, i1}, + {PPC_REG_CR1EQ, i1}, + {PPC_REG_CR1UN, i1}, + + {PPC_REG_CR2LT, i1}, + {PPC_REG_CR2GT, i1}, + {PPC_REG_CR2EQ, i1}, + {PPC_REG_CR2UN, i1}, + + {PPC_REG_CR3LT, i1}, + {PPC_REG_CR3GT, i1}, + {PPC_REG_CR3EQ, i1}, + {PPC_REG_CR3UN, i1}, + + {PPC_REG_CR4LT, i1}, + {PPC_REG_CR4GT, i1}, + {PPC_REG_CR4EQ, i1}, + {PPC_REG_CR4UN, i1}, + + {PPC_REG_CR5LT, i1}, + {PPC_REG_CR5GT, i1}, + {PPC_REG_CR5EQ, i1}, + {PPC_REG_CR5UN, i1}, + + {PPC_REG_CR6LT, i1}, + {PPC_REG_CR6GT, i1}, + {PPC_REG_CR6EQ, i1}, + {PPC_REG_CR6UN, i1}, + + {PPC_REG_CR7LT, i1}, + {PPC_REG_CR7GT, i1}, + {PPC_REG_CR7EQ, i1}, + {PPC_REG_CR7UN, i1}, // We also define these registers, because they can unexpectedly be // operands of some instructions, and if we do not have it, operand @@ -367,12 +367,13 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::initializeRegTypeMap() {PPC_REG_Q30, i256}, {PPC_REG_Q31, i256}, - // extra registers for PPCMapping.c + //FP ounding Mode {PPC_REG_RM, defTy}, {PPC_REG_CTR8, defTy}, {PPC_REG_LR8, defTy}, - {PPC_REG_CR1EQ, defTy}, - {PPC_REG_X2, defTy}, + {PPC_REG_XER, defTy}, + //The reprsentation of r0 when treated as the constant 0. + {PPC_REG_ZERO, defTy}, }; _reg2type = std::move(r2t); @@ -488,6 +489,96 @@ void Capstone2LlvmIrTranslatorPowerpc_impl::initializePseudoCallInstructionIDs() PPC_INS_BDZFL, PPC_INS_BDZFLA, PPC_INS_BDZFLRL, + + PPC_INS_BLT, + PPC_INS_BLTA, + PPC_INS_BLTCTR, + PPC_INS_BLTCTRL, + PPC_INS_BLTL, + PPC_INS_BLTLA, + PPC_INS_BLTLR, + PPC_INS_BLTLRL, + + PPC_INS_BLE, + PPC_INS_BLEA, + PPC_INS_BLECTR, + PPC_INS_BLECTRL, + PPC_INS_BLEL, + PPC_INS_BLELA, + PPC_INS_BLELR, + PPC_INS_BLELRL, + + PPC_INS_BEQ, + PPC_INS_BEQA, + PPC_INS_BEQCTR, + PPC_INS_BEQCTRL, + PPC_INS_BEQL, + PPC_INS_BEQLA, + PPC_INS_BEQLR, + PPC_INS_BEQLRL, + + PPC_INS_BGE, + PPC_INS_BGEA, + PPC_INS_BGECTR, + PPC_INS_BGECTRL, + PPC_INS_BGEL, + PPC_INS_BGELA, + PPC_INS_BGELR, + PPC_INS_BGELRL, + + PPC_INS_BGT, + PPC_INS_BGTA, + PPC_INS_BGTCTR, + PPC_INS_BGTCTRL, + PPC_INS_BGTL, + PPC_INS_BGTLA, + PPC_INS_BGTLR, + PPC_INS_BGTLRL, + + PPC_INS_BNL, + PPC_INS_BNLA, + PPC_INS_BNLCTR, + PPC_INS_BNLCTRL, + PPC_INS_BNLL, + PPC_INS_BNLLA, + PPC_INS_BNLLR, + PPC_INS_BNLLRL, + + PPC_INS_BNE, + PPC_INS_BNEA, + PPC_INS_BNECTR, + PPC_INS_BNECTRL, + PPC_INS_BNEL, + PPC_INS_BNELA, + PPC_INS_BNELR, + PPC_INS_BNELRL, + + PPC_INS_BNG, + PPC_INS_BNGA, + PPC_INS_BNGCTR, + PPC_INS_BNGCTRL, + PPC_INS_BNGL, + PPC_INS_BNGLA, + PPC_INS_BNGLR, + PPC_INS_BNGLRL, + + PPC_INS_BSO, + PPC_INS_BSOA, + PPC_INS_BSOCTR, + PPC_INS_BSOCTRL, + PPC_INS_BSOL, + PPC_INS_BSOLA, + PPC_INS_BSOLR, + PPC_INS_BSOLRL, + + PPC_INS_BNS, + PPC_INS_BNSA, + PPC_INS_BNSCTR, + PPC_INS_BNSCTRL, + PPC_INS_BNSL, + PPC_INS_BNSLA, + PPC_INS_BNSLR, + PPC_INS_BNSLRL, }; } @@ -521,9 +612,11 @@ Capstone2LlvmIrTranslatorPowerpc_impl::_i2fm = {PPC_INS_ANDI, &Capstone2LlvmIrTranslatorPowerpc_impl::translateAnd}, {PPC_INS_ATTN, nullptr}, {PPC_INS_BRINC, nullptr}, + {PPC_INS_CMP, &Capstone2LlvmIrTranslatorPowerpc_impl::translateCmp}, {PPC_INS_CMPB, nullptr}, {PPC_INS_CMPD, &Capstone2LlvmIrTranslatorPowerpc_impl::translateCmp}, {PPC_INS_CMPDI, &Capstone2LlvmIrTranslatorPowerpc_impl::translateCmp}, + {PPC_INS_CMPL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateCmp}, {PPC_INS_CMPLD, &Capstone2LlvmIrTranslatorPowerpc_impl::translateCmp}, {PPC_INS_CMPLDI, &Capstone2LlvmIrTranslatorPowerpc_impl::translateCmp}, {PPC_INS_CMPLW, &Capstone2LlvmIrTranslatorPowerpc_impl::translateCmp}, @@ -1022,7 +1115,6 @@ Capstone2LlvmIrTranslatorPowerpc_impl::_i2fm = {PPC_INS_RLDICR, nullptr}, {PPC_INS_RLDIMI, nullptr}, {PPC_INS_RLWIMI, &Capstone2LlvmIrTranslatorPowerpc_impl::translateRotateComplex5op}, - {PPC_INS_RLWINM, &Capstone2LlvmIrTranslatorPowerpc_impl::translateRotateComplex5op}, {PPC_INS_RLWNM, &Capstone2LlvmIrTranslatorPowerpc_impl::translateRotateComplex5op}, {PPC_INS_SC, nullptr}, {PPC_INS_SLBIA, nullptr}, @@ -1440,7 +1532,7 @@ Capstone2LlvmIrTranslatorPowerpc_impl::_i2fm = {PPC_INS_MFSRR2, nullptr}, {PPC_INS_MFSRR3, nullptr}, {PPC_INS_MFCFAR, nullptr}, - {PPC_INS_MFAMR, nullptr}, + {PPC_INS_MFAMR, &Capstone2LlvmIrTranslatorPowerpc_impl::translatePseudoAsmOp0FncOp1}, {PPC_INS_MFPID, nullptr}, {PPC_INS_MFTBLO, nullptr}, {PPC_INS_MFTBHI, nullptr}, @@ -1648,8 +1740,118 @@ Capstone2LlvmIrTranslatorPowerpc_impl::_i2fm = {PPC_INS_BDZFL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, {PPC_INS_BDZFLA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, {PPC_INS_BDZFLRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + + //Branch mnemonics incorporating conditions + //Branch if less than + {PPC_INS_BLT, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BLTA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BLTCTR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BLTCTRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BLTL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BLTLA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BLTLR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BLTLRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + //Branch if less than or equal + {PPC_INS_BLE, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BLEA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BLECTR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BLECTRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BLEL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BLELA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BLELR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BLELRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + //Branch if equal + {PPC_INS_BEQ, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BEQA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BEQCTR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BEQCTRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BEQL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BEQLA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BEQLR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BEQLRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + //Branch if greater than or equal + {PPC_INS_BGE, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BGEA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BGECTR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BGECTRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BGEL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BGELA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BGELR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BGELRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + //Branch if greater than + {PPC_INS_BGT, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BGTA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BGTCTR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BGTCTRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BGTL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BGTLA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BGTLR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BGTLRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + //Branch if not less than + {PPC_INS_BNL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNLA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNLCTR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNLCTRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNLL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNLLA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNLLR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNLLRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + //Branch if not equal + {PPC_INS_BNE, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNEA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNECTR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNECTRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNEL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNELA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNELR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNELRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + //Branch if not greater than + {PPC_INS_BNG, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNGA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNGCTR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNGCTRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNGL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNGLA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNGLR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNGLRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + //Branch if summary overflow + {PPC_INS_BSO, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BSOA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BSOCTR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BSOCTRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BSOL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BSOLA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BSOLR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BSOLRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + //Branch if not summary overflow + {PPC_INS_BNS, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNSA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNSCTR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNSCTRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNSL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNSLA, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNSLR, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + {PPC_INS_BNSLRL, &Capstone2LlvmIrTranslatorPowerpc_impl::translateB}, + //Branch if unordered + //PPC_INS_BUN => PPC_INS_BSO + //PPC_INS_BUNA => PPC_INS_BSOA + //PPC_INS_BUNCTR => PPC_INS_BSOCTR + //PPC_INS_BUNCTRL => PPC_INS_BSOCTRL + //PPC_INS_BUNL => PPC_INS_BSOL + //PPC_INS_BUNLA => PPC_INS_BSOLA + //PPC_INS_BUNLR => PPC_INS_BSOLR + //PPC_INS_BUNLRL => PPC_INS_BSOLRL + + //Branch if not unordered + //PPC_INS_BNU => PPC_INS_BNS + //PPC_INS_BNUA => PPC_INS_BNSA + //PPC_INS_BNUCTR => PPC_INS_BNSCTR + //PPC_INS_BNUCTRL => PPC_INS_BNSCTRL + //PPC_INS_BNUL => PPC_INS_BNSL + //PPC_INS_BNULA => PPC_INS_BNSLA + //PPC_INS_BNULR => PPC_INS_BNSLR + //PPC_INS_BNULRL => PPC_INS_BNSLRL - {PPC_INS_BCT, nullptr}, }; } // namespace capstone2llvmir diff --git a/src/capstone2llvmir/x86/x86.cpp b/src/capstone2llvmir/x86/x86.cpp index c39f74aba..a06a36971 100644 --- a/src/capstone2llvmir/x86/x86.cpp +++ b/src/capstone2llvmir/x86/x86.cpp @@ -1194,6 +1194,7 @@ Capstone2LlvmIrTranslatorX86_impl::loadOpFloatingBinaryTop( llvm::Value* op0 = nullptr; llvm::Value* op1 = nullptr; llvm::Value* idx = nullptr; + llvm::Value* idx2= nullptr; if (xi->op_count == 0) { @@ -1214,7 +1215,7 @@ Capstone2LlvmIrTranslatorX86_impl::loadOpFloatingBinaryTop( auto reg2 = xi->operands[1].reg; unsigned regOff2 = reg2 - X86_REG_ST0; - auto* idx2 = regOff2 + idx2 = regOff2 ? irb.CreateAdd(top, llvm::ConstantInt::get(top->getType(), regOff2)) : top; @@ -1281,7 +1282,7 @@ Capstone2LlvmIrTranslatorX86_impl::loadOpFloatingBinaryTop( } if (i->id == X86_INS_FSUBP - || i->id == X86_INS_FADDP + || i->id == X86_INS_FADD || i->id == X86_INS_FDIVP || i->id == X86_INS_FDIVRP || i->id == X86_INS_FMULP @@ -1292,6 +1293,12 @@ Capstone2LlvmIrTranslatorX86_impl::loadOpFloatingBinaryTop( op1 = tmp; } + if (i->id == X86_INS_FXCH + && top == idx) + { + idx = idx2; + } + return std::make_tuple(op0, op1, top, idx); } @@ -4402,10 +4409,11 @@ void Capstone2LlvmIrTranslatorX86_impl::translateFadd(cs_insn* i, cs_x86* xi, ll EXPECT_IS_EXPR(i, xi, irb, (xi->op_count <= 2)); std::tie(op0, op1, top, idx) = loadOpFloatingBinaryTop(i, xi, irb); + bool isFADDP = xi->opcode[0] == 0xDE && xi->opcode[1] == 0x00&& xi->opcode[2] == 0x00 && xi->opcode[3] == 0x00; auto* fadd = irb.CreateFAdd(op0, op1); - if (xi->op_count == 2 || i->id == X86_INS_FADDP) + if (xi->op_count == 2 || isFADDP) { storeX87DataReg(irb, idx, fadd); } @@ -4414,7 +4422,7 @@ void Capstone2LlvmIrTranslatorX86_impl::translateFadd(cs_insn* i, cs_x86* xi, ll storeX87DataReg(irb, top, fadd); } - if (i->id == X86_INS_FADDP) + if (i->id == X86_INS_FADD) { x87IncTop(irb, top); } @@ -5068,16 +5076,16 @@ void Capstone2LlvmIrTranslatorX86_impl::translateFucomPop(cs_insn* i, cs_x86* xi bool doublePop = i->id == X86_INS_FUCOMPP || i->id == X86_INS_FCOMPP; bool pop = i->id == X86_INS_FUCOMP || i->id == X86_INS_FCOMP - || i->id == X86_INS_FUCOMIP || i->id == X86_INS_FCOMIP + || i->id == X86_INS_FUCOMPI || i->id == X86_INS_FCOMPI || i->id == X86_INS_FICOMP || doublePop; uint32_t r1 = X87_REG_C0; uint32_t r2 = X87_REG_C2; uint32_t r3 = X87_REG_C3; if (i->id == X86_INS_FUCOMI - || i->id == X86_INS_FUCOMIP + || i->id == X86_INS_FUCOMPI || i->id == X86_INS_FCOMI - || i->id == X86_INS_FCOMIP) + || i->id == X86_INS_FCOMPI) { r1 = X86_REG_CF; r2 = X86_REG_PF; diff --git a/src/capstone2llvmir/x86/x86_init.cpp b/src/capstone2llvmir/x86/x86_init.cpp index 89014cb6f..15637452a 100644 --- a/src/capstone2llvmir/x86/x86_init.cpp +++ b/src/capstone2llvmir/x86/x86_init.cpp @@ -623,7 +623,6 @@ Capstone2LlvmIrTranslatorX86_impl::_i2fm = {X86_INS_ADDSUBPS, nullptr}, {X86_INS_FADD, &Capstone2LlvmIrTranslatorX86_impl::translateFadd}, {X86_INS_FIADD, &Capstone2LlvmIrTranslatorX86_impl::translateFadd}, - {X86_INS_FADDP, &Capstone2LlvmIrTranslatorX86_impl::translateFadd}, {X86_INS_ADOX, &Capstone2LlvmIrTranslatorX86_impl::translateAdc}, {X86_INS_AESDECLAST, nullptr}, {X86_INS_AESDEC, nullptr}, @@ -711,7 +710,7 @@ Capstone2LlvmIrTranslatorX86_impl::_i2fm = {X86_INS_COMISD, nullptr}, {X86_INS_COMISS, nullptr}, {X86_INS_FCOMP, &Capstone2LlvmIrTranslatorX86_impl::translateFucomPop}, - {X86_INS_FCOMIP, &Capstone2LlvmIrTranslatorX86_impl::translateFucomPop}, + {X86_INS_FCOMPI, &Capstone2LlvmIrTranslatorX86_impl::translateFucomPop}, {X86_INS_FCOMI, &Capstone2LlvmIrTranslatorX86_impl::translateFucomPop}, {X86_INS_FCOM, &Capstone2LlvmIrTranslatorX86_impl::translateFucomPop}, {X86_INS_FCOS, &Capstone2LlvmIrTranslatorX86_impl::translateFcos}, @@ -1118,7 +1117,6 @@ Capstone2LlvmIrTranslatorX86_impl::_i2fm = {X86_INS_PCMPGTQ, nullptr}, {X86_INS_PCMPISTRI, nullptr}, {X86_INS_PCMPISTRM, nullptr}, - {X86_INS_PCOMMIT, nullptr}, {X86_INS_PDEP, nullptr}, {X86_INS_PEXT, nullptr}, {X86_INS_PEXTRB, nullptr}, @@ -1311,12 +1309,12 @@ Capstone2LlvmIrTranslatorX86_impl::_i2fm = {X86_INS_FTST, &Capstone2LlvmIrTranslatorX86_impl::translateFucomPop}, {X86_INS_TZCNT, nullptr}, {X86_INS_TZMSK, nullptr}, - {X86_INS_FUCOMIP, &Capstone2LlvmIrTranslatorX86_impl::translateFucomPop}, + {X86_INS_FUCOMPI, &Capstone2LlvmIrTranslatorX86_impl::translateFucomPop}, {X86_INS_FUCOMI, &Capstone2LlvmIrTranslatorX86_impl::translateFucomPop}, {X86_INS_FUCOMPP, &Capstone2LlvmIrTranslatorX86_impl::translateFucomPop}, {X86_INS_FUCOMP, &Capstone2LlvmIrTranslatorX86_impl::translateFucomPop}, {X86_INS_FUCOM, &Capstone2LlvmIrTranslatorX86_impl::translateFucomPop}, - {X86_INS_UD2B, &Capstone2LlvmIrTranslatorX86_impl::translateNop}, + {X86_INS_UD1, &Capstone2LlvmIrTranslatorX86_impl::translateNop}, {X86_INS_UNPCKHPD, nullptr}, {X86_INS_UNPCKHPS, nullptr}, {X86_INS_UNPCKLPD, nullptr}, @@ -1354,9 +1352,7 @@ Capstone2LlvmIrTranslatorX86_impl::_i2fm = {X86_INS_VCOMPRESSPS, nullptr}, {X86_INS_VCVTDQ2PD, nullptr}, {X86_INS_VCVTDQ2PS, nullptr}, - {X86_INS_VCVTPD2DQX, nullptr}, {X86_INS_VCVTPD2DQ, nullptr}, - {X86_INS_VCVTPD2PSX, nullptr}, {X86_INS_VCVTPD2PS, nullptr}, {X86_INS_VCVTPD2UDQ, nullptr}, {X86_INS_VCVTPH2PS, nullptr}, @@ -1368,7 +1364,6 @@ Capstone2LlvmIrTranslatorX86_impl::_i2fm = {X86_INS_VCVTSD2USI, nullptr}, {X86_INS_VCVTSS2SI, nullptr}, {X86_INS_VCVTSS2USI, nullptr}, - {X86_INS_VCVTTPD2DQX, nullptr}, {X86_INS_VCVTTPD2DQ, nullptr}, {X86_INS_VCVTTPD2UDQ, nullptr}, {X86_INS_VCVTTPS2DQ, nullptr}, @@ -1939,180 +1934,13 @@ Capstone2LlvmIrTranslatorX86_impl::_i2fm = // pseudo instructions {X86_INS_CMPSS, nullptr}, - {X86_INS_CMPEQSS, nullptr}, - {X86_INS_CMPLTSS, nullptr}, - {X86_INS_CMPLESS, nullptr}, - {X86_INS_CMPUNORDSS, nullptr}, - {X86_INS_CMPNEQSS, nullptr}, - {X86_INS_CMPNLTSS, nullptr}, - {X86_INS_CMPNLESS, nullptr}, - {X86_INS_CMPORDSS, nullptr}, - {X86_INS_CMPSD, &Capstone2LlvmIrTranslatorX86_impl::translateCompareString}, - {X86_INS_CMPEQSD, nullptr}, - {X86_INS_CMPLTSD, nullptr}, - {X86_INS_CMPLESD, nullptr}, - {X86_INS_CMPUNORDSD, nullptr}, - {X86_INS_CMPNEQSD, nullptr}, - {X86_INS_CMPNLTSD, nullptr}, - {X86_INS_CMPNLESD, nullptr}, - {X86_INS_CMPORDSD, nullptr}, - {X86_INS_CMPPS, nullptr}, - {X86_INS_CMPEQPS, nullptr}, - {X86_INS_CMPLTPS, nullptr}, - {X86_INS_CMPLEPS, nullptr}, - {X86_INS_CMPUNORDPS, nullptr}, - {X86_INS_CMPNEQPS, nullptr}, - {X86_INS_CMPNLTPS, nullptr}, - {X86_INS_CMPNLEPS, nullptr}, - {X86_INS_CMPORDPS, nullptr}, - {X86_INS_CMPPD, nullptr}, - {X86_INS_CMPEQPD, nullptr}, - {X86_INS_CMPLTPD, nullptr}, - {X86_INS_CMPLEPD, nullptr}, - {X86_INS_CMPUNORDPD, nullptr}, - {X86_INS_CMPNEQPD, nullptr}, - {X86_INS_CMPNLTPD, nullptr}, - {X86_INS_CMPNLEPD, nullptr}, - {X86_INS_CMPORDPD, nullptr}, - {X86_INS_VCMPSS, nullptr}, - {X86_INS_VCMPEQSS, nullptr}, - {X86_INS_VCMPLTSS, nullptr}, - {X86_INS_VCMPLESS, nullptr}, - {X86_INS_VCMPUNORDSS, nullptr}, - {X86_INS_VCMPNEQSS, nullptr}, - {X86_INS_VCMPNLTSS, nullptr}, - {X86_INS_VCMPNLESS, nullptr}, - {X86_INS_VCMPORDSS, nullptr}, - {X86_INS_VCMPEQ_UQSS, nullptr}, - {X86_INS_VCMPNGESS, nullptr}, - {X86_INS_VCMPNGTSS, nullptr}, - {X86_INS_VCMPFALSESS, nullptr}, - {X86_INS_VCMPNEQ_OQSS, nullptr}, - {X86_INS_VCMPGESS, nullptr}, - {X86_INS_VCMPGTSS, nullptr}, - {X86_INS_VCMPTRUESS, nullptr}, - {X86_INS_VCMPEQ_OSSS, nullptr}, - {X86_INS_VCMPLT_OQSS, nullptr}, - {X86_INS_VCMPLE_OQSS, nullptr}, - {X86_INS_VCMPUNORD_SSS, nullptr}, - {X86_INS_VCMPNEQ_USSS, nullptr}, - {X86_INS_VCMPNLT_UQSS, nullptr}, - {X86_INS_VCMPNLE_UQSS, nullptr}, - {X86_INS_VCMPORD_SSS, nullptr}, - {X86_INS_VCMPEQ_USSS, nullptr}, - {X86_INS_VCMPNGE_UQSS, nullptr}, - {X86_INS_VCMPNGT_UQSS, nullptr}, - {X86_INS_VCMPFALSE_OSSS, nullptr}, - {X86_INS_VCMPNEQ_OSSS, nullptr}, - {X86_INS_VCMPGE_OQSS, nullptr}, - {X86_INS_VCMPGT_OQSS, nullptr}, - {X86_INS_VCMPTRUE_USSS, nullptr}, - {X86_INS_VCMPSD, nullptr}, - {X86_INS_VCMPEQSD, nullptr}, - {X86_INS_VCMPLTSD, nullptr}, - {X86_INS_VCMPLESD, nullptr}, - {X86_INS_VCMPUNORDSD, nullptr}, - {X86_INS_VCMPNEQSD, nullptr}, - {X86_INS_VCMPNLTSD, nullptr}, - {X86_INS_VCMPNLESD, nullptr}, - {X86_INS_VCMPORDSD, nullptr}, - {X86_INS_VCMPEQ_UQSD, nullptr}, - {X86_INS_VCMPNGESD, nullptr}, - {X86_INS_VCMPNGTSD, nullptr}, - {X86_INS_VCMPFALSESD, nullptr}, - {X86_INS_VCMPNEQ_OQSD, nullptr}, - {X86_INS_VCMPGESD, nullptr}, - {X86_INS_VCMPGTSD, nullptr}, - {X86_INS_VCMPTRUESD, nullptr}, - {X86_INS_VCMPEQ_OSSD, nullptr}, - {X86_INS_VCMPLT_OQSD, nullptr}, - {X86_INS_VCMPLE_OQSD, nullptr}, - {X86_INS_VCMPUNORD_SSD, nullptr}, - {X86_INS_VCMPNEQ_USSD, nullptr}, - {X86_INS_VCMPNLT_UQSD, nullptr}, - {X86_INS_VCMPNLE_UQSD, nullptr}, - {X86_INS_VCMPORD_SSD, nullptr}, - {X86_INS_VCMPEQ_USSD, nullptr}, - {X86_INS_VCMPNGE_UQSD, nullptr}, - {X86_INS_VCMPNGT_UQSD, nullptr}, - {X86_INS_VCMPFALSE_OSSD, nullptr}, - {X86_INS_VCMPNEQ_OSSD, nullptr}, - {X86_INS_VCMPGE_OQSD, nullptr}, - {X86_INS_VCMPGT_OQSD, nullptr}, - {X86_INS_VCMPTRUE_USSD, nullptr}, - {X86_INS_VCMPPS, nullptr}, - {X86_INS_VCMPEQPS, nullptr}, - {X86_INS_VCMPLTPS, nullptr}, - {X86_INS_VCMPLEPS, nullptr}, - {X86_INS_VCMPUNORDPS, nullptr}, - {X86_INS_VCMPNEQPS, nullptr}, - {X86_INS_VCMPNLTPS, nullptr}, - {X86_INS_VCMPNLEPS, nullptr}, - {X86_INS_VCMPORDPS, nullptr}, - {X86_INS_VCMPEQ_UQPS, nullptr}, - {X86_INS_VCMPNGEPS, nullptr}, - {X86_INS_VCMPNGTPS, nullptr}, - {X86_INS_VCMPFALSEPS, nullptr}, - {X86_INS_VCMPNEQ_OQPS, nullptr}, - {X86_INS_VCMPGEPS, nullptr}, - {X86_INS_VCMPGTPS, nullptr}, - {X86_INS_VCMPTRUEPS, nullptr}, - {X86_INS_VCMPEQ_OSPS, nullptr}, - {X86_INS_VCMPLT_OQPS, nullptr}, - {X86_INS_VCMPLE_OQPS, nullptr}, - {X86_INS_VCMPUNORD_SPS, nullptr}, - {X86_INS_VCMPNEQ_USPS, nullptr}, - {X86_INS_VCMPNLT_UQPS, nullptr}, - {X86_INS_VCMPNLE_UQPS, nullptr}, - {X86_INS_VCMPORD_SPS, nullptr}, - {X86_INS_VCMPEQ_USPS, nullptr}, - {X86_INS_VCMPNGE_UQPS, nullptr}, - {X86_INS_VCMPNGT_UQPS, nullptr}, - {X86_INS_VCMPFALSE_OSPS, nullptr}, - {X86_INS_VCMPNEQ_OSPS, nullptr}, - {X86_INS_VCMPGE_OQPS, nullptr}, - {X86_INS_VCMPGT_OQPS, nullptr}, - {X86_INS_VCMPTRUE_USPS, nullptr}, - {X86_INS_VCMPPD, nullptr}, - {X86_INS_VCMPEQPD, nullptr}, - {X86_INS_VCMPLTPD, nullptr}, - {X86_INS_VCMPLEPD, nullptr}, - {X86_INS_VCMPUNORDPD, nullptr}, - {X86_INS_VCMPNEQPD, nullptr}, - {X86_INS_VCMPNLTPD, nullptr}, - {X86_INS_VCMPNLEPD, nullptr}, - {X86_INS_VCMPORDPD, nullptr}, - {X86_INS_VCMPEQ_UQPD, nullptr}, - {X86_INS_VCMPNGEPD, nullptr}, - {X86_INS_VCMPNGTPD, nullptr}, - {X86_INS_VCMPFALSEPD, nullptr}, - {X86_INS_VCMPNEQ_OQPD, nullptr}, - {X86_INS_VCMPGEPD, nullptr}, - {X86_INS_VCMPGTPD, nullptr}, - {X86_INS_VCMPTRUEPD, nullptr}, - {X86_INS_VCMPEQ_OSPD, nullptr}, - {X86_INS_VCMPLT_OQPD, nullptr}, - {X86_INS_VCMPLE_OQPD, nullptr}, - {X86_INS_VCMPUNORD_SPD, nullptr}, - {X86_INS_VCMPNEQ_USPD, nullptr}, - {X86_INS_VCMPNLT_UQPD, nullptr}, - {X86_INS_VCMPNLE_UQPD, nullptr}, - {X86_INS_VCMPORD_SPD, nullptr}, - {X86_INS_VCMPEQ_USPD, nullptr}, - {X86_INS_VCMPNGE_UQPD, nullptr}, - {X86_INS_VCMPNGT_UQPD, nullptr}, - {X86_INS_VCMPFALSE_OSPD, nullptr}, - {X86_INS_VCMPNEQ_OSPD, nullptr}, - {X86_INS_VCMPGE_OQPD, nullptr}, - {X86_INS_VCMPGT_OQPD, nullptr}, - {X86_INS_VCMPTRUE_USPD, nullptr}, {X86_INS_ENDBR32, &Capstone2LlvmIrTranslatorX86_impl::translateNop}, {X86_INS_ENDBR64, &Capstone2LlvmIrTranslatorX86_impl::translateNop}, diff --git a/tests/capstone2llvmir/arm_tests.cpp b/tests/capstone2llvmir/arm_tests.cpp index 9ec01b05d..03044f593 100644 --- a/tests/capstone2llvmir/arm_tests.cpp +++ b/tests/capstone2llvmir/arm_tests.cpp @@ -1655,9 +1655,9 @@ TEST_P(Capstone2LlvmIrTranslatorArmTests, ARM_INS_MOVW) emulate("movw r0, #0xabcd"); - EXPECT_JUST_REGISTERS_LOADED({ARM_REG_R0}); + EXPECT_NO_REGISTERS_LOADED(); EXPECT_JUST_REGISTERS_STORED({ - {ARM_REG_R0, 0x1234abcd}, + {ARM_REG_R0, 0xabcd}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1717,7 +1717,9 @@ TEST_P(Capstone2LlvmIrTranslatorArmTests, ARM_INS_NOP) EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); - EXPECT_NO_VALUE_CALLED(); + EXPECT_JUST_VALUES_CALLED({ + {_module.getFunction("__asm_nop"), {}}, + }); } // diff --git a/tests/capstone2llvmir/powerpc_tests.cpp b/tests/capstone2llvmir/powerpc_tests.cpp index 85e020246..16607ac60 100644 --- a/tests/capstone2llvmir/powerpc_tests.cpp +++ b/tests/capstone2llvmir/powerpc_tests.cpp @@ -158,10 +158,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_ADD_dot_zero) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0, PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x0}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, true}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, true}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -181,10 +181,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_ADD_dot_negative) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0, PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, ANY}, - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -204,10 +204,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_ADD_dot_postitive) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0, PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x3333}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -356,10 +356,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_ADDIC_dot_32_true) EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xfe}, // 0xffffffff + 0xff = 0x01 | 00 00 00 fe {PPC_REG_CARRY, true}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -424,10 +424,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_ADDC_dot_32_true) EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xfe}, // 0xffffffff + 0xff = 0x01 | 00 00 00 fe {PPC_REG_CARRY, true}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -495,10 +495,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_ADDE_dot_true) EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x12345671}, {PPC_REG_CARRY, false}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -563,10 +563,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_ADDZE_dot_true) EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x12340001}, {PPC_REG_CARRY, false}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -631,10 +631,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_ADDME_dot_true) EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x12340000}, {PPC_REG_CARRY, true}, // TODO: I'm not sure about this, check it somehow. - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -677,10 +677,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_AND_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x10203040}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -703,10 +703,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_ANDI_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xf0f0}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -749,10 +749,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_ANDC_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xf0f0f0f0}, - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -775,10 +775,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_ANDIS_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xffff0000}, - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -821,10 +821,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_OR_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x1f3f0f0f}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -889,10 +889,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_ORC_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xf0f0f0f0}, - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -957,10 +957,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_XOR_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xf0f0f0f0}, - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1066,10 +1066,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_NOR_dot_32) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xe0c0f0f0}, - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1148,10 +1148,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_NEG_dot_32) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xedcba988}, - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1188,10 +1188,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_NEG_dot_64) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xfedcba9876543211}, - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1253,10 +1253,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_NAND_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xefdfcfbf}, - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1299,10 +1299,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_SUBF_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x0}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, true}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, true}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1347,10 +1347,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_SUBFC_dot_32) EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xffffeeef}, {PPC_REG_CARRY, false}, - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1441,10 +1441,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_SUBFE_dot_32_carry_true) EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xffffeeef}, {PPC_REG_CARRY, false}, - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1509,10 +1509,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_SUBFME_32_dot_carry_true) EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xffffdddd}, {PPC_REG_CARRY, true}, // ??? - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1577,10 +1577,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_SUBFZE_dot_32_carry_true) EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0xffffddde}, {PPC_REG_CARRY, false}, // ??? - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1645,10 +1645,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_MULLW_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x26cca6}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1691,10 +1691,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_MULHW_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x02468acf}, // 0x02 46 8a cf | 0e ca 86 42 - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1737,10 +1737,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_MULHWU_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x02468acf}, // 0x02 46 8a cf | 0e ca 86 42 - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1783,10 +1783,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_DIVW_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x1b20}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1829,10 +1829,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_DIVWU_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x1b20}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1875,10 +1875,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_EQV_dot) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x6aaeeaa6}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1919,10 +1919,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CNTLZW_dot_zero) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x0}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, true}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, true}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -1999,10 +1999,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_EXTSB_zero_dot_32) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x78}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -2061,10 +2061,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_EXTSH_zero_dot_32) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x7856}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -2123,10 +2123,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_EXTSW_zero_dot_32) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_R0, 0x78123456}, - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -2342,10 +2342,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_MTCRF) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR0_LT, ANY}, - {PPC_REG_CR0_GT, ANY}, - {PPC_REG_CR0_EQ, ANY}, - {PPC_REG_CR0_SO, ANY}, + {PPC_REG_CR0LT, ANY}, + {PPC_REG_CR0GT, ANY}, + {PPC_REG_CR0EQ, ANY}, + {PPC_REG_CR0UN, ANY}, {PPC_REG_CR1, ANY}, {PPC_REG_CR2, ANY}, {PPC_REG_CR3, ANY}, @@ -2413,19 +2413,19 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CRAND) ALL_MODES; setRegisters({ - {PPC_REG_R1, 0x12}, - {PPC_REG_R2, 0x34}, + {PPC_REG_CR0GT, 0x12}, + {PPC_REG_CR0EQ, 0x34}, {PPC_REG_R3, 0x56}, }); emulate("crand 1, 2, 3"); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R1, PPC_REG_R2, PPC_REG_R3}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0GT, PPC_REG_CR0EQ, PPC_REG_CR0UN}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR0_LT, ANY}, - {PPC_REG_CR0_GT, ANY}, - {PPC_REG_CR0_EQ, ANY}, - {PPC_REG_CR0_SO, ANY}, + {PPC_REG_CR0LT, ANY}, + {PPC_REG_CR0GT, ANY}, + {PPC_REG_CR0EQ, ANY}, + {PPC_REG_CR0UN, ANY}, {PPC_REG_CR1, ANY}, {PPC_REG_CR2, ANY}, {PPC_REG_CR3, ANY}, @@ -2436,7 +2436,7 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CRAND) }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ - {_module.getFunction("__asm_crand"), {0x12, 0x34, 0x56}}, + {_module.getFunction("__asm_crand"), {0x0, 0x0, 0x0}}, }); } @@ -3364,15 +3364,15 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_MCRF_read_cr0) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, true}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, true}, + {PPC_REG_CR0UN, false}, }); emulate("mcrf 4, 0"); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_LT, PPC_REG_CR0_GT, PPC_REG_CR0_EQ, PPC_REG_CR0_SO}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0LT, PPC_REG_CR0GT, PPC_REG_CR0EQ, PPC_REG_CR0UN}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CR4, ANY}, }); @@ -3394,10 +3394,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_MCRF_write_cr0) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR0_LT, ANY}, - {PPC_REG_CR0_GT, ANY}, - {PPC_REG_CR0_EQ, ANY}, - {PPC_REG_CR0_SO, ANY}, + {PPC_REG_CR0LT, ANY}, + {PPC_REG_CR0GT, ANY}, + {PPC_REG_CR0EQ, ANY}, + {PPC_REG_CR0UN, ANY}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -3796,10 +3796,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPD_lt) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0, PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -3818,10 +3818,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPD_gt) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0, PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -3840,10 +3840,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPD_eq) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0, PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, true}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, true}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -3862,10 +3862,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPD_lt_sign_32) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0, PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -3884,10 +3884,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPD_lt_sign_64) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0, PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -3906,10 +3906,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPD_lt_cr7) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0, PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR7_LT, true}, - {PPC_REG_CR7_GT, false}, - {PPC_REG_CR7_EQ, false}, - {PPC_REG_CR7_SO, false}, + {PPC_REG_CR7LT, true}, + {PPC_REG_CR7GT, false}, + {PPC_REG_CR7EQ, false}, + {PPC_REG_CR7UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -3931,10 +3931,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPDI_lt_cr7) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR7_LT, true}, - {PPC_REG_CR7_GT, false}, - {PPC_REG_CR7_EQ, false}, - {PPC_REG_CR7_SO, false}, + {PPC_REG_CR7LT, true}, + {PPC_REG_CR7GT, false}, + {PPC_REG_CR7EQ, false}, + {PPC_REG_CR7UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -3957,10 +3957,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPW_lt_cr7) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0, PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR7_LT, true}, - {PPC_REG_CR7_GT, false}, - {PPC_REG_CR7_EQ, false}, - {PPC_REG_CR7_SO, false}, + {PPC_REG_CR7LT, true}, + {PPC_REG_CR7GT, false}, + {PPC_REG_CR7EQ, false}, + {PPC_REG_CR7UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -3979,10 +3979,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPW_lt_cr7_64_trunc) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0, PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR7_LT, true}, - {PPC_REG_CR7_GT, false}, - {PPC_REG_CR7_EQ, false}, - {PPC_REG_CR7_SO, false}, + {PPC_REG_CR7LT, true}, + {PPC_REG_CR7GT, false}, + {PPC_REG_CR7EQ, false}, + {PPC_REG_CR7UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -4004,10 +4004,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPWI_lt_cr7) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR7_LT, true}, - {PPC_REG_CR7_GT, false}, - {PPC_REG_CR7_EQ, false}, - {PPC_REG_CR7_SO, false}, + {PPC_REG_CR7LT, true}, + {PPC_REG_CR7GT, false}, + {PPC_REG_CR7EQ, false}, + {PPC_REG_CR7UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -4030,10 +4030,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPLD_gt_unsign_32) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0, PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR5_LT, false}, - {PPC_REG_CR5_GT, true}, - {PPC_REG_CR5_EQ, false}, - {PPC_REG_CR5_SO, false}, + {PPC_REG_CR5LT, false}, + {PPC_REG_CR5GT, true}, + {PPC_REG_CR5EQ, false}, + {PPC_REG_CR5UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -4055,10 +4055,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPLDI_gt_unsign_32) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR5_LT, false}, - {PPC_REG_CR5_GT, true}, - {PPC_REG_CR5_EQ, false}, - {PPC_REG_CR5_SO, false}, + {PPC_REG_CR5LT, false}, + {PPC_REG_CR5GT, true}, + {PPC_REG_CR5EQ, false}, + {PPC_REG_CR5UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -4081,10 +4081,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPLW_gt_unsign_32) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0, PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR5_LT, false}, - {PPC_REG_CR5_GT, true}, - {PPC_REG_CR5_EQ, false}, - {PPC_REG_CR5_SO, false}, + {PPC_REG_CR5LT, false}, + {PPC_REG_CR5GT, true}, + {PPC_REG_CR5EQ, false}, + {PPC_REG_CR5UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -4103,10 +4103,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPLW_eq_unsign_64) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0, PPC_REG_R1}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR5_LT, false}, - {PPC_REG_CR5_GT, false}, - {PPC_REG_CR5_EQ, true}, - {PPC_REG_CR5_SO, false}, + {PPC_REG_CR5LT, false}, + {PPC_REG_CR5GT, false}, + {PPC_REG_CR5EQ, true}, + {PPC_REG_CR5UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -4128,10 +4128,10 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CMPLWI_gt_unsign_32) EXPECT_JUST_REGISTERS_LOADED({PPC_REG_R0}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR5_LT, false}, - {PPC_REG_CR5_GT, true}, - {PPC_REG_CR5_EQ, false}, - {PPC_REG_CR5_SO, false}, + {PPC_REG_CR5LT, false}, + {PPC_REG_CR5GT, true}, + {PPC_REG_CR5EQ, false}, + {PPC_REG_CR5UN, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -4149,7 +4149,7 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CRSET_cr0) EXPECT_NO_REGISTERS_LOADED(); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR0_EQ, true}, + {PPC_REG_CR0EQ, true}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -4163,7 +4163,7 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CRSET_cr5) EXPECT_NO_REGISTERS_LOADED(); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR5_EQ, true}, + {PPC_REG_CR5EQ, true}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -4181,7 +4181,7 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CRCLR_cr0) EXPECT_NO_REGISTERS_LOADED(); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR0_EQ, false}, + {PPC_REG_CR0EQ, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -4195,7 +4195,7 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CRCLR_cr5) EXPECT_NO_REGISTERS_LOADED(); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR5_EQ, false}, + {PPC_REG_CR5EQ, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -4210,14 +4210,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CRNOT) ALL_MODES; setRegisters({ - {PPC_REG_CR5_SO, true}, + {PPC_REG_CR5UN, true}, }); emulate("crnot 4*cr2+eq, 4*cr5+so"); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR5_SO}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR5UN}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR2_EQ, false}, + {PPC_REG_CR2EQ, false}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -4232,14 +4232,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_CRMOVE) ALL_MODES; setRegisters({ - {PPC_REG_CR5_SO, true}, + {PPC_REG_CR5UN, true}, }); emulate("crmove 4*cr2+eq, 4*cr5+so"); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR5_SO}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR5UN}); EXPECT_JUST_REGISTERS_STORED({ - {PPC_REG_CR2_EQ, true}, + {PPC_REG_CR2EQ, true}, }); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_NO_VALUE_CALLED(); @@ -4418,12 +4418,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_blt_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, true}, + {PPC_REG_CR0LT, true}, }); emulate("blt 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4437,12 +4437,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_blt_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, false}, + {PPC_REG_CR0LT, false}, }); emulate("blt 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4456,13 +4456,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_ble_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, true}, - {PPC_REG_CR0_EQ, false}, + {PPC_REG_CR0LT, true}, + {PPC_REG_CR0EQ, false}, }); emulate("ble 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_LT, PPC_REG_CR0_EQ}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0LT, PPC_REG_CR0EQ}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4476,13 +4476,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_ble_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, false}, - {PPC_REG_CR0_EQ, false}, + {PPC_REG_CR0LT, false}, + {PPC_REG_CR0EQ, false}, }); emulate("ble 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_LT, PPC_REG_CR0_EQ}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0LT, PPC_REG_CR0EQ}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4496,12 +4496,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_beq_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_EQ, true}, + {PPC_REG_CR0EQ, true}, }); emulate("beq 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_EQ}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0EQ}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4515,12 +4515,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_beq_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_EQ, false}, + {PPC_REG_CR0EQ, false}, }); emulate("beq 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_EQ}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0EQ}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4534,12 +4534,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_bne_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_EQ, false}, + {PPC_REG_CR0EQ, false}, }); emulate("bne 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_EQ}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0EQ}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4553,12 +4553,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_bne_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_EQ, true}, + {PPC_REG_CR0EQ, true}, }); emulate("bne 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_EQ}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0EQ}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4572,12 +4572,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_bgt_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_GT, true}, + {PPC_REG_CR0GT, true}, }); emulate("bgt 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_GT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0GT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4591,12 +4591,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_bgt_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_GT, false}, + {PPC_REG_CR0GT, false}, }); emulate("bgt 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_GT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0GT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4610,13 +4610,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_bge_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_GT, true}, - {PPC_REG_CR0_EQ, false}, + {PPC_REG_CR0GT, true}, + {PPC_REG_CR0EQ, false}, }); emulate("bge 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_GT, PPC_REG_CR0_EQ}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0GT, PPC_REG_CR0EQ}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4630,13 +4630,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_bge_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_GT, false}, - {PPC_REG_CR0_EQ, false}, + {PPC_REG_CR0GT, false}, + {PPC_REG_CR0EQ, false}, }); emulate("bge 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_GT, PPC_REG_CR0_EQ}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0GT, PPC_REG_CR0EQ}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4650,12 +4650,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_bun_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_SO, true}, + {PPC_REG_CR0UN, true}, }); emulate("bun 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_SO}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0UN}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4669,12 +4669,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_bun_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0UN, false}, }); emulate("bun 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_SO}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0UN}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4688,12 +4688,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_bso_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_SO, true}, + {PPC_REG_CR0UN, true}, }); emulate("bso 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_SO}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0UN}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4707,12 +4707,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_bso_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0UN, false}, }); emulate("bso 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_SO}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0UN}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4726,12 +4726,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_bns_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0UN, false}, }); emulate("bns 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_SO}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0UN}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4745,12 +4745,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_bns_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_SO, true}, + {PPC_REG_CR0UN, true}, }); emulate("bns 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_SO}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0UN}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4764,12 +4764,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_bnu_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_SO, false}, + {PPC_REG_CR0UN, false}, }); emulate("bnu 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_SO}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0UN}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4783,12 +4783,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_bnu_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_SO, true}, + {PPC_REG_CR0UN, true}, }); emulate("bnu 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_SO}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0UN}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4802,12 +4802,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_blt_cr4_true) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("blt cr4, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4821,12 +4821,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_B_blt_cr4_false) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("blt cr4, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4860,12 +4860,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BA_blt_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, true}, + {PPC_REG_CR0LT, true}, }); emulate("blta 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4879,12 +4879,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BA_blt_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, false}, + {PPC_REG_CR0LT, false}, }); emulate("blta 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4898,12 +4898,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BA_blt_cr4_true) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("blta cr4, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4917,12 +4917,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BA_blt_cr4_false) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("blta cr4, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -4958,12 +4958,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BL_blt_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, true}, + {PPC_REG_CR0LT, true}, }); emulate("bltl 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -4979,12 +4979,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BL_blt_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, false}, + {PPC_REG_CR0LT, false}, }); emulate("bltl 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5000,12 +5000,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BL_blt_cr4_true) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("bltl cr4, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5021,12 +5021,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BL_blt_cr4_false) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("bltl cr4, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5064,12 +5064,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BLA_blt_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, true}, + {PPC_REG_CR0LT, true}, }); emulate("bltla 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5085,12 +5085,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BLA_blt_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, false}, + {PPC_REG_CR0LT, false}, }); emulate("bltla 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5106,12 +5106,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BLA_blt_cr4_true) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("bltla cr4, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5127,12 +5127,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BLA_blt_cr4_false) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("bltla cr4, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5173,12 +5173,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BLR_lt_cr0_true) setRegisters({ {PPC_REG_LR, 0x100004bc}, - {PPC_REG_CR0_LT, true}, + {PPC_REG_CR0LT, true}, }); emulate("bltlr", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR0LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5194,12 +5194,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BLR_lt_cr0_false) setRegisters({ {PPC_REG_LR, 0x100004bc}, - {PPC_REG_CR0_LT, false}, + {PPC_REG_CR0LT, false}, }); emulate("bltlr", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR0LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); // TODO: We cannot check this, because it is in always false branch. @@ -5216,12 +5216,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BLR_lt_cr4_true) setRegisters({ {PPC_REG_LR, 0x100004bc}, - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("bltlr cr4", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5237,12 +5237,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BLR_lt_cr4_false) setRegisters({ {PPC_REG_LR, 0x100004bc}, - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("bltlr cr4", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); // EXPECT_JUST_VALUES_CALLED({ @@ -5281,12 +5281,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BCTR_lt_cr0_true) setRegisters({ {PPC_REG_CTR, 0x100004bc}, - {PPC_REG_CR0_LT, true}, + {PPC_REG_CR0LT, true}, }); emulate("bltctr", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5301,12 +5301,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BCTR_lt_cr0_false) setRegisters({ {PPC_REG_CTR, 0x100004bc}, - {PPC_REG_CR0_LT, false}, + {PPC_REG_CR0LT, false}, }); emulate("bltctr", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5321,12 +5321,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BCTR_lt_cr4_true) setRegisters({ {PPC_REG_CTR, 0x100004bc}, - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("bltctr cr4", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5341,12 +5341,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BCTR_lt_cr4_false) setRegisters({ {PPC_REG_CTR, 0x100004bc}, - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("bltctr cr4", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5387,12 +5387,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BLRL_lt_cr0_true) setRegisters({ {PPC_REG_LR, 0x100004bc}, - {PPC_REG_CR0_LT, true}, + {PPC_REG_CR0LT, true}, }); emulate("bltlrl", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR0LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5410,12 +5410,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BLRL_lt_cr0_false) setRegisters({ {PPC_REG_LR, 0x100004bc}, - {PPC_REG_CR0_LT, false}, + {PPC_REG_CR0LT, false}, }); emulate("bltlrl", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR0LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5432,12 +5432,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BLRL_lt_cr4_true) setRegisters({ {PPC_REG_LR, 0x100004bc}, - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("bltlrl cr4", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5455,12 +5455,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BLRL_lt_cr4_false) setRegisters({ {PPC_REG_LR, 0x100004bc}, - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("bltlrl cr4", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5503,12 +5503,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BCTRL_lt_cr0_true) setRegisters({ {PPC_REG_CTR, 0x100004bc}, - {PPC_REG_CR0_LT, true}, + {PPC_REG_CR0LT, true}, }); emulate("bltctrl", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5525,12 +5525,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BCTRL_lt_cr0_false) setRegisters({ {PPC_REG_CTR, 0x100004bc}, - {PPC_REG_CR0_LT, false}, + {PPC_REG_CR0LT, false}, }); emulate("bltctrl", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5547,12 +5547,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BCTRL_lt_cr4_true) setRegisters({ {PPC_REG_CTR, 0x100004bc}, - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("bltctrl cr4", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5569,12 +5569,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BCTRL_lt_cr4_false) setRegisters({ {PPC_REG_CTR, 0x100004bc}, - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("bltctrl cr4", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5596,12 +5596,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BT_lt_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, true}, + {PPC_REG_CR0LT, true}, }); emulate("bt lt, 0x4bc", 0x10000510); // gets translated to b - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5615,12 +5615,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BT_lt_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, false}, + {PPC_REG_CR0LT, false}, }); emulate("bt lt, 0x4bc", 0x10000510); // gets translated to b - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5634,12 +5634,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BT_lt_cr4_true) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("bt 4*cr4+lt, 0x4bc", 0x10000510); // gets translated to b - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5653,12 +5653,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BT_lt_cr4_false) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("bt 4*cr4+lt, 0x4bc", 0x10000510); // gets translated to b - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5678,12 +5678,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BTA_lt_cr4_true) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("bta 4*cr4+lt, 0x4bc", 0x10000510); // gets translated to ba - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5697,12 +5697,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BTA_lt_cr4_false) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("bta 4*cr4+lt, 0x4bc", 0x10000510); // gets translated to ba - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5723,12 +5723,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BTLR_lt_cr4_true) setRegisters({ {PPC_REG_LR, 0x100004bc}, - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("btlr 4*cr4+lt", 0x10000510); // gets translated to blr - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5744,12 +5744,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BTLR_lt_cr4_false) setRegisters({ {PPC_REG_LR, 0x100004bc}, - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("btlr 4*cr4+lt", 0x10000510); // gets translated to blr - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); // EXPECT_JUST_VALUES_CALLED({ @@ -5770,12 +5770,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BTCTR_lt_cr4_true) setRegisters({ {PPC_REG_CTR, 0x100004bc}, - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("btctr 4*cr4+lt", 0x10000510); // gets translated to bctr - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5790,12 +5790,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BTCTR_lt_cr4_false) setRegisters({ {PPC_REG_CTR, 0x100004bc}, - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("btctr 4*cr4+lt", 0x10000510); // gets translated to bctr - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -5815,12 +5815,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BTL_blt_cr4_true) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("btl 4*cr4+lt, 0x4bc", 0x10000510); // gets translated to bl - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5836,12 +5836,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BTL_blt_cr4_false) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("btl 4*cr4+lt, 0x4bc", 0x10000510); // gets translated to bl - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5863,12 +5863,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BTLA_blt_cr4_true) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("btla 4*cr4+lt, 0x4bc", 0x10000510); // gets translated to bla - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5884,12 +5884,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BTLA_blt_cr4_false) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("btla 4*cr4+lt, 0x4bc", 0x10000510); // gets translated to bla - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5912,12 +5912,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BTLRL_lt_cr4_true) setRegisters({ {PPC_REG_LR, 0x100004bc}, - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("btlrl 4*cr4+lt", 0x10000510); // gets translated to blrl - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5935,12 +5935,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BTLRL_lt_cr4_false) setRegisters({ {PPC_REG_LR, 0x100004bc}, - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("btlrl 4*cr4+lt", 0x10000510); // gets translated to blrl - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_LR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5963,12 +5963,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BTCTRL_lt_cr4_true) setRegisters({ {PPC_REG_CTR, 0x100004bc}, - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, }); emulate("btctrl 4*cr4+lt", 0x10000510); // gets translated to bctrl - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -5985,12 +5985,12 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BTCTRL_lt_cr4_false) setRegisters({ {PPC_REG_CTR, 0x100004bc}, - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, }); emulate("btctrl 4*cr4+lt", 0x10000510); // gets translated to bctrl - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_LR, 0x10000514}, }); @@ -6012,13 +6012,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BF_lt_cr0_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_GT, false}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0GT, false}, }); emulate("bf lt, 0x4bc", 0x10000510); // gets translated to b ge - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_GT, PPC_REG_CR0_EQ}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0GT, PPC_REG_CR0EQ}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -6032,13 +6032,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BF_lt_cr0_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_EQ, false}, - {PPC_REG_CR0_GT, true}, + {PPC_REG_CR0EQ, false}, + {PPC_REG_CR0GT, true}, }); emulate("bf lt, 0x4bc", 0x10000510); // gets translated to b ge - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0_GT, PPC_REG_CR0_EQ}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR0GT, PPC_REG_CR0EQ}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -6052,13 +6052,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BF_lt_cr4_true) ALL_MODES; setRegisters({ - {PPC_REG_CR4_EQ, false}, - {PPC_REG_CR4_GT, false}, + {PPC_REG_CR4EQ, false}, + {PPC_REG_CR4GT, false}, }); emulate("bf 4*cr4+lt, 0x4bc", 0x10000510); // gets translated to b ge - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_GT, PPC_REG_CR4_EQ}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4GT, PPC_REG_CR4EQ}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -6072,13 +6072,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_Bf_lt_cr4_false) ALL_MODES; setRegisters({ - {PPC_REG_CR4_EQ, true}, - {PPC_REG_CR4_GT, false}, + {PPC_REG_CR4EQ, true}, + {PPC_REG_CR4GT, false}, }); emulate("bf 4*cr4+lt, 0x4bc", 0x10000510); // gets translated to b ge - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4_GT, PPC_REG_CR4_EQ}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CR4GT, PPC_REG_CR4EQ}); EXPECT_NO_REGISTERS_STORED(); EXPECT_NO_MEMORY_LOADED_STORED(); EXPECT_JUST_VALUES_CALLED({ @@ -6689,13 +6689,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZT_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdnzt 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -6711,13 +6711,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZT_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdnzt 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -6733,13 +6733,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZT_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdnzt 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -6755,13 +6755,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZT_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdnzt 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -6777,13 +6777,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZT_nonzero_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, true}, + {PPC_REG_CR0LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdnzt lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -6799,13 +6799,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZT_nonzero_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, false}, + {PPC_REG_CR0LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdnzt lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -6821,13 +6821,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZT_zero_true) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, true}, + {PPC_REG_CR0LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdnzt lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -6843,13 +6843,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZT_zero_false) ALL_MODES; setRegisters({ - {PPC_REG_CR0_LT, false}, + {PPC_REG_CR0LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdnzt lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR0LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -6871,13 +6871,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTA_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdnzta 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -6893,13 +6893,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTA_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdnzta 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -6915,13 +6915,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTA_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdnzta 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -6937,13 +6937,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTA_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdnzta 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -6965,14 +6965,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTLR_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdnztlr 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -6988,14 +6988,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTLR_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdnztlr 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -7011,14 +7011,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTLR_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdnztlr 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -7035,14 +7035,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTLR_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdnztlr 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -7065,13 +7065,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTL_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdnztl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -7088,13 +7088,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTL_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdnztl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -7111,13 +7111,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTL_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdnztl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -7134,13 +7134,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTL_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdnztl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -7163,13 +7163,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTLA_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdnztla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -7186,13 +7186,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTLA_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdnztla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -7209,13 +7209,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTLA_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdnztla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -7232,13 +7232,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTLA_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdnztla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -7261,14 +7261,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTLRL_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdnztlrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -7285,14 +7285,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTLRL_nonzero_false_cr4 ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdnztlrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -7310,14 +7310,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTLRL_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdnztlrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -7335,14 +7335,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZTLRL_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdnztlrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -7366,13 +7366,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZF_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdnzf 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -7388,13 +7388,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZF_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdnzf 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -7410,13 +7410,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZF_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdnzf 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -7432,13 +7432,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZF_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdnzf 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -7460,13 +7460,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFA_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdnzfa 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -7482,13 +7482,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFA_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdnzfa 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -7504,13 +7504,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFA_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdnzfa 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -7526,13 +7526,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFA_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdnzfa 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -7558,14 +7558,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFA_zero_false_cr4) // ALL_MODES; // // setRegisters({ -// {PPC_REG_CR4_LT, true}, +// {PPC_REG_CR4LT, true}, // {PPC_REG_CTR, 10}, // {PPC_REG_LR, 0x100004bc}, // }); // // emulate("bdnzflr 4*cr4+lt", 0x10000510); // -// EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); +// EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); // EXPECT_JUST_REGISTERS_STORED({ // {PPC_REG_CTR, 9}, // }); @@ -7581,14 +7581,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFA_zero_false_cr4) // ALL_MODES; // // setRegisters({ -// {PPC_REG_CR4_LT, false}, +// {PPC_REG_CR4LT, false}, // {PPC_REG_CTR, 10}, // {PPC_REG_LR, 0x100004bc}, // }); // // emulate("bdnzflr 4*cr4+lt", 0x10000510); // -// EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); +// EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); // EXPECT_JUST_REGISTERS_STORED({ // {PPC_REG_CTR, 9}, // }); @@ -7604,14 +7604,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFA_zero_false_cr4) // ALL_MODES; // // setRegisters({ -// {PPC_REG_CR4_LT, true}, +// {PPC_REG_CR4LT, true}, // {PPC_REG_CTR, 1}, // {PPC_REG_LR, 0x100004bc}, // }); // // emulate("bdnzflr 4*cr4+lt", 0x10000510); // -// EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); +// EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); // EXPECT_JUST_REGISTERS_STORED({ // {PPC_REG_CTR, 0}, // }); @@ -7627,14 +7627,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFA_zero_false_cr4) // ALL_MODES; // // setRegisters({ -// {PPC_REG_CR4_LT, false}, +// {PPC_REG_CR4LT, false}, // {PPC_REG_CTR, 1}, // {PPC_REG_LR, 0x100004bc}, // }); // // emulate("bdnzflr 4*cr4+lt", 0x10000510); // -// EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); +// EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); // EXPECT_JUST_REGISTERS_STORED({ // {PPC_REG_CTR, 0}, // }); @@ -7656,13 +7656,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFL_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdnzfl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -7679,13 +7679,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFL_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdnzfl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -7702,13 +7702,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFL_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdnzfl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -7725,13 +7725,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFL_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdnzfl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -7754,13 +7754,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFLA_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdnzfla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -7777,13 +7777,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFLA_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdnzfla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -7800,13 +7800,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFLA_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdnzfla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -7823,13 +7823,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFLA_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdnzfla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -7852,14 +7852,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFLRL_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdnzflrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -7877,14 +7877,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFLRL_nonzero_false_cr4 ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdnzflrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -7901,14 +7901,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFLRL_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdnzflrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -7926,14 +7926,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDNZFLRL_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdnzflrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -7957,13 +7957,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZT_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdzt 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -7979,13 +7979,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZT_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdzt 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -8001,13 +8001,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZT_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdzt 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -8023,13 +8023,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZT_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdzt 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -8051,13 +8051,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTA_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdzta 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -8073,13 +8073,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTA_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdzta 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -8095,13 +8095,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTA_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdzta 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -8117,13 +8117,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTA_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdzta 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -8145,14 +8145,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTLR_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdztlr 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -8169,14 +8169,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTLR_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdztlr 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -8193,14 +8193,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTLR_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdztlr 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -8216,14 +8216,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTLR_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdztlr 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -8246,13 +8246,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTL_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdztl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -8269,13 +8269,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTL_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdztl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -8292,13 +8292,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTL_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdztl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -8315,13 +8315,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTL_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdztl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -8344,13 +8344,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTLA_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdztla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -8367,13 +8367,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTLA_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdztla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -8390,13 +8390,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTLA_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdztla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -8413,13 +8413,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTLA_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdztla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -8442,14 +8442,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTLRL_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdztlrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -8467,14 +8467,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTLRL_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdztlrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -8492,14 +8492,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTLRL_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdztlrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -8516,14 +8516,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZTLRL_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdztlrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -8547,13 +8547,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZF_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdzf 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -8569,13 +8569,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZF_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdzf 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -8591,13 +8591,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZF_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdzf 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -8613,13 +8613,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZF_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdzf 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -8641,13 +8641,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFA_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdzfa 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -8663,13 +8663,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFA_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdzfa 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -8685,13 +8685,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFA_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdzfa 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -8707,13 +8707,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFA_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdzfa 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -8735,14 +8735,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFLR_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdzflr 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -8759,14 +8759,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFLR_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdzflr 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, }); @@ -8783,14 +8783,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFLR_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdzflr 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -8807,14 +8807,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFLR_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdzflr 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, }); @@ -8836,13 +8836,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFL_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdzfl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -8859,13 +8859,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFL_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdzfl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -8882,13 +8882,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFL_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdzfl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -8905,13 +8905,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFL_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdzfl 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -8934,13 +8934,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFLA_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, }); emulate("bdzfla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -8957,13 +8957,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFLA_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, }); emulate("bdzfla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -8980,13 +8980,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFLA_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, }); emulate("bdzfla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -9003,13 +9003,13 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFLA_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, }); emulate("bdzfla 4*cr4+lt, 0x4bc", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -9032,14 +9032,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFLRL_nonzero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 10}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdzflrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -9057,14 +9057,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFLRL_nonzero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 10}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdzflrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 9}, {PPC_REG_LR, 0x10000514}, @@ -9082,14 +9082,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFLRL_zero_true_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, true}, + {PPC_REG_CR4LT, true}, {PPC_REG_CTR, 1}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdzflrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, @@ -9107,14 +9107,14 @@ TEST_P(Capstone2LlvmIrTranslatorPowerpcTests, PPC_INS_BDZFLRL_zero_false_cr4) ALL_MODES; setRegisters({ - {PPC_REG_CR4_LT, false}, + {PPC_REG_CR4LT, false}, {PPC_REG_CTR, 1}, {PPC_REG_LR, 0x100004bc}, }); emulate("bdzflrl 4*cr4+lt", 0x10000510); - EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4_LT, PPC_REG_LR}); + EXPECT_JUST_REGISTERS_LOADED({PPC_REG_CTR, PPC_REG_CR4LT, PPC_REG_LR}); EXPECT_JUST_REGISTERS_STORED({ {PPC_REG_CTR, 0}, {PPC_REG_LR, 0x10000514}, diff --git a/tests/capstone2llvmir/x86_tests.cpp b/tests/capstone2llvmir/x86_tests.cpp index c969b4dab..d1689cbd5 100644 --- a/tests/capstone2llvmir/x86_tests.cpp +++ b/tests/capstone2llvmir/x86_tests.cpp @@ -10732,6 +10732,7 @@ TEST_P(Capstone2LlvmIrTranslatorX86Tests, X86_INS_FADD_d8) EXPECT_JUST_REGISTERS_LOADED({X87_REG_TOP, X86_REG_ST2}); EXPECT_JUST_REGISTERS_STORED({ + {X87_REG_TOP, 0x3}, {X86_REG_ST2, 3.14 + 3.14}, }); EXPECT_JUST_MEMORY_LOADED({0x1234}); @@ -10756,6 +10757,7 @@ TEST_P(Capstone2LlvmIrTranslatorX86Tests, X86_INS_FADD_dc) EXPECT_JUST_REGISTERS_LOADED({X87_REG_TOP, X86_REG_ST2}); EXPECT_JUST_REGISTERS_STORED({ + {X87_REG_TOP, 0x3}, {X86_REG_ST2, 3.14 + 3.14}, }); EXPECT_JUST_MEMORY_LOADED({0x1234}); @@ -10777,6 +10779,7 @@ TEST_P(Capstone2LlvmIrTranslatorX86Tests, X86_INS_FADD_d8_c0) EXPECT_JUST_REGISTERS_LOADED({X87_REG_TOP, X86_REG_ST2, X86_REG_ST5}); EXPECT_JUST_REGISTERS_STORED({ + {X87_REG_TOP, 0x3}, {X86_REG_ST2, 3.14 + 3.14}, }); EXPECT_NO_MEMORY_LOADED_STORED(); @@ -10797,6 +10800,7 @@ TEST_P(Capstone2LlvmIrTranslatorX86Tests, X86_INS_FADD_dc_c0) EXPECT_JUST_REGISTERS_LOADED({X87_REG_TOP, X86_REG_ST2, X86_REG_ST5}); EXPECT_JUST_REGISTERS_STORED({ + {X87_REG_TOP, 0x3}, {X86_REG_ST5, 3.14 + 3.14}, }); EXPECT_NO_MEMORY_LOADED_STORED();