{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":169344463,"defaultBranch":"master","name":"linux","ownerLogin":"atishp04","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2019-02-06T02:17:24.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/3942047?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1725912710.0","currentOid":""},"activityList":{"items":[{"before":null,"after":"d975d1fc71375296874c62007464dd2a87b861af","ref":"refs/heads/gtmb_rfc_poc","pushedAt":"2024-09-09T20:11:50.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"drivers/irqchip: Add GTMB driver for GSI based ACPI devices\n\nThe GTMB driver acts as the GSI-to-MSI bridge for any MSI capable device\nthat uses GSI infrastructure in ACPI. One of the example is the GED device\nwhich can be used on platforms without a centralized IRQ-to-MSI bridge.\nThe GTMB device will become the parent IRQ domain for the GED device\ninterrupt.\n\nCurrently, it only implements the generic registers and System\nmemory as the address space type. Currently, it doesn't support\nother address space type but can be easily extended to support it.\n\nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"drivers/irqchip: Add GTMB driver for GSI based ACPI devices"}},{"before":null,"after":"c92fccb382c80a3ec07739ef15115ebd91349867","ref":"refs/heads/smmc_rfc_poc","pushedAt":"2024-08-22T18:38:02.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"Add SMMC driver for MSI only platforms with gas structure\n\nThe draft specification has opens about types of interrupts\nsupported. irq_type callback can be used to validate the types\nof interrupt support. If there is additional registers are defined\nfor level triggered interrupts, end of IRQ callback can be added.\n\nThe SMMC driver only implements the generic registers and System\nmemory as the address space type. Currently, it doesn't support\nother address space type but can be easily extended to support it.\n\nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"Add SMMC driver for MSI only platforms with gas structure"}},{"before":"71d75026a6a4bb8210c242fbb49f5b8da1861f69","after":"7c313ded7ebcafdfdd7760200cc9d4add51916d9","ref":"refs/heads/b4/counter_delegation","pushedAt":"2024-07-24T00:13:18.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"Revert \"Revert \"perf parse-events: Prefer sysfs/JSON hardware events over legacy\"\"\n\nThis reverts commit 4f1b067359ac8364cdb7f9fda41085fa85789d0f.","shortMessageHtmlLink":"Revert \"Revert \"perf parse-events: Prefer sysfs/JSON hardware events …"}},{"before":null,"after":"71d75026a6a4bb8210c242fbb49f5b8da1861f69","ref":"refs/heads/b4/counter_delegation","pushedAt":"2024-07-15T23:23:36.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"Revert \"Revert \"perf parse-events: Prefer sysfs/JSON hardware events over legacy\"\"\n\nThis reverts commit 4f1b067359ac8364cdb7f9fda41085fa85789d0f.","shortMessageHtmlLink":"Revert \"Revert \"perf parse-events: Prefer sysfs/JSON hardware events …"}},{"before":null,"after":"6b7da00ff51b2c664e823ab852892f2133bcabde","ref":"refs/heads/smmc_crs_pkg_rfc","pushedAt":"2024-07-12T22:35:58.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"Add SMMC driver for MSI only platforms with _DSM approach\n\nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"Add SMMC driver for MSI only platforms with _DSM approach"}},{"before":"a686c1670740ccecdfef3498977e02701e6e40cb","after":"99e4124efc4c4a54fed32c1e8f883aeaaa2c9183","ref":"refs/heads/smmc_working_rfc","pushedAt":"2024-07-12T22:22:36.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"Add SMMC driver for MSI only platforms with _DSM approach\n\nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"Add SMMC driver for MSI only platforms with _DSM approach"}},{"before":"861a4cfcde316ca47191248df6545397c03da50f","after":"a686c1670740ccecdfef3498977e02701e6e40cb","ref":"refs/heads/smmc_working_rfc","pushedAt":"2024-07-12T22:20:10.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"Add SMMC driver for MSI only platforms\n\nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"Add SMMC driver for MSI only platforms"}},{"before":null,"after":"861a4cfcde316ca47191248df6545397c03da50f","ref":"refs/heads/smmc_working_rfc","pushedAt":"2024-07-09T22:03:28.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"Add SMMC driver for MSI only platforms\n\nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"Add SMMC driver for MSI only platforms"}},{"before":null,"after":"c5f4dcedbb148c0b500d39f8387e4488af669c4c","ref":"refs/heads/smmc_working_package","pushedAt":"2024-07-03T09:22:57.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"Add SMMC driver package based.\n\nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"Add SMMC driver package based."}},{"before":"14ab3ca0ca3026c1eb33cf09871269cb9170ffb1","after":"f67739f4cd206e88f8ea82f5ba51ac08fa30c80c","ref":"refs/heads/kvm_riscv_qeueu_fixes","pushedAt":"2024-04-25T21:23:24.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"drivers/perf: riscv: Fix RV32 snapshot overflow use case\n\nThe shadow copy alogirthm is implemented incorrectly. This patch fixes\nthe behavior by keeping a per cpu shadow copy of the counter values to\navoid clobbering for the cases where system more than XLEN counters and\nthe overflown counter index are beyond XLEN. This issue can only be\nobserved only in RV32 if an SBI implementation assigns logical counters\nids greater than XLEN or firmware counter overflow is supported in the\nfuture.\n\nFixes: 22f5dac41004d (\"drivers/perf: riscv: Implement SBI PMU snapshot function\")\n\nReviewed-by: Samuel Holland \nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"drivers/perf: riscv: Fix RV32 snapshot overflow use case"}},{"before":null,"after":"14ab3ca0ca3026c1eb33cf09871269cb9170ffb1","ref":"refs/heads/kvm_riscv_qeueu_fixes","pushedAt":"2024-04-25T19:01:50.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"drivers/perf: riscv: Fix RV32 snapshot overflow use case\n\nThe shadow copy alogirthm is implemented incorrectly. This patch fixes\nthe behavior by keeping a per cpu shadow copy of the counter values to\navoid clobbering for the cases where system more than XLEN counters and\nthe overflown counter index are beyond XLEN. This issue can only be\nobserved only in RV32 if an SBI implementation assigns logical counters\nids greater than XLEN or firmware counter overflow is supported in the\nfuture.\n\nFixes : commit 22f5dac41004d (\"drivers/perf: riscv: Implement SBI PMU snapshot function\")\n\nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"drivers/perf: riscv: Fix RV32 snapshot overflow use case"}},{"before":"3225e603f06832f9887bf19a14fd72f353eb1ddb","after":"c4ed8ec675bff78acb924d9698474d7b4bbb9997","ref":"refs/heads/kvm_pmu_snapshot_v9","pushedAt":"2024-04-25T06:19:13.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"drivers/perf: riscv: Fix RV32 snapshot overflow use case\n\nThe shadow copy alogirthm is incorrect. This patch fixes the behavior\nby keeping a global shadow copy of the counter values to avoid clobbering\nfor the cases where system more than XLEN counters and the overflown\ncounter index are beyond XLEN. This can only happen only RV32 if an\nSBI implementation assigns logical counters ids greater than XLEN or\nfirmware counter overflow is supported in the future.\n\nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"drivers/perf: riscv: Fix RV32 snapshot overflow use case"}},{"before":"f82d1cbc5e8fc891cf0d73d1528969bcb468ec22","after":"3225e603f06832f9887bf19a14fd72f353eb1ddb","ref":"refs/heads/kvm_pmu_snapshot_v9","pushedAt":"2024-04-25T06:17:23.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"drivers/perf: riscv: Fix RV32 snapshot overflow use case\n\nThe shadow copy alogirthm is incorrect. This patch fixes the behavior\nby keeping a global shadow copy of the counter values to avoid clobbering\nfor the cases where system more than XLEN counters and the overflown\ncounter index are beyond XLEN. This can only happen only RV32 if an\nSBI implementation assigns logical counters ids greater than XLEN or\nfirmware counter overflow is supported in the future.\n\nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"drivers/perf: riscv: Fix RV32 snapshot overflow use case"}},{"before":"c2f6183bce83168bc9b74a296330e6e2de81e025","after":"d94f30d6081960e134091a6785115e86d0f84ef9","ref":"refs/heads/counter_delegation_v1_test","pushedAt":"2024-04-24T23:30:15.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"TEMP Fix for arch statndard event\n\nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"TEMP Fix for arch statndard event"}},{"before":"86d353b91dcbac62b61202cdafcee43a2d017fe9","after":"f82d1cbc5e8fc891cf0d73d1528969bcb468ec22","ref":"refs/heads/kvm_pmu_snapshot_v9","pushedAt":"2024-04-24T18:38:10.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"drivers/perf: riscv: Fix RV32 snapshot overflow use case\n\nThe shadow copy alogirthm is incorrect. This patch fixes the behavior\nby keeping a global shadow copy of the counter values to avoid clobbering\nfor the cases where system more than XLEN counters and the overflown\ncounter index are beyond XLEN. This can only happen only RV32 if an\nSBI implementation assigns logical counters ids greater than XLEN or\nfirmware counter overflow is supported in the future.\n\nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"drivers/perf: riscv: Fix RV32 snapshot overflow use case"}},{"before":null,"after":"86d353b91dcbac62b61202cdafcee43a2d017fe9","ref":"refs/heads/kvm_pmu_snapshot_v9","pushedAt":"2024-04-24T07:15:01.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"drivers/perf: riscv: Remove the warning from stop function\n\nThe warning messsage was initially added just to indicate that counter\nstop function is being called while the event is already stopped.\n\nHowever, we update the state to stopped case now in an overflow handler\nafter stopping the counter. If there is another child overflow handler\nis registered (e.g kvm) it may call stop again which will trigger the\nwarning.\n\nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"drivers/perf: riscv: Remove the warning from stop function"}},{"before":null,"after":"c2f6183bce83168bc9b74a296330e6e2de81e025","ref":"refs/heads/counter_delegation_v1_test","pushedAt":"2024-04-23T09:03:52.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"TEMP Fix for arch statndard event\n\nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"TEMP Fix for arch statndard event"}},{"before":"d870aeeed9ac45a7623ee6fec0cf0f1bf4e6d37b","after":"e40a33e8510ef43cb97ad253541f624f2d886b1d","ref":"refs/heads/kvm_pmu_snapshot_v8","pushedAt":"2024-04-19T23:47:09.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"KVM: riscv: selftests: Add commandline option for SBI PMU test\n\nSBI PMU test comprises of multiple tests and user may want to run\nonly a subset depending on the platform. The most common case would\nbe to run all to validate all the tests. However, some platform may\nnot support all events or all ISA extensions.\n\nThe commandline option allows user to disable any set of tests if\nthey want to.\n\nSuggested-by: Andrew Jones \nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"KVM: riscv: selftests: Add commandline option for SBI PMU test"}},{"before":"ce2d510fbad15db88ea2c5e4912963151fe95ef4","after":"d870aeeed9ac45a7623ee6fec0cf0f1bf4e6d37b","ref":"refs/heads/kvm_pmu_snapshot_v8","pushedAt":"2024-04-19T23:42:00.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"KVM: riscv: selftests: Add commandline option for SBI PMU test\n\nSBI PMU test comprises of multiple tests and user may want to run\nonly a subset depending on the platform. The most common case would\nbe to run all to validate all the tests. However, some platform may\nnot support all events or all ISA extensions.\n\nThe commandline option allows user to disable any set of tests if\nthey want to.\n\nSuggested-by: Andrew Jones \nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"KVM: riscv: selftests: Add commandline option for SBI PMU test"}},{"before":null,"after":"ce2d510fbad15db88ea2c5e4912963151fe95ef4","ref":"refs/heads/kvm_pmu_snapshot_v8","pushedAt":"2024-04-19T23:38:24.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"KVM: riscv: selftests: Add commandline option for SBI PMU test\n\nSBI PMU test comprises of multiple tests and user may want to run\nonly a subset depending on the platform. The most common case would\nbe to run all to validate all the tests. However, some platform may\nnot support all events or all ISA extensions.\n\nThe commandline option allows user to disable any set of tests if\nthey want to.\n\nSuggested-by: Andrew Jones \nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"KVM: riscv: selftests: Add commandline option for SBI PMU test"}},{"before":"a0e83e0629f40f5e1db095cd63f878a4f580b419","after":"e9e030edde3dce53119dca60d159f77c1136cbb2","ref":"refs/heads/kvm_pmu_snapshot_v7","pushedAt":"2024-04-16T18:42:18.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"KVM: riscv: selftests: Add commandline option for SBI PMU test\n\nSBI PMU test comprises of multiple tests and user may want to run\nonly a subset depending on the platform. The most common case would\nbe to run all to validate all the tests. However, some platform may\nnot support all events or all ISA extensions.\n\nThe commandline option allows user to disable any set of tests if\nthey want to.\n\nSuggested-by: Andrew Jones \nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"KVM: riscv: selftests: Add commandline option for SBI PMU test"}},{"before":"b86257f92f25f1e65b8b8e18c9c3f4254b75e272","after":"a0e83e0629f40f5e1db095cd63f878a4f580b419","ref":"refs/heads/kvm_pmu_snapshot_v7","pushedAt":"2024-04-16T08:52:48.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"KVM: riscv: selftests: Add commandline option for SBI PMU test\n\nSBI PMU test comprises of multiple tests and user may want to run\nonly a subset depending on the platform. The most common case would\nbe to run all to validate all the tests. However, some platform may\nnot support all events or all ISA extensions.\n\nThe commandline option allows user to disable any set of tests if\nthey want to.\n\nSuggested-by: Andrew Jones \nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"KVM: riscv: selftests: Add commandline option for SBI PMU test"}},{"before":null,"after":"b86257f92f25f1e65b8b8e18c9c3f4254b75e272","ref":"refs/heads/kvm_pmu_snapshot_v7","pushedAt":"2024-04-16T08:51:01.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"KVM: riscv: selftests: Add commandline option for SBI PMU test\n\nSBI PMU test comprises of multiple tests and user may want to run\nonly a subset depending on the platform. The most common case would\nbe to run all to validate all the tests. However, some platform may\nnot support all events or all ISA extensions.\n\nThe commandline option allows user to disable any set of tests if\nthey want to.\n\nSuggested-by: Andrew Jones \nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"KVM: riscv: selftests: Add commandline option for SBI PMU test"}},{"before":"62855011bb1d32c838df99745e4a8f805df9ee54","after":"9c7c54505e98040f81e9d17d038102dbc917efe0","ref":"refs/heads/kvm_pmu_snapshot_v6","pushedAt":"2024-04-11T00:06:57.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"KVM: riscv: selftests: Add commandline option for SBI PMU test\n\nSBI PMU test comprises of multiple tests and user may want to run\nonly a subset depending on the platform. The most common case would\nbe to run all to validate all the tests. However, some platform may\nnot support all events or all ISA extensions.\n\nThe commandline option allows user to disable particular test if they\nwant to.\n\nSuggested-by: Andrew Jones \nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"KVM: riscv: selftests: Add commandline option for SBI PMU test"}},{"before":null,"after":"62855011bb1d32c838df99745e4a8f805df9ee54","ref":"refs/heads/kvm_pmu_snapshot_v6","pushedAt":"2024-04-10T23:02:35.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"KVM: riscv: selftests: Add commandline option for SBI PMU test\n\nSBI PMU test comprises of multiple tests and user may want to run\nonly a subset depending on the platform. The most common case would\nbe to run all to validate all the tests. However, some platform may\nnot support all events or all ISA extensions.\n\nThe commandline option allows user to disable particular test if they\nwant to.\n\nSuggested-by: Andrew Jones \nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"KVM: riscv: selftests: Add commandline option for SBI PMU test"}},{"before":"b871b2a0cfeeff1365e9f409c9f27403bf0dbd39","after":"ff3717e4bcbe1a872c07226a15f7ef4d487b1fc7","ref":"refs/heads/kvm_pmu_snapshot_v5","pushedAt":"2024-04-03T07:58:46.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"KVM: riscv: selftests: Add a test for counter overflow\n\nAdd a test for verifying overflow interrupt. Currently, it relies on\noverflow support on cycle/instret events. This test works for cycle/\ninstret events which support sampling via hpmcounters on the platform.\nThere are no ISA extensions to detect if a platform supports that. Thus,\nthis test will fail on platform with virtualization but doesn't\nsupport overflow on these two events.\n\nReviewed-by: Anup Patel \nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"KVM: riscv: selftests: Add a test for counter overflow"}},{"before":"850587ef4c5f75754ad46f792eb4bc60b7e19b7b","after":"b871b2a0cfeeff1365e9f409c9f27403bf0dbd39","ref":"refs/heads/kvm_pmu_snapshot_v5","pushedAt":"2024-04-03T07:05:48.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"KVM: riscv: selftests: Add a test for counter overflow\n\nAdd a test for verifying overflow interrupt. Currently, it relies on\noverflow support on cycle/instret events. This test works for cycle/\ninstret events which support sampling via hpmcounters on the platform.\nThere are no ISA extensions to detect if a platform supports that. Thus,\nthis test will fail on platform with virtualization but doesn't\nsupport overflow on these two events.\n\nReviewed-by: Anup Patel \nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"KVM: riscv: selftests: Add a test for counter overflow"}},{"before":"cdddc91e3f95ed945d275254a88f64fc64b62f96","after":"850587ef4c5f75754ad46f792eb4bc60b7e19b7b","ref":"refs/heads/kvm_pmu_snapshot_v5","pushedAt":"2024-04-02T23:55:08.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"KVM: riscv: selftests: Add a test for counter overflow\n\nAdd a test for verifying overflow interrupt. Currently, it relies on\noverflow support on cycle/instret events. This test works for cycle/\ninstret events which support sampling via hpmcounters on the platform.\nThere are no ISA extensions to detect if a platform supports that. Thus,\nthis test will fail on platform with virtualization but doesn't\nsupport overflow on these two events.\n\nReviewed-by: Anup Patel \nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"KVM: riscv: selftests: Add a test for counter overflow"}},{"before":"b0e65c6b9040f92d37b78f24aab4948fd3f26bf8","after":"cdddc91e3f95ed945d275254a88f64fc64b62f96","ref":"refs/heads/kvm_pmu_snapshot_v5","pushedAt":"2024-04-02T21:17:44.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"KVM: riscv: selftests: Add a test for counter overflow\n\nAdd a test for verifying overflow interrupt. Currently, it relies on\noverflow support on cycle/instret events. This test works for cycle/\ninstret events which support sampling via hpmcounters on the platform.\nThere are no ISA extensions to detect if a platform supports that. Thus,\nthis test will fail on platform with virtualization but doesn't\nsupport overflow on these two events.\n\nReviewed-by: Anup Patel \nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"KVM: riscv: selftests: Add a test for counter overflow"}},{"before":"653a580a4c547726973fe1c7518fcd03edb37402","after":"b0e65c6b9040f92d37b78f24aab4948fd3f26bf8","ref":"refs/heads/kvm_pmu_snapshot_v5","pushedAt":"2024-04-02T09:15:16.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"atishp04","name":"Atish Patra","path":"/atishp04","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/3942047?s=80&v=4"},"commit":{"message":"KVM: riscv: selftests: Add a test for counter overflow\n\nAdd a test for verifying overflow interrupt. Currently, it relies on\noverflow support on cycle/instret events. This test works for cycle/\ninstret events which support sampling via hpmcounters on the platform.\nThere are no ISA extensions to detect if a platform supports that. Thus,\nthis test will fail on platform with virtualization but doesn't\nsupport overflow on these two events.\n\nReviewed-by: Anup Patel \nSigned-off-by: Atish Patra ","shortMessageHtmlLink":"KVM: riscv: selftests: Add a test for counter overflow"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"startCursor":"Y3Vyc29yOnYyOpK7MjAyNC0wOS0wOVQyMDoxMTo1MC4wMDAwMDBazwAAAASxUXeQ","endCursor":"Y3Vyc29yOnYyOpK7MjAyNC0wNC0wMlQwOToxNToxNi4wMDAwMDBazwAAAAQlUbCR"}},"title":"Activity · atishp04/linux"}