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‎gateware/docs/_static/eurorack_pmod_bare_pcba_top.jpg

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‎gateware/docs/_static/soldiercrab.jpg

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‎gateware/docs/_static/tiliqua_disassembled.png

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‎gateware/docs/_static/tiliqua_disassembled_top.jpg

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‎gateware/docs/_static/tiliqua_motherboard_without_som.jpg

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‎gateware/docs/blog/index.rst

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‎gateware/docs/blog/march_2025.rst

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‎gateware/docs/conf.py

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"sphinx.ext.doctest",
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"sphinx.ext.todo",
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"sphinx.ext.autodoc",
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"sphinx_rtd_theme",
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"sphinxcontrib.platformpicker",
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]
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"Platform overrides"
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]
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html_theme = "furo"
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html_theme = "sphinx_rtd_theme"
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html_static_path = ["_static"]
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html_css_files = ["custom.css"]
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html_logo = "_static/logo.png"
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html_logo = "_static/logo.jpg"
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rst_prolog = """
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.. role:: py(code)

‎gateware/docs/hardware.rst ‎gateware/docs/connections.rst

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Connecting Hardware
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###################
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Connections
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###########
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Connections: Front
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------------------

‎gateware/docs/dsp/index.rst

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TODO link to Amaranth documentation on streams.
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.. image:: _static/mydsp.png
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.. image:: /_static/mydsp.png
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:width: 800
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Components

‎gateware/docs/technical.rst ‎gateware/docs/hardware_changes.rst

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Hardware details
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################
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Changelist
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##########
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.. image:: _static/tiliqua_disassembled.png
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:width: 800
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There were some Tiliqua hardware released before the production R4 version. This page serves as a brief history of the differences between these versions, as well as any changes in post-production batches.
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Schematics and PCBAs
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--------------------
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Tiliqua R4
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==========
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**Schematics for all Tiliqua revisions in the wild can be found :** `here <https://github.com/apfaudio/tiliqua/tree/main/hardware/schematics>`_
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First production hardware release.
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Tiliqua consists of 3 main PCBAs. All of these are open-hardware designs built in KiCAD and stored in separate repositories.
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Motherboard (and front panel)
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-----------------------------
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**Repository:** `tiliqua-motherboard <https://github.com/apfaudio/tiliqua/tree/main/hardware>`_
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- Switched rotary encoder with bar graph display.
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- Dual USB ports:
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- `dbg`: Included RP2040-based JTAG debugger supported by `openFPGAloader`
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- `usb2`: USB PHY connected directly to FPGA for high-speed USB Audio support
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- Display output for video synthesis (maximum resolution 720/60P)
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- 2x expansion ports for up to 24 simultaneous audio channels (PMOD-compatible)
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- MIDI-In jack (TRS-A standard)
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Embedded FPGA SoM (`soldiercrab`)
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---------------------------------
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**Repository:** `soldiercrab <https://github.com/apfaudio/soldiercrab>`_
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- Lattice ECP5 FPGA, supported by open-source FPGA toolchains
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- 256 Mbit (32 MByte) HyperRAM / oSPI RAM (for long audio buffers or video framebuffers)
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- 128 Mbit (16 MByte) SPI flash for user bitstreams
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- High-speed USB HS PHY (ULPI)
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Audio Interface
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---------------
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- **SoldierCrab R3** FPGA SoM (LFE5U-25F, 1.8V 32MByte oSPIRAM)
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- **Tiliqua R4** motherboard and front panel.
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- **eurorack-pmod R3.3** audio interface.
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**Repository:** `eurorack-pmod <https://github.com/apfaudio/eurorack-pmod/tree/master/hardware>`_
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R4 changes (compared to R3)
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^^^^^^^^^^^^^^^^^^^
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- 8 (4 in + 4 out) DC-coupled audio channels, 192 KHz / 24-bit sampling supported
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- Touch and proximity sensing on all 8 audio jacks (if unused)
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- PWM-controlled, user-programmable red/green LEDs on each audio channel
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- Jack insertion detection on all 8 jacks
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- Add external PLL SI5351 and route 2x clocks to ECP5 (useful for EMC as it supports spread-spectrum, also for runtime clock/resolution switching).
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- Add series 27R/33R on all FFC lines to reduce radiated emissions.
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- Pinswaps to ensure external PLL is routed to true ECP5 clock input pins:
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- FFC_SDIN1: 44 -> 42
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- ENC_B: 40 -> 12
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- ENC_A: 42 -> 8
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- PLL_CLK1 -> 40 (removed: spare FPGA to RP2040 line)
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- PLL_CLK0 -> 44 (removed: spare FPGA to RP2040 line)
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- Route 4 new ex0/ex1 pins to RP2040 spare pins (shared with expansion connectors)
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- Swap RP2040 SPI flash for 128MBit part
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- Put spare RP2040 I2C pins on main tiliqua-mobo I2C bus.
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- Switch from 4L stackup to 6L stackup to improve SI/EMC.
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Hardware Revisions
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------------------
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Tiliqua R3
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==========
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There are a few Tiliqua hardware variants in existence:
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Another hardware revision that some beta testers have. Only 5 were produced.
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- **Tiliqua R2**
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- **SoldierCrab R2** FPGA SoM (LFE5U-45F, 3.3V 16MByte HyperRAM)
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- **Tiliqua R2** motherboard and front panel.
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- **eurorack-pmod R3.3** audio interface.
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- **Tiliqua R3**
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- **SoldierCrab R3** FPGA SoM (LFE5U-25F, 1.8V 32MByte oSPIRAM)
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- **Tiliqua R3** motherboard and front panel.
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- **eurorack-pmod R3.3** audio interface.
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- **Tiliqua R4** (unreleased)
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Hardware Changelist
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^^^^^^^^^^^^^^^^^^^
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- From **Tiliqua R2** to **Tiliqua R3**:
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R3 changes (compared to R2)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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- Pinswap all DVI pins to true ECP5 complementary pairs.
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- Swap all tantalums for ceramics, clean up PSU routing, swap LDO for TPS7A91, add choke input capacitors
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- Add 2x spare pins for RP2040/ECP5 I2C (no pullups)
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- Layerswap In1 / In2 (move GND closer to SMPS)
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- Add flip-flop on CODEC PDN pin (allows for soft-mute when swapping bitstreams)
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- From **Tiliqua R3** to **Tiliqua R4**:
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- Add external PLL SI5351 and route 2x clocks to ECP5 (useful for EMC as it supports spread-spectrum, also for runtime clock/resolution switching).
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- Add series 27R/33R on all FFC lines to reduce radiated emissions.
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- Pinswaps to ensure external PLL is routed to true ECP5 clock input pins:
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- FFC_SDIN1: 44 -> 42
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- ENC_B: 40 -> 12
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- ENC_A: 42 -> 8
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- PLL_CLK1 -> 40 (removed: spare FPGA to RP2040 line)
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- PLL_CLK0 -> 44 (removed: spare FPGA to RP2040 line)
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- Route 4 new ex0/ex1 pins to RP2040 spare pins (shared with expansion connectors)
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- Swap RP2040 SPI flash for 128MBit part
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- Put spare RP2040 I2C pins on main tiliqua-mobo I2C bus.
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- Switch from 4L stackup to 6L stackup to improve SI/EMC.
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Tiliqua R2
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==========
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This was the first hardware revision that some beta testers have. Only 5 were produced.
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- **SoldierCrab R2** FPGA SoM (LFE5U-45F, 3.3V 16MByte HyperRAM)
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- **Tiliqua R2** motherboard and front panel.
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- **eurorack-pmod R3.3** audio interface.
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Tiliqua R1
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==========
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This prototype was shown at SuperBooth 2024. It was never shipped to anyone.
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- **SoldierCrab R1** FPGA SoM (LFE5U-45F, 3.3V 16MByte HyperRAM, no USB2 PHY)
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- **Tiliqua R1** motherboard and front panel.
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- **eurorack-pmod R3.3** audio interface.
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‎gateware/docs/hardware_design.rst

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Electrical Design
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#################
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Tiliqua consists of 3 PCBAs. All of these are open-hardware designs built in KiCAD and stored in separate repositories. **Schematics for all Tiliqua revisions in the wild are plotted to PDFs** `here <https://github.com/apfaudio/tiliqua/tree/main/hardware/schematics>`_.
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Block Diagram (Tiliqua R4)
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--------------------------
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Below is high-level picture of how all the different electrical components of Tiliqua are connected.
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.. image:: _static/tiliqua-block-diagram.svg
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:width: 800
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Some connections are omitted for simplicity (example: some ex0/ex1 pins are connected to both the ECP5 and RP2040, not shown).
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We now follow with a summary of the core functions of each of the Tiliqua PCBAs.
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Tiliqua Motherboard
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-------------------
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**Repository:** `tiliqua-motherboard <https://github.com/apfaudio/tiliqua/tree/main/hardware>`_
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.. image:: _static/tiliqua_motherboard_without_som.jpg
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:width: 800
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- Rotary encoder with button and bar graph display.
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- RP2040-based JTAG debugger and UART bridge supported by `openFPGAloader`.
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- Two USB ports:
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- `dbg`: USB FS for JTAG debugging.
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- `usb2`: 480Mbit/sec USB HS PHY connected to FPGA. Device, host and dual-role operation is supported on this port with a dedicated TUSB322I CC control IC and +5V VBUS switch.
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- Display output for video synthesis
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- Maximum resolution 1280x720p/60Hz or 1920x1080p/30Hz.
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- 2x (PMOD-compatible) expansion ports for up to 24 simultaneous audio channels.
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- MIDI-In jack (TRS-A standard) with optoisolation.
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- External PLL (SI5351A) for dynamic display resolution switching.
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- Soft mute for pop-free bitstream switching
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FPGA SoM (`soldiercrab`)
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---------------------------------
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**Repository:** `soldiercrab <https://github.com/apfaudio/soldiercrab>`_ (see README there for more detailed docs on this SoM)
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.. image:: _static/soldiercrab.jpg
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:width: 800
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- Lattice ECP5 (25 K) FPGA, supported by open-source FPGA toolchains
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- 256 Mbit (32 MByte) HyperRAM / oSPI RAM (for long audio buffers or video framebuffers)
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- 128 Mbit (16 MByte) SPI flash for user bitstreams
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- High-speed USB HS PHY (ULPI)
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Audio Interface (`eurorack-pmod R3.3`)
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--------------------------------------
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**Repository:** `eurorack-pmod <https://github.com/apfaudio/eurorack-pmod/tree/master/hardware>`_
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.. image:: _static/eurorack_pmod_bare_pcba_top.jpg
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:width: 800
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- 8 (4 in + 4 out) DC-coupled audio channels, 192 KHz / 24-bit sampling
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- Touch and proximity sensing on all 8 audio jacks (if unused)
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- PWM-controlled, user-programmable red/green LEDs on each audio channel
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- Jack insertion detection on all 8 jacks
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- Built-in calibration EEPROM

‎gateware/docs/index.rst

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This manual is under construction and very incomplete!
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.. image:: _static/tiliqua_front_labelled.png
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.. image:: _static/tiliqua_disassembled_top.jpg
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:width: 800
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.. toctree::
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:caption: Hardware
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:maxdepth: 2
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connections
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hardware_design
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hardware_changes
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.. toctree::
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:caption: Building & Flashing
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:maxdepth: 3
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blog/index
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hardware
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technical
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install
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gettingstarted/index
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calibration
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bootloader
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dsp/index
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examples/index
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GitHub <https://github.com/apfaudio/tiliqua>
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Crowd Supply <https://www.crowdsupply.com/apfaudio/tiliqua>
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`apf.audio` homepage <https://apf.audio/>
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.. toctree::
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:caption: Reference
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:maxdepth: 3
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dsp/index
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.. toctree::
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:caption: Links
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:maxdepth: 2
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Tiliqua on Crowd Supply <https://www.crowdsupply.com/apfaudio/tiliqua>
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Tiliqua on GitHub <https://github.com/apfaudio/tiliqua>
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Homepage (apf.audio) <https://apf.audio/>

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