Renaming of "Cortex-M7 SIMD" in commens to DSP

* removed odd "micro_dev"
* fixes for instrinsics' functions comments

Author: ilyag-grovety

python/tvm/relay/op/strategy/arm_cpu.py

@@ -49,7 +49,7 @@ def schedule_concatenate_arm_cpu(_, outs, target):
         return topi.arm_cpu.schedule_concatenate(outs)
 
 
-@schedule_pool.register(["arm_cpu", "micro_dev"])
+@schedule_pool.register(["arm_cpu"])
 def schedule_pool_arm_cpu(attrs, outs, target):
     """schedule pooling ops arm cpu"""
     layout = attrs.layout
@@ -437,7 +437,7 @@ def schedule_bitserial_dense_arm_cpu(attrs, inputs, out_type, target):
     return strategy
 
 
-@dense_strategy.register(["arm_cpu", "micro_dev"])
+@dense_strategy.register(["arm_cpu"])
 def schedule_dense_arm_cpu(attrs, inputs, out_type, target):
     """dense arm cpu strategy"""
     strategy = _op.OpStrategy()
@@ -446,7 +446,7 @@ def schedule_dense_arm_cpu(attrs, inputs, out_type, target):
         strategy.add_implementation(
             wrap_compute_dense(topi.nn.dense),
             wrap_topi_schedule(topi.arm_cpu.schedule_dense_direct_simd),
-            name="dense_direct_simd.micro_dev",
+            name="dense_direct_simd",
         )
     else:
         strategy.add_implementation(
@@ -474,7 +474,7 @@ def conv1d_strategy_arm_cpu(attrs, inputs, out_type, target):
             strategy.add_implementation(
                 wrap_compute_conv1d(topi.arm_cpu.conv1d_nwc_direct_simd),
                 wrap_topi_schedule(topi.arm_cpu.schedule_conv1d_nwc_direct_simd),
-                name="conv1d_direct_simd.micro_dev",
+                name="conv1d_direct_simd",
             )
         else:
             raise RuntimeError(

python/tvm/topi/arm_cpu/conv1d.py

@@ -20,17 +20,17 @@
 
 from tvm import autotvm
 
-from .cortex_m7.conv1d import direct_simd as direct_simd_conv1d
+from .cortex_m7.conv1d import direct_simd
 
 
 @autotvm.register_topi_compute("conv1d_nwc_direct_simd.arm_cpu")
 def conv1d_nwc_direct_simd(cfg, data, kernel, strides, padding, dilation, out_dtype):
-    """Compute conv1d with SIMD (v7e-m)."""
-    return direct_simd_conv1d.conv1d_nwc_direct_simd_compute(
+    """Compute conv1d with v7e-m DSP instructions."""
+    return direct_simd.conv1d_nwc_direct_simd_compute(
         cfg, data, kernel, strides, padding, dilation, out_dtype
     )
 
 
 @autotvm.register_topi_schedule("conv1d_nwc_direct_simd.arm_cpu")
 def schedule_conv1d_nwc_direct_simd(cfg, outs):
-    return direct_simd_conv1d.conv1d_nwc_direct_simd_schedule(cfg, outs)
+    return direct_simd.conv1d_nwc_direct_simd_schedule(cfg, outs)

python/tvm/topi/arm_cpu/conv2d.py

@@ -507,7 +507,7 @@ def _callback(op):
 
 @autotvm.register_topi_compute("conv2d_nhwc_direct_simd.arm_cpu")
 def conv2d_nhwc_direct_simd(cfg, data, kernel, strides, padding, dilation, out_dtype):
-    """Compute conv2d_nhwc with SIMD (v7e-m)."""
+    """Compute conv2d_nhwc with v7e-m DSP instructions."""
     return direct_simd.conv2d_nhwc_direct_simd_compute(
         cfg, data, kernel, strides, padding, dilation, out_dtype
     )

python/tvm/topi/arm_cpu/cortex_m7/__init__.py

@@ -14,7 +14,7 @@
 # KIND, either express or implied.  See the License for the
 # specific language governing permissions and limitations
 # under the License.
-"""Schedules specialized for cortex-m7."""
+"""Schedules specialized for v7e-m DSP instructions."""
 
 
 from . import conv2d

python/tvm/topi/arm_cpu/cortex_m7/conv1d/__init__.py

@@ -14,6 +14,6 @@
 # KIND, either express or implied.  See the License for the
 # specific language governing permissions and limitations
 # under the License.
-"""Conv1d implementations for cortex-m7."""
+"""Conv1d implementations for v7e-m DSP instructions."""
 
 from . import direct_simd

python/tvm/topi/arm_cpu/cortex_m7/conv1d/direct_simd.py

@@ -31,7 +31,7 @@
 
 
 def conv1d_nwc_direct_simd(*args, **kwargs):
-    """Defines the Cortex-M7 SIMD implementation of conv1d on NWC layout."""
+    """Defines the v7e-m DSP instructions of conv1d on NWC layout."""
     assert not kwargs, "Do not support kwargs in template function call"
     args = deserialize_args(args)
     data, kernel = args[:2]
@@ -50,7 +50,7 @@ def conv1d_nwc_direct_simd(*args, **kwargs):
 
 
 def conv1d_nwc_direct_simd_compute(cfg, data, kernel, strides, padding, dilation, out_dtype):
-    """Compute function for Cortex-M7 SIMD implementation of conv1d on NWC layout."""
+    """Compute function for v7e-m DSP instructions of conv1d on NWC layout."""
     if isinstance(strides, (tuple, list)):
         strides = strides[0]
     if isinstance(dilation, (tuple, list)):
@@ -133,7 +133,7 @@ def conv1d_nwc_direct_simd_compute(cfg, data, kernel, strides, padding, dilation
 
 
 def conv1d_nwc_direct_simd_schedule(cfg, outs):
-    """Schedule function for Cortex-M7 SIMD implementation of conv1d on NWC layout."""
+    """Schedule function for v7e-m DSP instructions of conv1d on NWC layout."""
     sched = te.create_schedule([x.op for x in outs])
 
     def _callback(op):

python/tvm/topi/arm_cpu/cortex_m7/conv2d/__init__.py

@@ -14,6 +14,6 @@
 # KIND, either express or implied.  See the License for the
 # specific language governing permissions and limitations
 # under the License.
-"""Conv2d implementations for cortex-m7."""
+"""Conv2d implementations for v7e-m DSP instructions."""
 
 from . import direct_simd

python/tvm/topi/arm_cpu/cortex_m7/conv2d/direct_simd.py

@@ -32,7 +32,7 @@
 
 
 def conv2d_nhwc_direct_simd(*args, **kwargs):
-    """Defines the Cortex-M7 SIMD implementation of conv2d."""
+    """Defines the v7e-m DSP instructions of conv2d."""
     assert not kwargs, "Do not support kwargs in template function call"
     args = deserialize_args(args)
     data, kernel = args[:2]
@@ -51,7 +51,7 @@ def conv2d_nhwc_direct_simd(*args, **kwargs):
 
 
 def conv2d_nhwc_direct_simd_compute(cfg, data, kernel, strides, padding, dilation, out_dtype):
-    """Compute function for Cortex-M7 SIMD implementation of conv2d."""
+    """Compute function for v7e-m DSP instructions of conv2d."""
     assert isinstance(strides, int) or len(strides) == 2
     assert isinstance(dilation, int) or len(dilation) == 2
 
@@ -148,7 +148,7 @@ def conv2d_nhwc_direct_simd_compute(cfg, data, kernel, strides, padding, dilatio
 
 
 def conv2d_nhwc_direct_simd_schedule(cfg, outs):
-    """Schedule function for Cortex-M7 SIMD implementation of conv2d."""
+    """Schedule function for v7e-m DSP instructions of conv2d."""
     sched = te.create_schedule([x.op for x in outs])
 
     def _callback(op):

python/tvm/topi/arm_cpu/cortex_m7/dense/__init__.py

@@ -14,6 +14,6 @@
 # KIND, either express or implied.  See the License for the
 # specific language governing permissions and limitations
 # under the License.
-"""Dense implementations for cortex-m7."""
+"""Dense implementations for v7e-m DSP instructions."""
 
 from . import direct_simd

python/tvm/topi/arm_cpu/cortex_m7/dense/direct_simd.py

@@ -27,7 +27,7 @@
 
 
 def dense_direct_simd_schedule(outs):
-    """Schedule function for Cortex-M7 SIMD implementation of dense."""
+    """Schedule function for v7e-m DSP instructions of dense."""
     sched = te.create_schedule([x.op for x in outs])
 
     def _callback(op):