1919import os
2020import sys
2121import subprocess as sp
22+ import json
2223
2324import tvm
2425from tvm import relay
@@ -48,6 +49,10 @@ def _func_wrapper(expr):
4849 return _func_wrapper
4950
5051
52+ _register_verilator_op ("add" )
53+ _register_verilator_op ("nn.bias_add" )
54+
55+
5156def skip_test ():
5257 """Skip test if it requires the Verilator codegen and it's not present."""
5358 if not tvm .get_global_func ("relay.ext.verilator" , True ):
@@ -59,8 +64,33 @@ def skip_test():
5964 return False
6065
6166
67+ def clear_stats ():
68+ """Clear profiler statistics."""
69+ f = tvm .get_global_func ("verilator.profiler_clear" , True )
70+ if f :
71+ f ()
72+
73+
74+ def stats ():
75+ """Get profiler statistics."""
76+
77+ x = tvm .get_global_func ("verilator.profiler_status" )()
78+ return json .loads (x )
79+
80+
6281def offload (mod ):
63- """Offload ops based on the registered ops"""
82+ """Offload ops based on the registered ops
83+
84+ Paramters
85+ ---------
86+ mod : Module
87+ The input module.
88+
89+ Returns
90+ -------
91+ mod : Module
92+ The output module with offloaded ops.
93+ """
6494
6595 backend = "verilator"
6696 mod = transform .AnnotateTarget ([backend ])(mod )
@@ -69,7 +99,7 @@ def offload(mod):
6999
70100
71101def verilator_app_path ():
72- """Find verilator hardware app path"""
102+ """Create verilator hardware app path. """
73103
74104 cur_dir = os .path .dirname (os .path .realpath (__file__ ))
75105 return os .path .join (
@@ -82,37 +112,87 @@ def verilator_app_path():
82112 "vta-hw" ,
83113 "apps" ,
84114 "verilator" ,
115+ "add" ,
85116 )
86117
87118
88- def compile_hardware ():
89- """Compile hardware into shared library"""
119+ def compile_hardware (lanes ):
120+ """Compile hardware into shared library
121+
122+ Paramters
123+ ---------
124+ lanes : Int
125+ The number of vector lanes.
126+
127+ Returns
128+ -------
129+ path : Str
130+ The path of the shared library.
131+ """
132+ lib_name = "libverilator_{}" .format (lanes )
133+ lib_name_ext = "{}.so" .format (lib_name )
134+ lib = os .path .join (verilator_app_path (), lib_name_ext )
135+ if not os .path .isfile (lib ):
136+ opt_lib_name = "LIB_NAME={}" .format (lib_name )
137+ opt_lanes = "LANES={}" .format (lanes )
138+ cmd = []
139+ cmd .append ("make" )
140+ cmd .append ("--directory" )
141+ cmd .append (verilator_app_path ())
142+ cmd .append (opt_lib_name )
143+ cmd .append (opt_lanes )
144+ sp .run (cmd , check = True , stdout = sp .DEVNULL )
145+ return lib
146+
90147
91- cmd = []
92- cmd .append ("make" )
93- cmd .append ("--directory" )
94- cmd .append (verilator_app_path ())
95- sp .run (cmd , check = True )
148+ def compiler_opts (lib ):
149+ """Create compiler options
96150
151+ Paramters
152+ ---------
153+ lib : Str
154+ The path of the hardware shared library.
97155
98- def compile_module (mod ):
99- """Compile Relay module and hardware library"""
156+ Returns
157+ -------
158+ opts : Dict
159+ The compiler options.
160+ """
161+ opts = {
162+ "lib_path" : lib ,
163+ "profiler_enable" : True ,
164+ "profiler_cycle_counter_id" : 0 ,
165+ }
166+ return opts
100167
101- lib = os .path .join (verilator_app_path (), "libverilator.so" )
102- if not os .path .isfile (lib ):
103- compile_hardware ()
104168
105- opts = {"lib_path" : lib }
169+ def run_module (inp , mod , params = None , opts = None ):
170+ """Compile Relay module and hardware library
106171
107- with tvm . transform . PassContext ( opt_level = 3 , config = { "relay.ext.verilator.options" : opts }):
108- exe = relay . vm . compile ( mod , target = "llvm" , params = None )
109- code , lib = exe . save ()
110- return runtime . vm . Executable . load_exec ( code , lib )
172+ Paramters
173+ ---------
174+ inp : Data
175+ The input data.
111176
177+ mod : Module
178+ The relay module.
112179
113- def run_module ( exe , inputs ):
114- """Run Relay module"""
180+ params : Parameters
181+ The model Parameters.
115182
116- dev = tvm .cpu ()
117- vm = runtime .vm .VirtualMachine (exe , dev )
118- return vm .run (** inputs )
183+ opts : Dict
184+ The compiler
185+
186+ Returns
187+ -------
188+ out : Data
189+ The output data.
190+ """
191+
192+ with tvm .transform .PassContext (opt_level = 3 , config = {"relay.ext.verilator.options" : opts }):
193+ lib = relay .vm .compile (mod , target = "llvm" , params = params )
194+ code , lib = lib .save ()
195+ exe = runtime .vm .Executable .load_exec (code , lib )
196+ vm = runtime .vm .VirtualMachine (exe , tvm .cpu ())
197+ out = vm .run (** inp )
198+ return out
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