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[Relay] Legalize pass #3672
[Relay] Legalize pass #3672
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src/relay/pass/rewrite_op.cc
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// Returns the altered expression | ||
Expr OpRewriter(const Call &ref_call, | ||
const Array<Expr> &new_args, | ||
const NodeRef& ctx) { |
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align indent
src/relay/pass/rewrite_op.cc
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if (fop_rewrite.count(op)) { | ||
tvm::Array<tvm::Tensor> tinfos; | ||
for (auto expr : ref_call->args) { | ||
auto ttype = expr->type_as<TensorTypeNode>(); |
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it could be TupleTypeNode
src/relay/pass/rewrite_op.cc
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bool modified = false; | ||
if (fop_rewrite.count(op)) { | ||
tvm::Array<tvm::Tensor> tinfos; | ||
for (auto expr : ref_call->args) { |
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for (auto expr : ref_call->args) { | |
for (auto& expr : ref_call->args) { |
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This pass transforms an expression to other expression. This pass has many usecases * Replace a expr to another expr, if the other expr has faster performance. * For ASICs, we might want to modify the inputs to adapt to the HW support. * Alter op layout can work in conjunction with this pass. The supporting usecase is the Intel i8 x i8 conv. Intel HW supports u8 x i8 conv in HW. Using this pass, we can replace an i8 x i8 conv to a sequence of operators where one of the operators is now u8 x i8 conv. This will also help automatic quantizaion performance.
Let us debate on the name of the pass. Rewrite is a too generic. @FrozenGene @yzhliu @merrymercy @jroesch any thoughts? |
How about Strength Reduction? Not sure. But the idea is to replace one expr with other expr with the goal that it will make it faster. On the other hand, Strength Reduction might sound target agnostic, but this one is not. |
yeah, I also think |
Let us call it Legalize, as per LLVM terminology. https://wiki.aalto.fi/display/t1065450/LLVM+Legalization+and+Lowering The first step when to designing API is to check conventional APIs and try to make things as consistent as possible. |
Thanks for the pointers for considering APIs. I have changed the name to Legalize. Please review again. |
I will review the code tomorrow. Sorry for this. Because Monday is always very busy. :-( |
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LGTM. Some comments of code should be handled.
python/tvm/relay/transform.py
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@@ -435,6 +435,21 @@ def AlterOpLayout(): | |||
return _transform.AlterOpLayout() | |||
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def Legalize(): | |||
"""Rewrites a expression with another expression. |
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Maybe we should change Rewrites
to Legalize
# KIND, either express or implied. See the License for the | ||
# specific language governing permissions and limitations | ||
# under the License. | ||
"""Test alter op layout pass""" |
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Test legalize pass
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We can merge once @FrozenGene 's comments have been addressed.
Should we move the expansion of batch_norm op from simplify inference to legalize pass? |
I like it. This is a target-independent pass though (which is fine, if everybody agrees to it). Simplify_inference is anyways a vague name. From the name, it seems like something really big is happening inside :) But, I would suggest doing it in a separate PR to avoid complicating this PR, as it will likely involve the discussion of when we should call this pass. |
Thanks @anijain2305 @tqchen @FrozenGene @icemelon9 |
* [Relay] Rewrite pass. This pass transforms an expression to other expression. This pass has many usecases * Replace a expr to another expr, if the other expr has faster performance. * For ASICs, we might want to modify the inputs to adapt to the HW support. * Alter op layout can work in conjunction with this pass. The supporting usecase is the Intel i8 x i8 conv. Intel HW supports u8 x i8 conv in HW. Using this pass, we can replace an i8 x i8 conv to a sequence of operators where one of the operators is now u8 x i8 conv. This will also help automatic quantizaion performance. * Better API name. * Removing the conv2d legalization for x86. Will send a separate PR. * Test name changes. * Registering one funtion to register FTVMLegalize. * Better comments.
* [Relay] Rewrite pass. This pass transforms an expression to other expression. This pass has many usecases * Replace a expr to another expr, if the other expr has faster performance. * For ASICs, we might want to modify the inputs to adapt to the HW support. * Alter op layout can work in conjunction with this pass. The supporting usecase is the Intel i8 x i8 conv. Intel HW supports u8 x i8 conv in HW. Using this pass, we can replace an i8 x i8 conv to a sequence of operators where one of the operators is now u8 x i8 conv. This will also help automatic quantizaion performance. * Better API name. * Removing the conv2d legalization for x86. Will send a separate PR. * Test name changes. * Registering one funtion to register FTVMLegalize. * Better comments.
Relevant Issue - #3670
This pass transforms an expression to other expression.
This pass has many usecases
The supporting usecase is the Intel i8 x i8 conv. Intel HW supports u8 x i8 conv
in HW. Using this pass, we can replace an i8 x i8 conv to a sequence of
operators where one of the operators is now u8 x i8 conv.