[VTA] [Chisel] fix uop load request #3643
Merged
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Background
Currently, micro-operations
uop
in VTA are 32-bit wide, which is usually lower to the number of bits used by the memory bus. In order to take full advantage of memory bandwidth, micro-ops are loaded in memory burst and written touop
memory. The cost for this approach is aligning/masking the data to be written on SRAMs with the benefit of fully utilizing the bandwidth available.Bug
I recently found a bug when
uop
load-requests had an odd offset (SRAM) and even number ofuop
. This was causing the integration gemm testtest_benchmark_gemm.py
to fail. With this fix, VTA chisel is now passing the following tests (unit-tests, integration, and tutorial) except fordeploy_resnet_on_vta.py
Solution
Incorporate the offset into the calculation of the size of the dma request.