diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson index 8e8011af5fac4..e97c9997888b9 100644 --- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson +++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson @@ -82,6 +82,9 @@ } ] + // exclusion files + vcs_cov_excl_files: ["{proj_root}/hw/top_earlgrey/dv/cov/ast_mem_cfg.el"] + // Default iterations for all tests - each test entry can override this. reseed: 1 diff --git a/hw/top_earlgrey/dv/cov/ast_mem_cfg.el b/hw/top_earlgrey/dv/cov/ast_mem_cfg.el new file mode 100644 index 0000000000000..15a42ba905cea --- /dev/null +++ b/hw/top_earlgrey/dv/cov/ast_mem_cfg.el @@ -0,0 +1,154 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//================================================== +// This file contains the Excluded objects +// Generated By User: sriyer +// Format Version: 2 +// Date: Sat Oct 16 02:48:13 2021 +// ExclMode: default +//================================================== +CHECKSUM: "1907957879 976951533" +INSTANCE: tb.dut.u_ast +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle dpram_rmf_o.marg_a "logic dpram_rmf_o.marg_a[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle spram_rm_o.marg_en "logic spram_rm_o.marg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle spram_rm_o.marg "logic spram_rm_o.marg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle dpram_rml_o.marg_en_b "logic dpram_rml_o.marg_en_b" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle dpram_rml_o.marg_en_a "logic dpram_rml_o.marg_en_a" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle dpram_rml_o.marg_b "logic dpram_rml_o.marg_b[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle dpram_rml_o.marg_a "logic dpram_rml_o.marg_a[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle dpram_rmf_o.marg_en_b "logic dpram_rmf_o.marg_en_b" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle dpram_rmf_o.marg_en_a "logic dpram_rmf_o.marg_en_a" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle dpram_rmf_o.marg_b "logic dpram_rmf_o.marg_b[3:0]" +CHECKSUM: "135692598 2162367909" +INSTANCE: tb.dut.top_earlgrey.u_spi_device +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.a_ram_fcfg.cfg "logic ram_cfg_i.a_ram_fcfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.b_ram_lcfg.cfg_en "logic ram_cfg_i.b_ram_lcfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.b_ram_lcfg.cfg "logic ram_cfg_i.b_ram_lcfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.b_ram_fcfg.cfg_en "logic ram_cfg_i.b_ram_fcfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.b_ram_fcfg.cfg "logic ram_cfg_i.b_ram_fcfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.a_ram_lcfg.cfg_en "logic ram_cfg_i.a_ram_lcfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.a_ram_lcfg.cfg "logic ram_cfg_i.a_ram_lcfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.a_ram_fcfg.cfg_en "logic ram_cfg_i.a_ram_fcfg.cfg_en" +CHECKSUM: "3917244548 3354025262" +INSTANCE: tb.dut.top_earlgrey.u_rv_core_ibex.u_core +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.ram_cfg.cfg "logic ram_cfg_i.ram_cfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.rf_cfg.cfg_en "logic ram_cfg_i.rf_cfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.rf_cfg.cfg "logic ram_cfg_i.rf_cfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.ram_cfg.cfg_en "logic ram_cfg_i.ram_cfg.cfg_en" +CHECKSUM: "4158670361 2390704470" +INSTANCE: tb.dut.top_earlgrey +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_1p_cfg_i.ram_cfg.cfg "logic ram_1p_cfg_i.ram_cfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle rom_cfg_i.cfg_en "logic rom_cfg_i.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle rom_cfg_i.cfg "logic rom_cfg_i.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_2p_cfg_i.b_ram_lcfg.cfg_en "logic ram_2p_cfg_i.b_ram_lcfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_2p_cfg_i.b_ram_lcfg.cfg "logic ram_2p_cfg_i.b_ram_lcfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_2p_cfg_i.b_ram_fcfg.cfg_en "logic ram_2p_cfg_i.b_ram_fcfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_2p_cfg_i.b_ram_fcfg.cfg "logic ram_2p_cfg_i.b_ram_fcfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_2p_cfg_i.a_ram_lcfg.cfg_en "logic ram_2p_cfg_i.a_ram_lcfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_2p_cfg_i.a_ram_lcfg.cfg "logic ram_2p_cfg_i.a_ram_lcfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_2p_cfg_i.a_ram_fcfg.cfg_en "logic ram_2p_cfg_i.a_ram_fcfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_2p_cfg_i.a_ram_fcfg.cfg "logic ram_2p_cfg_i.a_ram_fcfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_1p_cfg_i.rf_cfg.cfg_en "logic ram_1p_cfg_i.rf_cfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_1p_cfg_i.rf_cfg.cfg "logic ram_1p_cfg_i.rf_cfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_1p_cfg_i.ram_cfg.cfg_en "logic ram_1p_cfg_i.ram_cfg.cfg_en" +CHECKSUM: "40684302 1739668335" +INSTANCE: tb.dut.top_earlgrey.u_sram_ctrl_ret_aon +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle cfg_i.ram_cfg.cfg "logic cfg_i.ram_cfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle cfg_i.rf_cfg.cfg_en "logic cfg_i.rf_cfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle cfg_i.rf_cfg.cfg "logic cfg_i.rf_cfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle cfg_i.ram_cfg.cfg_en "logic cfg_i.ram_cfg.cfg_en" +CHECKSUM: "40684302 1739668335" +INSTANCE: tb.dut.top_earlgrey.u_sram_ctrl_main +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle cfg_i.ram_cfg.cfg "logic cfg_i.ram_cfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle cfg_i.rf_cfg.cfg_en "logic cfg_i.rf_cfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle cfg_i.rf_cfg.cfg "logic cfg_i.rf_cfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle cfg_i.ram_cfg.cfg_en "logic cfg_i.ram_cfg.cfg_en" +CHECKSUM: "812233703 589831144" +INSTANCE: tb.dut.top_earlgrey.u_usbdev +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.a_ram_fcfg.cfg "logic ram_cfg_i.a_ram_fcfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.b_ram_lcfg.cfg_en "logic ram_cfg_i.b_ram_lcfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.b_ram_lcfg.cfg "logic ram_cfg_i.b_ram_lcfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.b_ram_fcfg.cfg_en "logic ram_cfg_i.b_ram_fcfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.b_ram_fcfg.cfg "logic ram_cfg_i.b_ram_fcfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.a_ram_lcfg.cfg_en "logic ram_cfg_i.a_ram_lcfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.a_ram_lcfg.cfg "logic ram_cfg_i.a_ram_lcfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.a_ram_fcfg.cfg_en "logic ram_cfg_i.a_ram_fcfg.cfg_en" +CHECKSUM: "3097037268 2947567769" +INSTANCE: tb.dut.top_earlgrey.u_rv_core_ibex +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.ram_cfg.cfg "logic ram_cfg_i.ram_cfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.rf_cfg.cfg_en "logic ram_cfg_i.rf_cfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.rf_cfg.cfg "logic ram_cfg_i.rf_cfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.ram_cfg.cfg_en "logic ram_cfg_i.ram_cfg.cfg_en" +CHECKSUM: "4206284388 2271198526" +INSTANCE: tb.dut.top_earlgrey.u_rom_ctrl +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle rom_cfg_i.cfg "logic rom_cfg_i.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle rom_cfg_i.cfg_en "logic rom_cfg_i.cfg_en" +CHECKSUM: "1974103575 3179743996" +INSTANCE: tb.dut.top_earlgrey.u_otbn +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.ram_cfg.cfg "logic ram_cfg_i.ram_cfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.rf_cfg.cfg_en "logic ram_cfg_i.rf_cfg.cfg_en" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.rf_cfg.cfg "logic ram_cfg_i.rf_cfg.cfg[3:0]" +ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" +Toggle ram_cfg_i.ram_cfg.cfg_en "logic ram_cfg_i.ram_cfg.cfg_en"