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rt2800pci.c
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rt2800pci.c
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/*
Copyright (C) 2009 - 2010 Ivo van Doorn <[email protected]>
Copyright (C) 2009 Alban Browaeys <[email protected]>
Copyright (C) 2009 Felix Fietkau <[email protected]>
Copyright (C) 2009 Luis Correia <[email protected]>
Copyright (C) 2009 Mattias Nissler <[email protected]>
Copyright (C) 2009 Mark Asselstine <[email protected]>
Copyright (C) 2009 Xose Vazquez Perez <[email protected]>
Copyright (C) 2009 Bart Zolnierkiewicz <[email protected]>
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2800pci
Abstract: rt2800pci device specific routines.
Supported chipsets: RT2800E & RT2800ED.
*/
#include <linux/delay.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/eeprom_93cx6.h>
#include "rt2x00.h"
#include "rt2x00pci.h"
#include "rt2x00soc.h"
#include "rt2800lib.h"
#include "rt2800.h"
#include "rt2800pci.h"
void MT_2800pci_hex_dump(char *str, unsigned char *pSrcBufVA, u32 SrcBufLen);
extern int AsicWaitPDMAIdle(struct rt2x00_dev *rt2x00dev, int round, int wait_us);
extern void RTMPEnableRxTx(struct rt2x00_dev *rt2x00dev);
static void rt2860_int_disable(struct rt2x00_dev *rt2x00dev, unsigned int mode)
{
u32 regValue;
rt2x00dev->int_disable_mask |= mode;
regValue = rt2x00dev->int_enable_reg & ~(rt2x00dev->int_disable_mask);
rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, regValue); /* 0: disable */
}
static void rt2860_int_enable(struct rt2x00_dev *rt2x00dev, unsigned int mode)
{
u32 regValue;
rt2x00dev->int_disable_mask &= ~(mode);
regValue = rt2x00dev->int_enable_reg & ~(rt2x00dev->int_disable_mask);
rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, regValue); /* 1:enable */
}
/*
* Allow hardware encryption to be disabled.
*/
static bool modparam_nohwcrypt = false;
module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
{
unsigned int i;
u32 reg;
/*
* SOC devices don't support MCU requests.
*/
if (rt2x00_is_soc(rt2x00dev))
return;
if (rt2x00_rt(rt2x00dev, MT7630))
return;
for (i = 0; i < 200; i++) {
rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, ®);
if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
break;
udelay(REGISTER_BUSY_DELAY);
}
if (i == 200)
ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
}
#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
{
void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
iounmap(base_addr);
}
#else
static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
{
}
#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
#ifdef CONFIG_PCI
static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
{
struct rt2x00_dev *rt2x00dev = eeprom->data;
u32 reg;
rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
eeprom->reg_data_clock =
!!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
eeprom->reg_chip_select =
!!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
}
static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
{
struct rt2x00_dev *rt2x00dev = eeprom->data;
u32 reg = 0;
rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
!!eeprom->reg_data_clock);
rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
!!eeprom->reg_chip_select);
rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
}
static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
{
struct eeprom_93cx6 eeprom;
u32 reg;
rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
eeprom.data = rt2x00dev;
eeprom.register_read = rt2800pci_eepromregister_read;
eeprom.register_write = rt2800pci_eepromregister_write;
switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
{
case 0:
eeprom.width = PCI_EEPROM_WIDTH_93C46;
break;
case 1:
eeprom.width = PCI_EEPROM_WIDTH_93C66;
break;
default:
eeprom.width = PCI_EEPROM_WIDTH_93C86;
break;
}
eeprom.reg_data_in = 0;
eeprom.reg_data_out = 0;
eeprom.reg_data_clock = 0;
eeprom.reg_chip_select = 0;
eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
EEPROM_SIZE / sizeof(u16));
}
static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
{
return rt2800_efuse_detect(rt2x00dev);
}
static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
{
rt2800_read_eeprom_efuse(rt2x00dev);
}
#else
static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
{
}
static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
{
return 0;
}
static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
{
}
#endif /* CONFIG_PCI */
/*
* Queue handlers.
*/
static void rt2800pci_start_queue(struct data_queue *queue)
{
struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
u32 reg;
//printk("===>%s:MT7630 queue->qid=%d\n", __FUNCTION__,queue->qid);
switch (queue->qid) {
case QID_RX:
#if 1
rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
#endif
break;
case QID_BEACON:
rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1);
rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, ®);
rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
break;
default:
break;
}
}
static void rt2800pci_kick_queue(struct data_queue *queue)
{
struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
struct queue_entry *entry;
//printk("===>%s:MT7630 queue->qid=%d\n", __FUNCTION__,queue->qid);
switch (queue->qid) {
case QID_AC_VO:
case QID_AC_VI:
case QID_AC_BE:
case QID_AC_BK:
entry = rt2x00queue_get_entry(queue, Q_INDEX);
if (rt2x00_rt(rt2x00dev, MT7630))
rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX_7630(queue->qid),
entry->entry_idx);
else
rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
entry->entry_idx);
break;
case QID_MGMT:
entry = rt2x00queue_get_entry(queue, Q_INDEX);
if (rt2x00_rt(rt2x00dev, MT7630))
rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX_7630(5),
entry->entry_idx);
else
rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
entry->entry_idx);
break;
default:
break;
}
}
static void rt2800pci_stop_queue(struct data_queue *queue)
{
struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
u32 reg;
//printk("===>%s:MT7630 queue->qid=%d\n", __FUNCTION__,queue->qid);
switch (queue->qid) {
case QID_RX:
#if 1
rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
#endif
break;
case QID_BEACON:
rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, ®);
rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
/*
* Wait for current invocation to finish. The tasklet
* won't be scheduled anymore afterwards since we disabled
* the TBTT and PRE TBTT timer.
*/
tasklet_kill(&rt2x00dev->tbtt_tasklet);
tasklet_kill(&rt2x00dev->pretbtt_tasklet);
break;
default:
break;
}
}
/*
* Firmware functions
*/
static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
{
/*
* Chip rt3290 use specific 4KB firmware named rt3290.bin.
*/
if (rt2x00_rt(rt2x00dev, RT3290))
return FIRMWARE_RT3290;
else if (rt2x00_rt(rt2x00dev, MT7630))
return FIRMWARE_MT7630;
else
return FIRMWARE_RT2860;
}
static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
const u8 *data, const size_t len)
{
u32 reg;
if (rt2x00_rt(rt2x00dev, MT7630))
{
u32 Loop=0;
u32 ILMLen, DLMLen;
u16 FWVersion, BuildVersion;
u32 StartOffset, EndOffset, idx = 0, val = 0;
{
loadfw_protect:
rt2x00pci_register_read(rt2x00dev, 0x07B0, ®);
Loop++;
if (((reg & 0x01) == 0) && (Loop < 10000))
goto loadfw_protect;
}
/* check MCU if ready */
rt2x00pci_register_read(rt2x00dev, 0x0730, ®);
if (reg == 0x01)
goto done;
ILMLen = (*(data + 3) << 24) | (*(data + 2) << 16) |
(*(data + 1) << 8) | (*data);
DLMLen = (*(data + 7) << 24) | (*(data + 6) << 16) |
(*(data + 5) << 8) | (*(data + 4));
FWVersion = (*(data + 11) << 8) | (*(data + 10));
BuildVersion = (*(data + 9) << 8) | (*(data + 8));
printk("FW Version:%d.%d.%02d ", (FWVersion & 0xf000) >> 8,
(FWVersion & 0x0f00) >> 8, FWVersion & 0x00ff);
printk("Build:%x\n", BuildVersion);
printk("Build Time:");
for (Loop = 0; Loop < 16; Loop++)
printk("%c", *(data + 16 + Loop));
printk("\n");
printk("ILM Length = %d(bytes)\n", ILMLen);
printk("DLM Length = %d(bytes)\n", DLMLen);
rt2x00pci_register_write(rt2x00dev, 0x074c, 0x0);
StartOffset = 96;
EndOffset = 32 + ILMLen;
/* Load ILM code */
for (idx = StartOffset; idx < EndOffset; idx += 4)
{
val = (*(data + idx)) +
(*(data + idx +3) << 24) +
(*(data + idx + 2) << 16) +
(*(data + idx + 1) << 8);
rt2x00pci_register_write(rt2x00dev, 0x80000 + (idx - 32), val);
}
/* Loading IVB part into last 64 bytes of ILM */
StartOffset = 32;
EndOffset = 96;
for (idx = StartOffset; idx < EndOffset; idx += 4)
{
val = (*(data + idx)) +
(*(data + idx + 3) << 24) +
(*(data + idx + 2) << 16) +
(*(data + idx + 1) << 8);
rt2x00pci_register_write(rt2x00dev, 0x80000 + (0x54000 - 0x40) + (idx - 32), val);
}
rt2x00pci_register_write(rt2x00dev, 0x074c, 0x80000);
StartOffset = 32 + ILMLen;
EndOffset = 32 + ILMLen + DLMLen;
/* Load DLM code */
for (idx = StartOffset; idx < EndOffset; idx += 4)
{
val = (*(data + idx)) +
(*(data + idx + 3) << 24) +
(*(data + idx + 2) << 16) +
(*(data + idx + 1) << 8);
rt2x00pci_register_write(rt2x00dev, 0x80000 + (idx - 32 - ILMLen), val);
}
rt2x00pci_register_write(rt2x00dev, 0x074c, 0x0);
rt2x00pci_register_write(rt2x00dev, 0x0718, 0x03);
/* check MCU if ready */
Loop = 0;
do
{
rt2x00pci_register_read(rt2x00dev, 0x0730, ®);
if (reg == 0x1)
break;
mdelay(10);
Loop++;
} while (Loop <= 20);
printk("%s: COM_REG0(0x%x) = 0x%x\n", __FUNCTION__, 0x0730, reg);
if (reg != 0x1)
{
rt2x00pci_register_read(rt2x00dev, 0x0700, ®);
printk("%s: 0x0700 = 0x%x\n", __FUNCTION__, val);
rt2x00pci_register_read(rt2x00dev, 0x0704, ®);
printk("%s: 0x%x = 0x%x\n", __FUNCTION__, 0x0704, val);
}
rt2x00pci_register_write(rt2x00dev, 0x07B0, 0x1);
}
else
{
/*
* enable Host program ram write selection
*/
reg = 0;
rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
/*
* Write firmware to device.
*/
rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
data, len);
rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
}
done:
return 0;
}
/*
* Initialization functions.
*/
static bool rt2800pci_get_entry_state(struct queue_entry *entry)
{
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
u32 word;
//printk("===>%s:MT7630\n", __FUNCTION__);
if (entry->queue->qid == QID_RX) {
rt2x00_desc_read(entry_priv->desc, 1, &word);
return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
} else {
rt2x00_desc_read(entry_priv->desc, 1, &word);
return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
}
}
typedef struct __attribute__ ((packed)) _RXD_STRUC{
/* Word 0 */
UINT32 SDP0;
/* Word 1 */
UINT32 SDL1:14;
UINT32 LS1:1;
UINT32 BURST:1;
UINT32 SDL0:14;
UINT32 LS0:1;
UINT32 DDONE:1;
/* Word 2 */
UINT32 SDP1;
}RXD_STRUC, *PRXD_STRUC;
static void rt2800pci_clear_entry(struct queue_entry *entry)
{
//printk("===>%s:MT7630\n", __FUNCTION__);
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
u32 word;
if (entry->queue->qid == QID_RX) {
if (rt2x00_rt(rt2x00dev, MT7630))
{
#if 0
pRxD = entry_priv->desc;
pRxD->SDP0 = skbdesc->skb_dma;
pRxD->DDONE = 0;
#else
rt2x00_desc_read(entry_priv->desc, 0, &word);
rt2x00_set_field32(&word, RXD_W0_7630_SDP0, skbdesc->skb_dma);
rt2x00_desc_write(entry_priv->desc, 0, word);
rt2x00_desc_read(entry_priv->desc, 1, &word);
rt2x00_set_field32(&word, RXD_W1_7630_DMA_DONE, 0);
rt2x00_set_field32(&word, RXD_W1_7630_SDL0, entry->skb->len);
rt2x00_desc_write(entry_priv->desc, 1, word);
#endif
/*
* Set RX IDX in register to inform hardware that we have
* handled this entry and it is available for reuse again.
*/
rt2x00pci_register_write(rt2x00dev, RX_RING_CIDX,
entry->entry_idx);
//printk("rt2800pci_clear_entry entry_priv->desc = 0x%x skbdesc->skb_dma = 0x%x entry->entry_idx = %d\n",entry_priv->desc,skbdesc->skb_dma,entry->entry_idx);
//MT_2800pci_hex_dump("RXD entry_priv->desc", entry_priv->desc, 16);
} else {
rt2x00_desc_read(entry_priv->desc, 0, &word);
rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
rt2x00_desc_write(entry_priv->desc, 0, word);
rt2x00_desc_read(entry_priv->desc, 1, &word);
rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
rt2x00_desc_write(entry_priv->desc, 1, word);
/*
* Set RX IDX in register to inform hardware that we have
* handled this entry and it is available for reuse again.
*/
rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
entry->entry_idx);
}
} else {
rt2x00_desc_read(entry_priv->desc, 1, &word);
rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
rt2x00_desc_write(entry_priv->desc, 1, word);
//printk("clear entry TX %d\n",entry->queue->qid);
}
}
static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
{
struct queue_entry_priv_pci *entry_priv;
u32 i, offset;
int ret=0;
/*
* Initialize registers.
*/
if (rt2x00_rt(rt2x00dev, MT7630))
{
for (i = 0 ; i < 4; i++)
{
offset = i * 0x10;
entry_priv = rt2x00dev->tx[i].entries[i].priv_data;
rt2x00pci_register_write(rt2x00dev, TX_RING_BASE + offset, entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TX_RING_CNT + offset, rt2x00dev->tx[i].limit);
rt2x00pci_register_write(rt2x00dev, TX_RING_CIDX + offset, 0);
printk("-->TX_RING: Base=0x%x, Cnt=%d\n", entry_priv->desc_dma,rt2x00dev->tx[i].limit);
}
offset = 4 * 0x10;
rt2x00pci_register_write(rt2x00dev, TX_RING_BASE + offset, 0);
rt2x00pci_register_write(rt2x00dev, TX_RING_CNT + offset, 0);
rt2x00pci_register_write(rt2x00dev, TX_RING_CIDX + offset, 0);
rt2x00pci_register_write(rt2x00dev, TX_MGMT_BASE, 0);
rt2x00pci_register_write(rt2x00dev, TX_MGMT_CNT, 0);
rt2x00pci_register_write(rt2x00dev, TX_MGMT_CIDX, 0);
entry_priv = rt2x00dev->rx->entries[0].priv_data;
rt2x00pci_register_write(rt2x00dev, RX_RING_BASE, entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, RX_RING_CNT, rt2x00dev->rx[0].limit);
rt2x00pci_register_write(rt2x00dev, RX_RING_CIDX, rt2x00dev->rx[0].limit - 1);
rt2x00pci_register_write(rt2x00dev, RX_RING_CIDX + 0x10, rt2x00dev->rx[0].limit - 1);
printk("-->RX_RING: Base=0x%x, Cnt=%d\n", entry_priv->desc_dma,rt2x00dev->rx[0].limit);
printk("InitTxRxRing\n");
/*
Reset DMA Index
*/
rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, 0xFFFFFFFF);
ret = rt2800_wait_wpdma_ready(rt2x00dev);
if (ret != 0)
printk("DMA busy\n");
rt2800_disable_wpdma(rt2x00dev);
rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
}
else {
entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
rt2x00dev->tx[0].limit);
rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
rt2x00dev->tx[1].limit);
rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
rt2x00dev->tx[2].limit);
rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
rt2x00dev->tx[3].limit);
rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR4, 0);
rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT4, 0);
rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX4, 0);
rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX4, 0);
rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR5, 0);
rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT5, 0);
rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX5, 0);
rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX5, 0);
entry_priv = rt2x00dev->rx->entries[0].priv_data;
rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
rt2x00dev->rx[0].limit);
rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
rt2x00dev->rx[0].limit - 1);
rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
rt2800_disable_wpdma(rt2x00dev);
rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
}
return 0;
}
#if 0
typedef union _WPDMA_GLO_CFG_STRUC {
struct {
u32 EnableTxDMA:1;
u32 TxDMABusy:1;
u32 EnableRxDMA:1;
u32 RxDMABusy:1;
u32 WPDMABurstSIZE:2;
u32 EnTXWriteBackDDONE:1;
u32 BigEndian:1;
u32 HDR_SEG_LEN:8;
u32 rsv:14;
u32 clk_gate_dis:1;
u32 rx_2b_offset:1;
} field;
u32 word;
} WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
int AsicWaitPDMAIdle(struct rt2x00_dev *rt2x00dev, int round, int wait_us)
{
int i = 0;
WPDMA_GLO_CFG_STRUC GloCfg;
do {
rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &GloCfg.word);
if ((GloCfg.field.TxDMABusy == 0) && (GloCfg.field.RxDMABusy == 0)) {
printk("==> DMAIdle, GloCfg=0x%x\n", GloCfg.word);
return 0;
}
udelay(wait_us);
}while ((i++) < round);
printk("==> DMABusy, GloCfg=0x%x\n", GloCfg.word);
return 1;
}
static void RT28XXDMAEnable(struct rt2x00_dev *rt2x00dev)
{
WPDMA_GLO_CFG_STRUC GloCfg;
rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x4);
AsicWaitPDMAIdle(rt2x00dev, 200, 1000);
udelay(50);
rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &GloCfg.word);
GloCfg.field.EnTXWriteBackDDONE = 1;
GloCfg.field.WPDMABurstSIZE = 3;
GloCfg.field.EnableRxDMA = 1;
GloCfg.field.EnableTxDMA = 1;
rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, GloCfg.word);
printk("<== WRITE DMA offset 0x208 = 0x%x\n", GloCfg.word);
}
static void RTMPEnableRxTx(struct rt2x00_dev *rt2x00dev)
{
u32 rx_filter_flag;
printk("==> RTMPEnableRxTx\n");
RT28XXDMAEnable(rt2x00dev);
/* enable RX of MAC block*/
rx_filter_flag = 0x17f97; /* Staion not drop control frame will fail WiFi Certification.*/
rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, rx_filter_flag);
{
rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0xc);
//+++Add by shiang for debug for pbf_loopback
// RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x2c);
//---Add by shiang for debug
//+++Add by shiang for debug invalid RxWI->WCID
//---Add by shiang for debug invalid RxWI->WCID
}
printk("<== RTMPEnableRxTx\n");
}
#endif
/*
* Device state switch handlers.
*/
static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
enum dev_state state)
{
u32 reg;
unsigned long flags;
/*
* When interrupts are being enabled, the interrupt registers
* should clear the register to assure a clean state.
*/
if (state == STATE_RADIO_IRQ_ON) {
if (rt2x00_rt(rt2x00dev, MT7630))
rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, 0xffffffff);
else
{
rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
}
}
spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
reg = 0;
if (state == STATE_RADIO_IRQ_ON) {
if (rt2x00_rt(rt2x00dev, MT7630))
{
rt2x00_set_field32(®, INT_MASK_CSR_7630_RX_DONE, 1);
rt2x00_set_field32(®, INT_MASK_CSR_7630_TBTT, 1);
rt2x00_set_field32(®, INT_MASK_CSR_7630_PRE_TBTT, 1);
rt2x00_set_field32(®, INT_MASK_CSR_7630_TX_FIFO_STATUS, 1);
rt2x00_set_field32(®, INT_MASK_CSR_7630_AUTO_WAKEUP, 1);
} else {
rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, 3);
rt2x00_set_field32(®, INT_MASK_CSR_TBTT, 1);
rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, 1);
rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, 1);
rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, 1);
}
#if 1
if (rt2x00_rt(rt2x00dev, MT7630))
reg = ((DELAYINTMASK) |(RxINT|TxDataInt|TxMgmtInt));
#endif
}
rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
rt2x00dev->int_enable_reg=reg;
spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
if (state == STATE_RADIO_IRQ_ON && rt2x00_rt(rt2x00dev, MT7630)) {
printk("set INT_MASK_CSR = 0x%x\n",reg);
RTMPEnableRxTx(rt2x00dev);
rt2x00pci_register_read(rt2x00dev, 0x1300, ®); /* clear garbage interrupts*/
printk("0x1300 = %08x\n", reg);
printk("%s(1):Check if PDMA is idle!\n", __FUNCTION__);
AsicWaitPDMAIdle(rt2x00dev, 5, 10);
printk("%s(2):Check if PDMA is idle!\n", __FUNCTION__);
AsicWaitPDMAIdle(rt2x00dev, 5, 10);
}
if (state == STATE_RADIO_IRQ_OFF) {
/*
* Wait for possibly running tasklets to finish.
*/
tasklet_kill(&rt2x00dev->tx0damdone_tasklet);
tasklet_kill(&rt2x00dev->tx1damdone_tasklet);
tasklet_kill(&rt2x00dev->tx2damdone_tasklet);
tasklet_kill(&rt2x00dev->tx3damdone_tasklet);
tasklet_kill(&rt2x00dev->txstatus_tasklet);
tasklet_kill(&rt2x00dev->rxdone_tasklet);
tasklet_kill(&rt2x00dev->autowake_tasklet);
tasklet_kill(&rt2x00dev->tbtt_tasklet);
tasklet_kill(&rt2x00dev->pretbtt_tasklet);
}
}
static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
{
u32 reg;
/*
* Reset DMA indexes
*/
if (!rt2x00_rt(rt2x00dev, MT7630))
{
rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
}
rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
if (rt2x00_is_pcie(rt2x00dev) &&
(rt2x00_rt(rt2x00dev, RT3572) ||
rt2x00_rt(rt2x00dev, RT5390) ||
rt2x00_rt(rt2x00dev, RT5392))) {
rt2x00pci_register_read(rt2x00dev, AUX_CTRL, ®);
rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
}
if (!rt2x00_rt(rt2x00dev, MT7630))
{
rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
}
reg = 0;
rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);
rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
return 0;
}
static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
{
int retval;
printk("===>%s: \n", __FUNCTION__);
/* Wait for DMA, ignore error until we initialize queues. */
rt2800_wait_wpdma_ready(rt2x00dev);
if (!rt2x00_rt(rt2x00dev, MT7630))
{
if (unlikely(rt2800pci_init_queues(rt2x00dev)))
return -EIO;
}
retval = rt2800_enable_radio(rt2x00dev);
if (retval)
return retval;
#if 0
/* After resume MCU_BOOT_SIGNAL will trash these. */
rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
#endif
rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
printk("<===%s: \n", __FUNCTION__);
//return -EIO;
return retval;
}
static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
{
if (rt2x00_is_soc(rt2x00dev)) {
rt2800_disable_radio(rt2x00dev);
rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
}
}
static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
enum dev_state state)
{
printk("===>%s\n",__FUNCTION__);
if (state == STATE_AWAKE) {
rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
0, 0x02);
rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
} else if (state == STATE_SLEEP) {
rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
0xffffffff);
rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
0xffffffff);
rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
0xff, 0x01);
}
return 0;
}
static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
enum dev_state state)
{
int retval = 0;
printk("===>%s:MT7630\n", __FUNCTION__);
switch (state) {
case STATE_RADIO_ON:
retval = rt2800pci_enable_radio(rt2x00dev);
break;
case STATE_RADIO_OFF:
/*
* After the radio has been disabled, the device should
* be put to sleep for powersaving.
*/
rt2800pci_disable_radio(rt2x00dev);
rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
break;
case STATE_RADIO_IRQ_ON:
case STATE_RADIO_IRQ_OFF:
rt2800pci_toggle_irq(rt2x00dev, state);
break;
case STATE_DEEP_SLEEP:
case STATE_SLEEP:
case STATE_STANDBY:
case STATE_AWAKE:
retval = rt2800pci_set_state(rt2x00dev, state);
break;
default:
retval = -ENOTSUPP;
break;
}
if (unlikely(retval))
ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
state, retval);
return retval;
}
/*
* TX descriptor initialization
*/
static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)