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Merge pull request #83 from angr/fix/add_to_mem_endness
fix the endianness issue in mem_changer
2 parents 496229a + 4b20071 commit 92dc6fb

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2 files changed

+18
-3
lines changed

2 files changed

+18
-3
lines changed

angrop/chain_builder/mem_changer.py

+6-3
Original file line numberDiff line numberDiff line change
@@ -24,12 +24,15 @@ def update(self):
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self._mem_add_gadgets = self._get_all_mem_add_gadgets()
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def verify(self, chain, addr, value, _):
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arch_bytes = self.project.arch.bytes
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endness = self.project.arch.memory_endness
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# verify the chain actually works
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chain2 = chain.copy()
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chain2._blank_state.memory.store(addr.data, 0x42424242, self.project.arch.bytes)
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chain2._blank_state.memory.store(addr.data, 0x41424344, arch_bytes, endness=endness)
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state = chain2.exec()
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sim_data = state.memory.load(addr.data, self.project.arch.bytes, endness=self.project.arch.memory_endness)
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if not state.solver.eval(sim_data == 0x42424242 + value.data):
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sim_data = state.memory.load(addr.data, arch_bytes, endness=endness)
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if not state.solver.eval(sim_data == 0x41424344 + value.data):
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raise RopException("memory add fails - 1")
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# the next pc must come from the stack
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if len(state.regs.pc.variables) != 1:

tests/test_chainbuilder.py

+12
Original file line numberDiff line numberDiff line change
@@ -207,6 +207,18 @@ def test_add_to_mem():
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rop.add_to_mem(0x41414140, 0x42424242)
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cache_path = os.path.join(CACHE_DIR, "amd64_glibc_2.19")
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proj = angr.Project(os.path.join(BIN_DIR, "tests", "x86_64", "libc.so.6"), auto_load_libs=False)
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rop = proj.analyses.ROP()
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if os.path.exists(cache_path):
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rop.load_gadgets(cache_path)
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else:
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rop.find_gadgets()
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rop.save_gadgets(cache_path)
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rop.add_to_mem(0x41414140, 0x42424242)
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def test_pivot():
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cache_path = os.path.join(CACHE_DIR, "i386_glibc_2.35")
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proj = angr.Project(os.path.join(BIN_DIR, "tests", "i386", "i386_glibc_2.35"), auto_load_libs=False)

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