@@ -34,7 +34,8 @@ def __init__(self, project, fast_mode, kernel_mode=False, arch=None, stack_gsize
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# initial state that others are based off, all analysis should copy the state first and work on
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# the copied state
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self ._stack_bsize = stack_gsize * self .project .arch .bytes # number of controllable bytes on stack
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- self ._state = rop_utils .make_symbolic_state (self .project , self .arch .reg_set .union ({self .arch .base_pointer }), stack_gsize = stack_gsize )
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+ sym_reg_set = self .arch .reg_set .union ({self .arch .base_pointer })
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+ self ._state = rop_utils .make_symbolic_state (self .project , sym_reg_set , stack_gsize = stack_gsize )
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self ._concrete_sp = self ._state .solver .eval (self ._state .regs .sp )
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@rop_utils .timeout (3 )
@@ -203,7 +204,7 @@ def _reach_unconstrained_or_syscall(self, addr):
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succ = self .project .factory .successors (state )
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state = succ .flat_successors [0 ]
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state2 = rop_utils .step_to_unconstrained_successor (self .project , state = state )
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- except Exception :
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+ except Exception : # pylint: disable=broad-exception-caught
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return init_state , final_state
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return init_state , state2
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return init_state , final_state
@@ -224,7 +225,8 @@ def _identify_transit_type(self, final_state, ctrl_type):
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continue
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if act .size != self .project .arch .bits :
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continue
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- if (act .data .ast == final_state .ip ).symbolic or not final_state .solver .eval (act .data .ast == final_state .ip ):
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+ if (act .data .ast == final_state .ip ).symbolic or \
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+ not final_state .solver .eval (act .data .ast == final_state .ip ):
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continue
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sols = final_state .solver .eval_upto (final_state .regs .sp - act .addr .ast , 2 )
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if len (sols ) != 1 :
@@ -507,7 +509,7 @@ def _check_if_stack_controls_ast(self, ast, initial_state, gadget_stack_change=N
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concrete_stack_s = initial_state .copy ()
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concrete_stack_s .add_constraints (
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initial_state .memory .load (initial_state .regs .sp , stack_bytes_length ) == concrete_stack )
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- test_constraint = ( ast != test_val )
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+ test_constraint = ast != test_val
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# stack must have set the register and it must be able to set the register to all 1's or all 0's
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ans = not concrete_stack_s .solver .satisfiable (extra_constraints = (test_constraint ,)) and \
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rop_utils .fast_unconstrained_check (initial_state , ast )
@@ -611,7 +613,7 @@ def _build_mem_access(self, a, gadget, init_state, final_state):
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elif len (test_data ) == 1 :
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mem_access .data_constant = test_data [0 ]
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else :
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- raise Exception ("No data values, something went wrong" )
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+ raise RopException ("No data values, something went wrong" )
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elif a .action == "read" :
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# for reads we want to know if any register will have the data after
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succ_state = final_state
@@ -738,7 +740,7 @@ def _analyze_mem_access(self, final_state, init_state, gadget):
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continue
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# ignore read/write on stack after pivot
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- if a .addr .ast .symbolic and not ( a .addr .ast .variables - sp_vars ) :
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+ if a .addr .ast .symbolic and not a .addr .ast .variables - sp_vars :
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continue
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# ignore read/write on stack
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