Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Memory with async read ports can synthesize to a BRAM on Xilinx platforms #218

Open
nmigen-issue-migration opened this issue Sep 20, 2019 · 0 comments
Open

Memory with async read ports can synthesize to a BRAM on Xilinx platforms #218

nmigen-issue-migration opened this issue Sep 20, 2019 · 0 comments
Labels
improvement platform:xilinx-7series platform:xilinx-spartan-3/6 unsoundness

Comments

@nmigen-issue-migration
Copy link

Issue by whitequark
Friday Sep 20, 2019 at 20:13 GMT
Originally opened as m-labs/nmigen#218

Due to what is arguably a bug in the Xilinx toolchain (since it synthesizes perfectly well-formed behavioral Verilog to something that has different behavior), any Memory with an asynchronous read port (often a SyncFIFO) can synthesize to a BRAM in an unpredictable way. To avoid this, a platform-specific pass should insert an attribute for any memory with asynchronous read ports that makes sure it ends up as distributed RAM.

@nakengelhardt tried to fix this in oMigen in m-labs/migen#105, but oMigen does not have the infrastructure required to fix this properly.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
improvement platform:xilinx-7series platform:xilinx-spartan-3/6 unsoundness
Milestone
No milestone
Development

No branches or pull requests
2 participants
@whitequark @nmigen-issue-migration