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flow graph analysis and automation #213
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Comment by whitequark One thing to add is that for a while I wanted to add some first-class interface for specifying port directions, essentially the same thing as describing something as
Not just simulation; assertions for property testing ("formal verification") are much more valuable for this, since they are better at discovering edge cases.
There has been interest in having an AXI4-Stream-like interface in nMigen core (from @lambdaconcept, and it also exists in LiteX, showing substantial interest), so I think such stream interface should be added first. |
Comment by jordens Right. A good stream interface is the foundation for all this. |
Comment by whitequark My proposal for the stream interface is to use four signals: |
Comment by jordens Perfect. It would be great if we can make this interface so smooth that the even the dumb usage ( |
Comment by whitequark We can make |
Comment by jordens Or a different constructor to make this usage explicit. |
Comment by mithro Would be good to understand how this might match wishbone too? |
Comment by whitequark I don't think this is relevant to Wishbone, since it does not have a streaming interface. |
Comment by whitequark I believe that an implementation of Rigel would provide every single feature @jordens requested. |
Comment by daveshah1 I would love something like that in nMigen, and might even be able to help next year. My past experience of line-buffer based video processing with moving windows has been very enjoyable, it would be interesting to work with something like that again. |
Comment by whitequark Sweet! |
Comment by mithro That paper is super interesting! This stuff is something that I could potentially look at providing funding around. I'm more interested in actually using it for graphics related stuff. |
Issue by jordens
Friday Sep 20, 2019 at 12:09 GMT
Originally opened as m-labs/nmigen#213
Develop tooling to help with non-trivial flow graphs. Somewhat like the old
migen.flow
scheme.Features
stb
-style interfaces where data is not constantly streamed but "blanked"eof
a.k.a.sop
/eop
): determine overall cycle periodsstb
/ack
-style interfaces and implement back-pressure to dynamically pace upstream componentsImplementation aspects/questions
stb
signals) at the module boundaries. I.e. allow verification of the specified latency matrices.Use cases, prior art:
migen.flow
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