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commit f0856bb Author: akatsuki105 <[email protected]> Date: Tue Nov 26 22:09:15 2024 +0900 fix commit 1a5083c Author: akatsuki105 <[email protected]> Date: Tue Nov 26 04:04:09 2024 +0900 fix commit 929d588 Author: akatsuki105 <[email protected]> Date: Wed Nov 20 14:55:09 2024 +0900 fix commit e637ec8 Author: akatsuki105 <[email protected]> Date: Wed Nov 20 14:29:56 2024 +0900 fix commit 8feca17 Author: akatsuki105 <[email protected]> Date: Wed Nov 20 14:26:52 2024 +0900 wip commit b05dfe3 Author: akatsuki105 <[email protected]> Date: Wed Nov 20 14:21:12 2024 +0900 wip commit ddb02e6 Author: akatsuki105 <[email protected]> Date: Wed Nov 20 14:15:53 2024 +0900 wip commit 923f5ad Author: akatsuki105 <[email protected]> Date: Wed Nov 20 13:48:44 2024 +0900 wip commit 9a0c950 Author: akatsuki105 <[email protected]> Date: Wed Nov 20 13:43:29 2024 +0900 wip commit f5ead09 Author: akatsuki105 <[email protected]> Date: Wed Nov 20 13:38:38 2024 +0900 fix commit 013e0c4 Author: akatsuki105 <[email protected]> Date: Wed Nov 20 13:30:01 2024 +0900 wip commit e8e9338 Author: akatsuki105 <[email protected]> Date: Wed Nov 20 13:23:50 2024 +0900 fix commit 5e764a0 Author: akatsuki105 <[email protected]> Date: Wed Nov 20 13:17:05 2024 +0900 fix commit 5e28825 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 18:57:59 2024 +0900 fix commit 7a13969 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 16:40:34 2024 +0900 wip commit c37ad48 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 16:03:55 2024 +0900 wip commit 78f5448 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 15:48:35 2024 +0900 fix commit 629aa66 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 15:48:11 2024 +0900 wip commit 5f41e0e Author: akatsuki105 <[email protected]> Date: Tue Nov 19 15:41:30 2024 +0900 wip commit 6244d26 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 15:32:43 2024 +0900 wip commit 3691bbc Author: akatsuki105 <[email protected]> Date: Tue Nov 19 15:29:14 2024 +0900 wip commit b489855 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 15:19:48 2024 +0900 refactor palette commit 48f91c9 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 15:08:07 2024 +0900 wip commit ba7d3b8 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 14:23:19 2024 +0900 wip commit 8d73726 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 14:19:42 2024 +0900 fix commit 4160e88 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 14:17:28 2024 +0900 fix mbc2 commit 99b9aae Author: akatsuki105 <[email protected]> Date: Tue Nov 19 13:58:09 2024 +0900 wip commit 20a3e8d Author: akatsuki105 <[email protected]> Date: Tue Nov 19 13:39:34 2024 +0900 fix commit a62ab00 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 13:28:05 2024 +0900 wip commit b9b126a Author: akatsuki105 <[email protected]> Date: Tue Nov 19 13:25:47 2024 +0900 wip commit 17b9f56 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 12:28:06 2024 +0900 wip commit 16dcbf6 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 12:24:58 2024 +0900 fix commit 0bf2fa2 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 12:22:08 2024 +0900 fix commit 1accc90 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 12:16:19 2024 +0900 wip commit 039577e Author: akatsuki105 <[email protected]> Date: Tue Nov 19 12:14:50 2024 +0900 wip commit e2baebd Author: akatsuki105 <[email protected]> Date: Tue Nov 19 12:11:53 2024 +0900 sp commit 01fd9c9 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 12:09:51 2024 +0900 rename commit 595c2af Author: akatsuki105 <[email protected]> Date: Tue Nov 19 12:08:23 2024 +0900 wip commit 1490d56 Author: akatsuki105 <[email protected]> Date: Tue Nov 19 12:05:01 2024 +0900 wip commit ade39dd Author: akatsuki105 <[email protected]> Date: Mon Nov 18 18:08:35 2024 +0900 wip commit ebbe87b Author: akatsuki105 <[email protected]> Date: Mon Nov 18 17:59:01 2024 +0900 wip memory commit c289fb0 Author: akatsuki105 <[email protected]> Date: Mon Nov 18 17:09:49 2024 +0900 wip commit 024393c Author: akatsuki105 <[email protected]> Date: Mon Nov 18 17:06:08 2024 +0900 wip commit 6330e8a Author: akatsuki105 <[email protected]> Date: Mon Nov 18 17:01:18 2024 +0900 compatible palette commit 8e27dfe Author: akatsuki105 <[email protected]> Date: Mon Nov 18 15:56:51 2024 +0900 wip commit 0fa21ab Author: akatsuki105 <[email protected]> Date: Mon Nov 18 14:22:07 2024 +0900 wip commit 58f3103 Author: akatsuki105 <[email protected]> Date: Mon Nov 18 12:32:18 2024 +0900 mbc2 commit eeaee45 Author: akatsuki105 <[email protected]> Date: Mon Nov 18 01:47:29 2024 +0900 fix commit ddf6422 Author: akatsuki105 <[email protected]> Date: Mon Nov 18 01:17:53 2024 +0900 wip commit a76e67b Author: akatsuki105 <[email protected]> Date: Sun Nov 17 23:27:43 2024 +0900 cgb mode commit 734c186 Author: akatsuki105 <[email protected]> Date: Sun Nov 17 23:05:27 2024 +0900 mode
1 parent dc50be5 commit 3a42d68

38 files changed

+1376
-1273
lines changed

‎.vscode/settings.json

+23-6
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,26 @@
11
{
2-
"[go]": {
3-
"editor.tabSize": 2,
4-
"editor.formatOnSave": true,
5-
"editor.codeActionsOnSave": {
6-
"source.organizeImports": "explicit"
7-
}
2+
"[go]": {
3+
"editor.tabSize": 2,
4+
"editor.formatOnSave": true,
5+
"editor.codeActionsOnSave": {
6+
"source.organizeImports": "explicit"
7+
}
8+
},
9+
"[cpp]": {
10+
"editor.formatOnSave": true,
11+
"editor.tabSize": 2,
12+
"editor.foldingStrategy": "indentation",
13+
},
14+
"[c]": {
15+
"editor.foldingStrategy": "indentation",
16+
},
17+
"gopls": {
18+
"codelenses": { // CodeLens はエディタ画面から直接コマンドを実行できる機能 (packageの上にクリックすると静的解析を行うボタンが出てくる)
19+
"gc_details": true
820
},
21+
"ui.diagnostic.annotations": {
22+
"escape": true,
23+
// "inline": true,
24+
}
25+
}
926
}

‎README.md

+1-1
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ You can play on [web](https://dawngb.vercel.app/)!
1818
## Features
1919

2020
- GB(DMG) and GBC(CGB) support
21-
- MBC1, MBC3, MBC5, MBC30 support
21+
- MBC1, MBC2, MBC3, MBC5, MBC30 support
2222
- Sound(APU) support
2323
- Libretro support(run `make libretro`)
2424
- Multiplatform support

‎core/gb/apu/apu.go

+3-2
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@ import (
77
"github.com/akatsuki105/dawngb/core/gb/apu/psg"
88
)
99

10+
// SoCに組み込まれているため、`/cpu`にある方が正確ではある
1011
type APU struct {
1112
cycles int64 // 8MHzのマスターサイクル単位
1213
*psg.PSG
@@ -27,8 +28,8 @@ func New(audioBuffer io.Writer) *APU {
2728
}
2829
}
2930

30-
func (a *APU) Reset(hasBIOS bool) {
31-
a.PSG.Reset(hasBIOS)
31+
func (a *APU) Reset() {
32+
a.PSG.Reset()
3233
a.cycles = 0
3334
clear(a.samples[:])
3435
a.sampleCount = 0

‎core/gb/apu/psg/psg.go

+2-5
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ func New(model uint8) *PSG {
3939
}
4040
}
4141

42-
func (a *PSG) Reset(hasBIOS bool) {
42+
func (a *PSG) Reset() {
4343
a.enabled = false
4444
a.ch1.reset()
4545
a.ch2.reset()
@@ -49,12 +49,9 @@ func (a *PSG) Reset(hasBIOS bool) {
4949
clear(a.ioreg[:])
5050
a.leftVolume, a.rightVolume = 7, 7
5151
a.leftEnables, a.rightEnables = [4]bool{}, [4]bool{}
52-
if !hasBIOS {
53-
a.skipBIOS()
54-
}
5552
}
5653

57-
func (a *PSG) skipBIOS() {
54+
func (a *PSG) SkipBIOS() {
5855
a.Write(NR10, 0x80)
5956
a.Write(NR11, 0xBF)
6057
a.Write(NR12, 0xF3)

‎core/gb/cartridge/cartridge.go

+12-9
Original file line numberDiff line numberDiff line change
@@ -22,9 +22,9 @@ type mbc interface {
2222

2323
type Cartridge struct {
2424
title string
25-
rom []uint8
25+
ROM []uint8
2626
ram []uint8 // SRAM
27-
mbc
27+
mbc // mapper
2828
}
2929

3030
func New(rom []uint8) (*Cartridge, error) {
@@ -40,10 +40,10 @@ func New(rom []uint8) (*Cartridge, error) {
4040
ram: make([]uint8, 0),
4141
}
4242

43-
c.rom = make([]uint8, (32*KB)<<rom[0x148])
44-
copy(c.rom, rom)
43+
c.ROM = make([]uint8, (32*KB)<<rom[0x148])
44+
copy(c.ROM, rom)
4545

46-
ramSize, ok := RAM_SIZES[rom[0x149]]
46+
ramSize, ok := RAM_SIZES[rom[0x149]] // これはSRAMチップのサイズであって、MBC2のようなMBCチップにRAMが内蔵されている場合は0になるっぽい
4747
if ok {
4848
c.ram = make([]uint8, ramSize)
4949
}
@@ -53,17 +53,20 @@ func New(rom []uint8) (*Cartridge, error) {
5353
return nil, err
5454
}
5555
c.mbc = mbc
56-
fmt.Println("MapperID:", c.rom[0x147])
56+
// fmt.Println("MapperID:", c.ROM[0x147])
5757
return c, nil
5858
}
5959

6060
func createMBC(c *Cartridge) (mbc, error) {
61-
mbcType := c.rom[0x147]
61+
mbcType := c.ROM[0x147]
6262
switch mbcType {
6363
case 0:
6464
return newMBC0(c), nil
6565
case 1, 2, 3:
6666
return newMBC1(c), nil
67+
case 5, 6:
68+
c.ram = make([]uint8, 512)
69+
return newMBC2(c), nil
6770
case 16, 19:
6871
return newMBC3(c), nil
6972
case 25, 26, 27:
@@ -85,8 +88,8 @@ func (c *Cartridge) Write(addr uint16, val uint8) {
8588
c.mbc.write(addr, val)
8689
}
8790

88-
func (c *Cartridge) IsCGB() bool {
89-
return (c.rom[0x143] & (1 << 7)) != 0
91+
func (c *Cartridge) CGBFlag() uint8 {
92+
return c.ROM[0x143]
9093
}
9194

9295
func (c *Cartridge) LoadSRAM(data []uint8) error {

‎core/gb/cartridge/mbc0.go

+14-5
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,35 @@
11
package cartridge
22

33
type mbc0 struct {
4-
c *Cartridge
4+
c *Cartridge
5+
hasRam bool
56
}
67

78
func newMBC0(c *Cartridge) mbc {
8-
return &mbc0{c: c}
9+
hasRam := c.ROM[0x147] != 0
10+
return &mbc0{
11+
c: c,
12+
hasRam: hasRam,
13+
}
914
}
1015

1116
func (m *mbc0) read(addr uint16) uint8 {
1217
switch addr >> 12 {
1318
case 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7:
14-
return m.c.rom[addr]
19+
return m.c.ROM[addr]
1520
case 0xA, 0xB:
16-
return m.c.ram[addr&0x1FFF]
21+
if m.hasRam {
22+
return m.c.ram[addr&0x1FFF]
23+
}
1724
}
1825
return 0xFF
1926
}
2027

2128
func (m *mbc0) write(addr uint16, val uint8) {
2229
switch addr >> 12 {
2330
case 0xA, 0xB:
24-
m.c.ram[addr&0x1FFF] = val
31+
if m.hasRam {
32+
m.c.ram[addr&0x1FFF] = val
33+
}
2534
}
2635
}

‎core/gb/cartridge/mbc1.go

+8-9
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,13 @@
11
package cartridge
22

33
type mbc1 struct {
4-
c *Cartridge
5-
ramEnabled bool
6-
romBank uint8
7-
ramBank uint8
8-
mode uint8
4+
c *Cartridge
5+
ramEnabled bool
6+
romBank, ramBank uint8
7+
mode uint8
98
}
109

11-
func newMBC1(c *Cartridge) mbc {
10+
func newMBC1(c *Cartridge) *mbc1 {
1211
return &mbc1{
1312
c: c,
1413
romBank: 1,
@@ -18,15 +17,15 @@ func newMBC1(c *Cartridge) mbc {
1817
func (m *mbc1) read(addr uint16) uint8 {
1918
switch addr >> 12 {
2019
case 0x0, 0x1, 0x2, 0x3:
21-
return m.c.rom[addr&0x3FFF]
20+
return m.c.ROM[addr&0x3FFF]
2221
case 0x4, 0x5, 0x6, 0x7:
2322
romBank := uint(m.romBank)
2423
if m.mode == 0 {
25-
if len(m.c.rom) >= int(1*MB) {
24+
if len(m.c.ROM) >= int(1*MB) {
2625
romBank |= (uint(m.ramBank) << 5)
2726
}
2827
}
29-
return m.c.rom[(romBank<<14)|uint(addr&0x3FFF)]
28+
return m.c.ROM[(romBank<<14)|uint(addr&0x3FFF)]
3029
case 0xA, 0xB:
3130
if m.ramEnabled {
3231
ramBank := uint(0)

‎core/gb/cartridge/mbc2.go

+52
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
package cartridge
2+
3+
type mbc2 struct {
4+
c *Cartridge
5+
ramEnabled bool
6+
romBank uint8 // 0..15
7+
}
8+
9+
func newMBC2(c *Cartridge) *mbc2 {
10+
return &mbc2{
11+
c: c,
12+
romBank: 1,
13+
}
14+
}
15+
16+
func (m *mbc2) reset() {
17+
m.ramEnabled = false
18+
m.romBank = 1
19+
}
20+
21+
func (m *mbc2) read(addr uint16) uint8 {
22+
switch addr >> 12 {
23+
case 0x0, 0x1, 0x2, 0x3: // ROMバンク0
24+
return m.c.ROM[addr&0x3FFF]
25+
case 0x4, 0x5, 0x6, 0x7: // ROMバンク1..15
26+
return m.c.ROM[(uint(m.romBank)<<14)|uint(addr&0x3FFF)]
27+
case 0xA, 0xB: // RAM
28+
if m.ramEnabled {
29+
return 0xF0 | (m.c.ram[addr&0x1FF] & 0x0F)
30+
}
31+
}
32+
return 0xFF
33+
}
34+
35+
func (m *mbc2) write(addr uint16, val uint8) {
36+
switch addr >> 12 {
37+
case 0x0, 0x1, 0x2, 0x3: // RAM有効化 or ROMバンク切り替え
38+
mode := (addr >> 8) & 0x1
39+
if mode == 0 {
40+
m.ramEnabled = val == 0x0A
41+
} else {
42+
m.romBank = val & 0x0F
43+
if m.romBank == 0 {
44+
m.romBank = 1
45+
}
46+
}
47+
case 0xA, 0xB: // RAM書き込み
48+
if m.ramEnabled {
49+
m.c.ram[addr&0x1FF] = val & 0x0F
50+
}
51+
}
52+
}

‎core/gb/cartridge/mbc3.go

+13-14
Original file line numberDiff line numberDiff line change
@@ -16,12 +16,11 @@ type rtc struct {
1616
}
1717

1818
type mbc3 struct {
19-
c *Cartridge
20-
ramEnabled bool
21-
romBank uint
22-
ramBank uint
23-
rtc rtc
24-
ramBankMax uint
19+
c *Cartridge
20+
ramEnabled bool
21+
romBank, ramBank uint8
22+
rtc rtc
23+
ramBankMax uint8
2524
}
2625

2726
func newMBC3(c *Cartridge) mbc {
@@ -39,19 +38,19 @@ func newMBC3(c *Cartridge) mbc {
3938
// ポケモンクリスタルなどは、MBC30と呼ばれる特殊なMBC3を使っている
4039
// これを見分ける方法は今のところ、カートリッジヘッダのROMサイズとRAMサイズを見るしかない
4140
func (m *mbc3) isMBC30() bool {
42-
return (len(m.c.rom) > int(2*MB)) || (len(m.c.ram) > int(32*KB))
41+
return (len(m.c.ROM) > int(2*MB)) || (len(m.c.ram) > int(32*KB))
4342
}
4443

4544
func (m *mbc3) read(addr uint16) uint8 {
4645
switch addr >> 12 {
4746
case 0x0, 0x1, 0x2, 0x3:
48-
return m.c.rom[addr&0x3FFF]
47+
return m.c.ROM[addr&0x3FFF]
4948
case 0x4, 0x5, 0x6, 0x7:
50-
return m.c.rom[(m.romBank<<14)|uint(addr&0x3FFF)]
49+
return m.c.ROM[(uint(m.romBank)<<14)|uint(addr&0x3FFF)]
5150
case 0xA, 0xB:
5251
if m.ramEnabled {
5352
if m.ramBank < m.ramBankMax {
54-
return m.c.ram[(m.ramBank<<13)|uint(addr&0x1FFF)]
53+
return m.c.ram[(uint(m.ramBank)<<13)|uint(addr&0x1FFF)]
5554
}
5655

5756
// RTC
@@ -81,16 +80,16 @@ func (m *mbc3) write(addr uint16, val uint8) {
8180
case 0x0, 0x1:
8281
m.ramEnabled = (val&0x0F == 0x0A)
8382
case 0x2, 0x3:
84-
m.romBank = uint(val & 0b111_1111)
83+
m.romBank = (val & 0b111_1111)
8584
if m.isMBC30() {
86-
m.romBank = uint(val)
85+
m.romBank = val
8786
}
8887
if m.romBank == 0 {
8988
m.romBank = 1
9089
}
9190
case 0x4, 0x5:
9291
if val <= 0x0C {
93-
m.ramBank = uint(val)
92+
m.ramBank = val
9493
}
9594
case 0x6, 0x7:
9695
// 現在のRTCの値をlatch(保存), これで特定の瞬間のRTCの値を取得できる
@@ -99,7 +98,7 @@ func (m *mbc3) write(addr uint16, val uint8) {
9998
case 0xA, 0xB:
10099
if m.ramEnabled {
101100
if m.ramBank < m.ramBankMax {
102-
m.c.ram[(m.ramBank<<13)|uint(addr&0x1FFF)] = val
101+
m.c.ram[(uint(m.ramBank)<<13)|uint(addr&0x1FFF)] = val
103102
} else {
104103
switch m.ramBank {
105104
case 0xC:

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