main.v

`timescale	1ps / 1ps
////////////////////////////////////////////////////////////////////////////////
//
// Filename:	./main.v
//
// Project:	OpenArty, an entirely open SoC based upon the Arty platform
//
// DO NOT EDIT THIS FILE!
// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
// DO NOT EDIT THIS FILE!
//
// CmdLine:	autofpga autofpga -d -o . allclocks.txt global.txt icape.txt version.txt buserr.txt pic.txt pwrcount.txt spio.txt clrspio.txt rtcgps.txt rtcdate.txt wbuconsole.txt bkram.txt spansion.txt sdram.txt zipmaster.txt mdio.txt enet.txt gps.txt wboledrgb.txt mem_flash_bkram.txt mem_bkram_only.txt mem_sdram_bkram.txt
//
// Creator:	Dan Gisselquist, Ph.D.
//		Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2017-2020, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:	GPL, v3, as defined and found on www.gnu.org,
//		http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype	none
//
//
// Here is a list of defines which may be used, post auto-design
// (not post-build), to turn particular peripherals (and bus masters)
// on and off.  In particular, to turn off support for a particular
// design component, just comment out its respective `define below.
//
// These lines are taken from the respective @ACCESS tags for each of our
// components.  If a component doesn't have an @ACCESS tag, it will not
// be listed here.
//
// First, the independent access fields for any bus masters
`define	ALLCLOCKS_PRESENT
`define	WBUBUS_MASTER
// And then for the independent peripherals
`define	GPSTRK_ACCESS
`define	OLEDRGB_ACCESS
`define	INCLUDE_ZIPCPU
`define	CFG_ACCESS
`define	GPSUART_ACCESS
`define	BUSPIC_ACCESS
`define	FLASH_ACCESS
`define	BUSCONSOLE_ACCESS
`define	CLRLED_ACCESS
`define	SPIO_ACCESS
`define	RTC_ACCESS
`define	BKRAM_ACCESS
`define	PWRCOUNT_ACCESS
`define	NETCTRL_ACCESS
//
//
// The list of those things that have @DEPENDS tags
//
//
//
// Dependencies
// Any core with both an @ACCESS and a @DEPENDS tag will show up here.
// The @DEPENDS tag will turn into a series of ifdef's, with the @ACCESS
// being defined only if all of the ifdef's are true//
`ifdef	FLASH_ACCESS
`define	FLASHCFG_ACCESS
`endif	// FLASH_ACCESS
`ifdef	RTC_ACCESS
`define	RTCDATE_ACCESS
`endif	// RTC_ACCESS
`ifdef	ALLCLOCKS_PRESENT
`define	ETHERNET_ACCESS
`endif	// ALLCLOCKS_PRESENT
`ifdef	ALLCLOCKS_PRESENT
`define	SDRAM_ACCESS
`endif	// ALLCLOCKS_PRESENT
//
// End of dependency list
//
//
//
// Any include files
//
// These are drawn from anything with a MAIN.INCLUDE definition.
//
//
// Finally, we define our main module itself.  We start with the list of
// I/O ports, or wires, passed into (or out of) the main function.
//
// These fields are copied verbatim from the respective I/O port lists,
// from the fields given by @MAIN.PORTLIST
//
module	main(i_clk, i_reset,
		// The GPS 1PPS signal port
		i_gps_pps,
		// Ethernet control (packets) lines
		// i_eth_tx_clk and i_eth_rx_clk come from allclocks.txt
		o_eth_rstn, i_eth_col, i_eth_crs, i_eth_rx_dv,
			i_eth_rxd, i_eth_rxerr,
		o_eth_tx_en, o_eth_txd,
		// OLEDRGB control interface (roughly SPI)
		o_oledrgb_sck, o_oledrgb_cs_n, o_oledrgb_mosi,
		o_oledrgb_dcn, o_oledrgb_reset_n,
		o_oledrgb_vccen, o_oledrgb_pmoden,
		i_eth_rx_clk,
		// SDRAM ports
		o_sdram_cyc, o_sdram_stb, o_sdram_we,
				o_sdram_addr, o_sdram_data, o_sdram_sel,
			i_sdram_stall, i_sdram_ack, i_sdram_data,
			i_sdram_err,
		i_cpu_reset,
		// The GPS-UART
		i_gpsu_rx, o_gpsu_tx,
		// The Universal QSPI Flash
		o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
		i_eth_tx_clk,
		// UART/host to wishbone interface
		i_wbu_uart_rx, o_wbu_uart_tx,
		no_clk,
		// CLRLED interface
		o_clr_ledr, o_clr_ledg, o_clr_ledb,
		// SPIO interface
		i_sw, i_btn, o_led,
		// The ethernet MDIO wires
		o_mdclk, o_mdio, o_mdwe, i_mdio);
//
// Any parameter definitions
//
// These are drawn from anything with a MAIN.PARAM definition.
// As they aren't connected to the toplevel at all, it would
// be best to use localparam over parameter, but here we don't
// check
	localparam [31:0] GPSCLOCK_DEFAULT_STEP = 32'had373298;
	//
	//
	// Variables/definitions needed by the ZipCPU BUS master
	//
	//
	// A 32-bit address indicating where the ZipCPU should start running
	// from
`ifdef	BKROM_ACCESS
	localparam	RESET_ADDRESS = @$(/bkrom.BASE);
`else
`ifdef	FLASH_ACCESS
	localparam	RESET_ADDRESS = 155189248;
`else
	localparam	RESET_ADDRESS = 134217728;
`endif	// FLASH_ACCESS
`endif	// BKROM_ACCESS
	//
	// The number of valid bits on the bus
	localparam	ZIP_ADDRESS_WIDTH = 27; // Zip-CPU address width
	//
	// Number of ZipCPU interrupts
	localparam	ZIP_INTS = 16;
	//
	// ZIP_START_HALTED
	//
	// A boolean, indicating whether or not the ZipCPU be halted on startup?
`ifdef	BKROM_ACCESS
	localparam	ZIP_START_HALTED=1'b0;
`else
	localparam	ZIP_START_HALTED=1'b1;
`endif
	localparam	ICAPE_LGDIV=3;
	//
	// WBUBUS parameters
	//
	// Baudrate :   1000000
	// Clock    :  81247960
	localparam [23:0] BUSUART = 24'h51;	//   1000000 baud
	localparam	DBGBUSBITS = $clog2(BUSUART);
	//
	// Maximum command is 6 bytes, where each byte takes 10 baud clocks
	// and each baud clock requires DBGBUSBITS to represent.  Here,
	// we'll add one more for good measure.
	localparam	DBGBUSWATCHDOG_RAW = DBGBUSBITS + 9;
	localparam	DBGBUSWATCHDOG = (DBGBUSWATCHDOG_RAW > 19)
				? DBGBUSWATCHDOG_RAW : 19;
//
// The next step is to declare all of the various ports that were just
// listed above.  
//
// The following declarations are taken from the values of the various
// @MAIN.IODECL keys.
//
	input	wire		i_clk;
	// verilator lint_off UNUSED
	input	wire		i_reset;
	// verilator lint_on UNUSED
	//The GPS Clock
	input	wire		i_gps_pps;
	// Ethernet control
	output	wire		o_eth_rstn;
	input	wire		i_eth_col, i_eth_crs, i_eth_rx_dv;
	input	wire	[3:0]	i_eth_rxd;
	input	wire		i_eth_rxerr;
	output	wire		o_eth_tx_en;
	output	wire	[3:0]	o_eth_txd;
	// OLEDRGB interface
	output	wire		o_oledrgb_sck, o_oledrgb_cs_n,
				o_oledrgb_mosi,
				o_oledrgb_dcn, o_oledrgb_reset_n,
				o_oledrgb_vccen, o_oledrgb_pmoden;
	// With no ethernet included, this clock will be unused
	// Verilator lint_off UNUSED
	input	wire	i_eth_rx_clk;
	// Verilator lint_on  UNUSED
	// SDRAM I/O declarations
	output	wire			o_sdram_cyc,
					o_sdram_stb, o_sdram_we;
	output	wire	[(27-1):0]	o_sdram_addr;
	output	wire	[(32-1):0]	o_sdram_data;
	output	wire	[(32/8)-1:0]	o_sdram_sel;
	//
	input	wire			i_sdram_ack;
	input	wire			i_sdram_stall;
	input	wire	[(32-1):0]	i_sdram_data;
	// Verilator lint_off UNUSED
	input	wire			i_sdram_err;
	// Verilator lint_on  UNUSED
	input	wire		i_cpu_reset;
	input	wire		i_gpsu_rx;
	output	wire		o_gpsu_tx;
	// The Universal QSPI flash
	output	wire		o_qspi_cs_n, o_qspi_sck;
	output	wire	[3:0]	o_qspi_dat;
	input	wire	[3:0]	i_qspi_dat;
	output	wire	[1:0]	o_qspi_mod;
	// With no ethernet included, this clock will be unused
	// Verilator lint_off UNUSED
	input	wire	i_eth_tx_clk;
	// Verilator lint_on  UNUSED
	input	wire		i_wbu_uart_rx;
	output	wire		o_wbu_uart_tx;
	// This clock is unused in main, AutoFPGA still wants it though
	// Verilator lint_off UNUSED
	input	wire	no_clk;
	// Verilator lint_on  UNUSED
	// SPIO interface
	output	wire	[3:0]	o_clr_ledr, o_clr_ledg, o_clr_ledb;
	// SPIO interface
	input	wire	[4-1:0]	i_sw;
	input	wire	[4-1:0]	i_btn;
	output	wire	[4-1:0]	o_led;
	// Ethernet control (MDIO)
	output	wire		o_mdclk, o_mdio, o_mdwe;
	input	wire		i_mdio;
	// Make Verilator happy ... defining bus wires for lots of components
	// often ends up with unused wires lying around.  We'll turn off
	// Ver1lator's lint warning here that checks for unused wires.
	// verilator lint_off UNUSED



	//
	// Declaring interrupt lines
	//
	// These declarations come from the various components values
	// given under the @INT.<interrupt name>.WIRE key.
	//
	wire	ck_pps;	// gck.INT.PPS.WIRE
	wire	nettx_int;	// netp.INT.NETTX.WIRE
	wire	netrx_int;	// netp.INT.NETRX.WIRE
	wire	oledrgb_int;	// oledrgb.INT.OLED.WIRE
	wire	zip_cpu_int;	// zip.INT.ZIP.WIRE
	wire	gpsutx_int;	// gpsu.INT.GPSTX.WIRE
	wire	gpsutxf_int;	// gpsu.INT.GPSTXF.WIRE
	wire	gpsurx_int;	// gpsu.INT.GPSRX.WIRE
	wire	gpsurxf_int;	// gpsu.INT.GPSRXF.WIRE
	wire	w_bus_int;	// buspic.INT.BUS.WIRE
	wire	uarttxf_int;	// uart.INT.UARTTXF.WIRE
	wire	uartrxf_int;	// uart.INT.UARTRXF.WIRE
	wire	uarttx_int;	// uart.INT.UARTTX.WIRE
	wire	uartrx_int;	// uart.INT.UARTRX.WIRE
	wire	spio_int;	// spio.INT.SPIO.WIRE
	wire	rtc_int;	// rtc.INT.RTC.WIRE


	//
	// Component declarations
	//
	// These declarations come from the @MAIN.DEFNS keys found in the
	// various components comprising the design.
	//
	wire	gps_pps, gps_led, gps_locked, gps_tracking;
	wire	[63:0]	gps_now, gps_err, gps_step;
	wire	[1:0]	gps_dbg_tick;
	wire	[31:0]	gps_dbg;
	wire	tb_pps;
	//
	wire	[31:0]	netp_debug;
`include "builddate.v"
	// ZipSystem/ZipCPU connection definitions
	// All we define here is a set of scope wires
	wire	[31:0]	zip_debug;
	wire		zip_trigger;
	wire	[ZIP_INTS-1:0] zip_int_vector;
	wire	w_gpsu_cts_n, w_gpsu_rts_n;
	assign	w_gpsu_cts_n=1'b1;
// BUILDTIME doesnt need to include builddate.v a second time
// `include "builddate.v"
	// Definitions for the flash debug port
	wire		flash_dbg_trigger;
	wire	[31:0]	flash_debug;
`ifndef	GPSTRK_ACCESS
	reg	[31:0]	r_subseconds_data;
`endif
	reg	[28-1:0]	r_buserr_addr;
	//
	//
	// UART interface
	//
	//
	wire	[7:0]	wbu_rx_data, wbu_tx_data;
	wire		wbu_rx_stb;
	wire		wbu_tx_stb, wbu_tx_busy;

	wire	w_ck_uart, w_uart_tx;
	// Definitions for the WB-UART converter.  We really only need one
	// (more) non-bus wire--one to use to select if we are interacting
	// with the ZipCPU or not.
	wire	[0:0]	wbubus_dbg;
`ifndef	INCLUDE_ZIPCPU
	//
	// The bus-console depends upon the zip_dbg wires.  If there is no
	// ZipCPU defining them, we'll need to define them here anyway.
	//
	wire		zip_dbg_stall, zip_dbg_ack;
	wire	[31:0]	zip_dbg_data;
`endif
	// Console definitions
	wire		w_console_rx_stb, w_console_tx_stb, w_console_busy;
	wire	[6:0]	w_console_rx_data, w_console_tx_data;
	wire	[31:0]	uart_debug;
`ifndef	PWRCOUNT_ACCESS
	reg	[8:0]	clrled_counter;
`else
	wire	[8:0]	clrled_counter;
`endif
	wire	[31:0]	clrled0_data, clrled1_data,
			clrled2_data, clrled3_data;
	reg		r_clrled_ack;
	reg	[31:0]	r_clrled_data;
	// Definitions in support of the GPS driven RTC
	// This clock step is designed to match 81247960 Hz
	localparam	[31:0]	RTC_CLKSTEP = 32'h0034dcca;
	wire	rtc_ppd, rtc_pps;
	reg	r_rtc_ack;
	reg	[31:0]	r_pwrcount_data;


	//
	// Declaring interrupt vector wires
	//
	// These declarations come from the various components having
	// PIC and PIC.MAX keys.
	//
	wire	[14:0]	bus_int_vector;
	wire	[14:0]	alt_int_vector;
	wire	[14:0]	sys_int_vector;
	//
	//
	// Define bus wires
	//
	//

	// Bus wb
	// Wishbone definitions for bus wb, component zip
	// Verilator lint_off UNUSED
	wire		wb_zip_cyc, wb_zip_stb, wb_zip_we;
	wire	[26:0]	wb_zip_addr;
	wire	[31:0]	wb_zip_data;
	wire	[3:0]	wb_zip_sel;
	wire		wb_zip_stall, wb_zip_ack, wb_zip_err;
	wire	[31:0]	wb_zip_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb, component wbu_arbiter
	// Verilator lint_off UNUSED
	wire		wb_wbu_arbiter_cyc, wb_wbu_arbiter_stb, wb_wbu_arbiter_we;
	wire	[26:0]	wb_wbu_arbiter_addr;
	wire	[31:0]	wb_wbu_arbiter_data;
	wire	[3:0]	wb_wbu_arbiter_sel;
	wire		wb_wbu_arbiter_stall, wb_wbu_arbiter_ack, wb_wbu_arbiter_err;
	wire	[31:0]	wb_wbu_arbiter_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(SIO), component buildtime
	// Verilator lint_off UNUSED
	wire		wb_buildtime_cyc, wb_buildtime_stb, wb_buildtime_we;
	wire	[26:0]	wb_buildtime_addr;
	wire	[31:0]	wb_buildtime_data;
	wire	[3:0]	wb_buildtime_sel;
	wire		wb_buildtime_stall, wb_buildtime_ack, wb_buildtime_err;
	wire	[31:0]	wb_buildtime_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(SIO), component buserr
	// Verilator lint_off UNUSED
	wire		wb_buserr_cyc, wb_buserr_stb, wb_buserr_we;
	wire	[26:0]	wb_buserr_addr;
	wire	[31:0]	wb_buserr_data;
	wire	[3:0]	wb_buserr_sel;
	wire		wb_buserr_stall, wb_buserr_ack, wb_buserr_err;
	wire	[31:0]	wb_buserr_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(SIO), component buspic
	// Verilator lint_off UNUSED
	wire		wb_buspic_cyc, wb_buspic_stb, wb_buspic_we;
	wire	[26:0]	wb_buspic_addr;
	wire	[31:0]	wb_buspic_data;
	wire	[3:0]	wb_buspic_sel;
	wire		wb_buspic_stall, wb_buspic_ack, wb_buspic_err;
	wire	[31:0]	wb_buspic_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(SIO), component pwrcount
	// Verilator lint_off UNUSED
	wire		wb_pwrcount_cyc, wb_pwrcount_stb, wb_pwrcount_we;
	wire	[26:0]	wb_pwrcount_addr;
	wire	[31:0]	wb_pwrcount_data;
	wire	[3:0]	wb_pwrcount_sel;
	wire		wb_pwrcount_stall, wb_pwrcount_ack, wb_pwrcount_err;
	wire	[31:0]	wb_pwrcount_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(SIO), component rtcdate
	// Verilator lint_off UNUSED
	wire		wb_rtcdate_cyc, wb_rtcdate_stb, wb_rtcdate_we;
	wire	[26:0]	wb_rtcdate_addr;
	wire	[31:0]	wb_rtcdate_data;
	wire	[3:0]	wb_rtcdate_sel;
	wire		wb_rtcdate_stall, wb_rtcdate_ack, wb_rtcdate_err;
	wire	[31:0]	wb_rtcdate_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(SIO), component spio
	// Verilator lint_off UNUSED
	wire		wb_spio_cyc, wb_spio_stb, wb_spio_we;
	wire	[26:0]	wb_spio_addr;
	wire	[31:0]	wb_spio_data;
	wire	[3:0]	wb_spio_sel;
	wire		wb_spio_stall, wb_spio_ack, wb_spio_err;
	wire	[31:0]	wb_spio_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(SIO), component subseconds
	// Verilator lint_off UNUSED
	wire		wb_subseconds_cyc, wb_subseconds_stb, wb_subseconds_we;
	wire	[26:0]	wb_subseconds_addr;
	wire	[31:0]	wb_subseconds_data;
	wire	[3:0]	wb_subseconds_sel;
	wire		wb_subseconds_stall, wb_subseconds_ack, wb_subseconds_err;
	wire	[31:0]	wb_subseconds_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(SIO), component version
	// Verilator lint_off UNUSED
	wire		wb_version_cyc, wb_version_stb, wb_version_we;
	wire	[26:0]	wb_version_addr;
	wire	[31:0]	wb_version_data;
	wire	[3:0]	wb_version_sel;
	wire		wb_version_stall, wb_version_ack, wb_version_err;
	wire	[31:0]	wb_version_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(DIO), component clrled
	// Verilator lint_off UNUSED
	wire		wb_clrled_cyc, wb_clrled_stb, wb_clrled_we;
	wire	[26:0]	wb_clrled_addr;
	wire	[31:0]	wb_clrled_data;
	wire	[3:0]	wb_clrled_sel;
	wire		wb_clrled_stall, wb_clrled_ack, wb_clrled_err;
	wire	[31:0]	wb_clrled_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(DIO), component gck
	// Verilator lint_off UNUSED
	wire		wb_gck_cyc, wb_gck_stb, wb_gck_we;
	wire	[26:0]	wb_gck_addr;
	wire	[31:0]	wb_gck_data;
	wire	[3:0]	wb_gck_sel;
	wire		wb_gck_stall, wb_gck_ack, wb_gck_err;
	wire	[31:0]	wb_gck_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(DIO), component oledrgb
	// Verilator lint_off UNUSED
	wire		wb_oledrgb_cyc, wb_oledrgb_stb, wb_oledrgb_we;
	wire	[26:0]	wb_oledrgb_addr;
	wire	[31:0]	wb_oledrgb_data;
	wire	[3:0]	wb_oledrgb_sel;
	wire		wb_oledrgb_stall, wb_oledrgb_ack, wb_oledrgb_err;
	wire	[31:0]	wb_oledrgb_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(DIO), component gtb
	// Verilator lint_off UNUSED
	wire		wb_gtb_cyc, wb_gtb_stb, wb_gtb_we;
	wire	[26:0]	wb_gtb_addr;
	wire	[31:0]	wb_gtb_data;
	wire	[3:0]	wb_gtb_sel;
	wire		wb_gtb_stall, wb_gtb_ack, wb_gtb_err;
	wire	[31:0]	wb_gtb_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(DIO), component netp
	// Verilator lint_off UNUSED
	wire		wb_netp_cyc, wb_netp_stb, wb_netp_we;
	wire	[26:0]	wb_netp_addr;
	wire	[31:0]	wb_netp_data;
	wire	[3:0]	wb_netp_sel;
	wire		wb_netp_stall, wb_netp_ack, wb_netp_err;
	wire	[31:0]	wb_netp_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(DIO), component rtc
	// Verilator lint_off UNUSED
	wire		wb_rtc_cyc, wb_rtc_stb, wb_rtc_we;
	wire	[26:0]	wb_rtc_addr;
	wire	[31:0]	wb_rtc_data;
	wire	[3:0]	wb_rtc_sel;
	wire		wb_rtc_stall, wb_rtc_ack, wb_rtc_err;
	wire	[31:0]	wb_rtc_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb(DIO), component wb_sio
	// Verilator lint_off UNUSED
	wire		wb_sio_cyc, wb_sio_stb, wb_sio_we;
	wire	[26:0]	wb_sio_addr;
	wire	[31:0]	wb_sio_data;
	wire	[3:0]	wb_sio_sel;
	wire		wb_sio_stall, wb_sio_ack, wb_sio_err;
	wire	[31:0]	wb_sio_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb, component flashcfg
	// Verilator lint_off UNUSED
	wire		wb_flashcfg_cyc, wb_flashcfg_stb, wb_flashcfg_we;
	wire	[26:0]	wb_flashcfg_addr;
	wire	[31:0]	wb_flashcfg_data;
	wire	[3:0]	wb_flashcfg_sel;
	wire		wb_flashcfg_stall, wb_flashcfg_ack, wb_flashcfg_err;
	wire	[31:0]	wb_flashcfg_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb, component gpsu
	// Verilator lint_off UNUSED
	wire		wb_gpsu_cyc, wb_gpsu_stb, wb_gpsu_we;
	wire	[26:0]	wb_gpsu_addr;
	wire	[31:0]	wb_gpsu_data;
	wire	[3:0]	wb_gpsu_sel;
	wire		wb_gpsu_stall, wb_gpsu_ack, wb_gpsu_err;
	wire	[31:0]	wb_gpsu_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb, component uart
	// Verilator lint_off UNUSED
	wire		wb_uart_cyc, wb_uart_stb, wb_uart_we;
	wire	[26:0]	wb_uart_addr;
	wire	[31:0]	wb_uart_data;
	wire	[3:0]	wb_uart_sel;
	wire		wb_uart_stall, wb_uart_ack, wb_uart_err;
	wire	[31:0]	wb_uart_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb, component cfg
	// Verilator lint_off UNUSED
	wire		wb_cfg_cyc, wb_cfg_stb, wb_cfg_we;
	wire	[26:0]	wb_cfg_addr;
	wire	[31:0]	wb_cfg_data;
	wire	[3:0]	wb_cfg_sel;
	wire		wb_cfg_stall, wb_cfg_ack, wb_cfg_err;
	wire	[31:0]	wb_cfg_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb, component mdio
	// Verilator lint_off UNUSED
	wire		wb_mdio_cyc, wb_mdio_stb, wb_mdio_we;
	wire	[26:0]	wb_mdio_addr;
	wire	[31:0]	wb_mdio_data;
	wire	[3:0]	wb_mdio_sel;
	wire		wb_mdio_stall, wb_mdio_ack, wb_mdio_err;
	wire	[31:0]	wb_mdio_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb, component wb_dio
	// Verilator lint_off UNUSED
	wire		wb_dio_cyc, wb_dio_stb, wb_dio_we;
	wire	[26:0]	wb_dio_addr;
	wire	[31:0]	wb_dio_data;
	wire	[3:0]	wb_dio_sel;
	wire		wb_dio_stall, wb_dio_ack, wb_dio_err;
	wire	[31:0]	wb_dio_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb, component netb
	// Verilator lint_off UNUSED
	wire		wb_netb_cyc, wb_netb_stb, wb_netb_we;
	wire	[26:0]	wb_netb_addr;
	wire	[31:0]	wb_netb_data;
	wire	[3:0]	wb_netb_sel;
	wire		wb_netb_stall, wb_netb_ack, wb_netb_err;
	wire	[31:0]	wb_netb_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb, component bkram
	// Verilator lint_off UNUSED
	wire		wb_bkram_cyc, wb_bkram_stb, wb_bkram_we;
	wire	[26:0]	wb_bkram_addr;
	wire	[31:0]	wb_bkram_data;
	wire	[3:0]	wb_bkram_sel;
	wire		wb_bkram_stall, wb_bkram_ack, wb_bkram_err;
	wire	[31:0]	wb_bkram_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb, component flash
	// Verilator lint_off UNUSED
	wire		wb_flash_cyc, wb_flash_stb, wb_flash_we;
	wire	[26:0]	wb_flash_addr;
	wire	[31:0]	wb_flash_data;
	wire	[3:0]	wb_flash_sel;
	wire		wb_flash_stall, wb_flash_ack, wb_flash_err;
	wire	[31:0]	wb_flash_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wb, component sdram
	// Verilator lint_off UNUSED
	wire		wb_sdram_cyc, wb_sdram_stb, wb_sdram_we;
	wire	[26:0]	wb_sdram_addr;
	wire	[31:0]	wb_sdram_data;
	wire	[3:0]	wb_sdram_sel;
	wire		wb_sdram_stall, wb_sdram_ack, wb_sdram_err, sdram_err;
	assign		wb_sdram_err = sdram_err;
	wire	[31:0]	wb_sdram_idata;
	// Verilator lint_on UNUSED
	// Bus wbu
	// Wishbone definitions for bus wbu, component wbu
	// Verilator lint_off UNUSED
	wire		wbu_wbu_cyc, wbu_wbu_stb, wbu_wbu_we;
	wire	[27:0]	wbu_wbu_addr;
	wire	[31:0]	wbu_wbu_data;
	wire	[3:0]	wbu_wbu_sel;
	wire		wbu_wbu_stall, wbu_wbu_ack, wbu_wbu_err;
	wire	[31:0]	wbu_wbu_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wbu, component wbu_arbiter
	// Verilator lint_off UNUSED
	wire		wbu_wbu_arbiter_cyc, wbu_wbu_arbiter_stb, wbu_wbu_arbiter_we;
	wire	[27:0]	wbu_wbu_arbiter_addr;
	wire	[31:0]	wbu_wbu_arbiter_data;
	wire	[3:0]	wbu_wbu_arbiter_sel;
	wire		wbu_wbu_arbiter_stall, wbu_wbu_arbiter_ack, wbu_wbu_arbiter_err;
	wire	[31:0]	wbu_wbu_arbiter_idata;
	// Verilator lint_on UNUSED
	// Wishbone definitions for bus wbu, component zip
	// Verilator lint_off UNUSED
	wire		wbu_zip_cyc, wbu_zip_stb, wbu_zip_we;
	wire	[27:0]	wbu_zip_addr;
	wire	[31:0]	wbu_zip_data;
	wire	[3:0]	wbu_zip_sel;
	wire		wbu_zip_stall, wbu_zip_ack, wbu_zip_err;
	wire	[31:0]	wbu_zip_idata;
	// Verilator lint_on UNUSED

	//
	// Peripheral address decoding
	//
	//
	// BUS-LOGIC for wb
	//
	//
	// wb Bus logic to handle SINGLE slaves
	//
	reg		r_wb_sio_ack;
	reg	[31:0]	r_wb_sio_data;

	assign	wb_sio_stall = 1'b0;

	initial r_wb_sio_ack = 1'b0;
	always	@(posedge i_clk)
		r_wb_sio_ack <= (wb_sio_stb);
	assign	wb_sio_ack = r_wb_sio_ack;

	always	@(posedge i_clk)
	casez( wb_sio_addr[2:0] )
	3'h0: r_wb_sio_data <= wb_buildtime_idata;
	3'h1: r_wb_sio_data <= wb_buserr_idata;
	3'h2: r_wb_sio_data <= wb_buspic_idata;
	3'h3: r_wb_sio_data <= wb_pwrcount_idata;
	3'h4: r_wb_sio_data <= wb_rtcdate_idata;
	3'h5: r_wb_sio_data <= wb_spio_idata;
	3'h6: r_wb_sio_data <= wb_subseconds_idata;
	3'h7: r_wb_sio_data <= wb_version_idata;
	// No default: SIZE = 8, [Guru meditation: 3 != 3]
	endcase
	assign	wb_sio_idata = r_wb_sio_data;


	//
	// Now to translate this logic to the various SIO slaves
	//
	// In this case, the SIO bus has the prefix wb_sio
	// and all of the slaves have various wires beginning
	// with their own respective bus prefixes.
	// Our goal here is to make certain that all of
	// the slave bus inputs match the SIO bus wires
	assign	wb_buildtime_cyc = wb_sio_cyc;
	assign	wb_buildtime_stb = wb_sio_stb && (wb_sio_addr[ 2: 0] ==  3'h0);  // 0x0000000
	assign	wb_buildtime_we  = wb_sio_we;
	assign	wb_buildtime_data= wb_sio_data;
	assign	wb_buildtime_sel = wb_sio_sel;
	assign	wb_buserr_cyc = wb_sio_cyc;
	assign	wb_buserr_stb = wb_sio_stb && (wb_sio_addr[ 2: 0] ==  3'h1);  // 0x0000004
	assign	wb_buserr_we  = wb_sio_we;
	assign	wb_buserr_data= wb_sio_data;
	assign	wb_buserr_sel = wb_sio_sel;
	assign	wb_buspic_cyc = wb_sio_cyc;
	assign	wb_buspic_stb = wb_sio_stb && (wb_sio_addr[ 2: 0] ==  3'h2);  // 0x0000008
	assign	wb_buspic_we  = wb_sio_we;
	assign	wb_buspic_data= wb_sio_data;
	assign	wb_buspic_sel = wb_sio_sel;
	assign	wb_pwrcount_cyc = wb_sio_cyc;
	assign	wb_pwrcount_stb = wb_sio_stb && (wb_sio_addr[ 2: 0] ==  3'h3);  // 0x000000c
	assign	wb_pwrcount_we  = wb_sio_we;
	assign	wb_pwrcount_data= wb_sio_data;
	assign	wb_pwrcount_sel = wb_sio_sel;
	assign	wb_rtcdate_cyc = wb_sio_cyc;
	assign	wb_rtcdate_stb = wb_sio_stb && (wb_sio_addr[ 2: 0] ==  3'h4);  // 0x0000010
	assign	wb_rtcdate_we  = wb_sio_we;
	assign	wb_rtcdate_data= wb_sio_data;
	assign	wb_rtcdate_sel = wb_sio_sel;
	assign	wb_spio_cyc = wb_sio_cyc;
	assign	wb_spio_stb = wb_sio_stb && (wb_sio_addr[ 2: 0] ==  3'h5);  // 0x0000014
	assign	wb_spio_we  = wb_sio_we;
	assign	wb_spio_data= wb_sio_data;
	assign	wb_spio_sel = wb_sio_sel;
	assign	wb_subseconds_cyc = wb_sio_cyc;
	assign	wb_subseconds_stb = wb_sio_stb && (wb_sio_addr[ 2: 0] ==  3'h6);  // 0x0000018
	assign	wb_subseconds_we  = wb_sio_we;
	assign	wb_subseconds_data= wb_sio_data;
	assign	wb_subseconds_sel = wb_sio_sel;
	assign	wb_version_cyc = wb_sio_cyc;
	assign	wb_version_stb = wb_sio_stb && (wb_sio_addr[ 2: 0] ==  3'h7);  // 0x000001c
	assign	wb_version_we  = wb_sio_we;
	assign	wb_version_data= wb_sio_data;
	assign	wb_version_sel = wb_sio_sel;
	//
	// wb Bus logic to handle 7 DOUBLE slaves
	//
	//
	reg	[1:0]	r_wb_dio_ack;
	// # dlist = 7, nextlg(#dlist) = 3
	reg	[2:0]	r_wb_dio_bus_select;
	reg	[31:0]	r_wb_dio_data;

	// DOUBLE peripherals are not allowed to stall.
	assign	wb_dio_stall = 1'b0;

	// DOUBLE peripherals return their acknowledgments in two
	// clocks--always, allowing us to collect this logic together
	// in a slave independent manner.  Here, the acknowledgment
	// is treated as a two stage shift register, cleared on any
	// reset, or any time the cycle line drops.  (Dropping the
	// cycle line aborts the transaction.)
	initial	r_wb_dio_ack = 0;
	always	@(posedge i_clk)
	if (i_reset || !wb_dio_cyc)
		r_wb_dio_ack <= 0;
	else
		r_wb_dio_ack <= { r_wb_dio_ack[0], (wb_dio_stb) };
	assign	wb_dio_ack = r_wb_dio_ack[1];

	// Since it costs us two clocks to go through this
	// logic, we'll take one of those clocks here to set
	// a selection index, and then on the next clock we'll
	// use this index to select from among the vaious
	// possible bus return values
	always @(posedge i_clk)
	casez(wb_dio_addr[5:3])
	3'b000: r_wb_dio_bus_select <= 3'd0;
	3'b001: r_wb_dio_bus_select <= 3'd1;
	3'b010: r_wb_dio_bus_select <= 3'd2;
	3'b011: r_wb_dio_bus_select <= 3'd3;
	3'b100: r_wb_dio_bus_select <= 3'd4;
	3'b101: r_wb_dio_bus_select <= 3'd5;
	3'b110: r_wb_dio_bus_select <= 3'd6;
	default: r_wb_dio_bus_select <= 0;
	endcase

	always	@(posedge i_clk)
	casez(r_wb_dio_bus_select)
	3'd0: r_wb_dio_data <= wb_clrled_idata;
	3'd1: r_wb_dio_data <= wb_gck_idata;
	3'd2: r_wb_dio_data <= wb_oledrgb_idata;
	3'd3: r_wb_dio_data <= wb_gtb_idata;
	3'd4: r_wb_dio_data <= wb_netp_idata;
	3'd5: r_wb_dio_data <= wb_rtc_idata;
	3'd6: r_wb_dio_data <= wb_sio_idata;
	default: r_wb_dio_data <= wb_sio_idata;
	endcase

	assign	wb_dio_idata = r_wb_dio_data;

	assign	wb_clrled_cyc = wb_dio_cyc;
	assign	wb_clrled_stb = wb_dio_stb && ((wb_dio_addr[ 5: 3] &  3'h7) ==  3'h0);  // 0x0000000
	assign	wb_clrled_we  = wb_dio_we;
	assign	wb_clrled_addr= wb_dio_addr;
	assign	wb_clrled_data= wb_dio_data;
	assign	wb_clrled_sel = wb_dio_sel;
	assign	wb_gck_cyc = wb_dio_cyc;
	assign	wb_gck_stb = wb_dio_stb && ((wb_dio_addr[ 5: 3] &  3'h7) ==  3'h1);  // 0x0000020 - 0x000002f
	assign	wb_gck_we  = wb_dio_we;
	assign	wb_gck_addr= wb_dio_addr;
	assign	wb_gck_data= wb_dio_data;
	assign	wb_gck_sel = wb_dio_sel;
	assign	wb_oledrgb_cyc = wb_dio_cyc;
	assign	wb_oledrgb_stb = wb_dio_stb && ((wb_dio_addr[ 5: 3] &  3'h7) ==  3'h2);  // 0x0000040 - 0x000004f
	assign	wb_oledrgb_we  = wb_dio_we;
	assign	wb_oledrgb_addr= wb_dio_addr;
	assign	wb_oledrgb_data= wb_dio_data;
	assign	wb_oledrgb_sel = wb_dio_sel;
	assign	wb_gtb_cyc = wb_dio_cyc;
	assign	wb_gtb_stb = wb_dio_stb && ((wb_dio_addr[ 5: 3] &  3'h7) ==  3'h3);  // 0x0000060 - 0x000007f
	assign	wb_gtb_we  = wb_dio_we;
	assign	wb_gtb_addr= wb_dio_addr;
	assign	wb_gtb_data= wb_dio_data;
	assign	wb_gtb_sel = wb_dio_sel;
	assign	wb_netp_cyc = wb_dio_cyc;
	assign	wb_netp_stb = wb_dio_stb && ((wb_dio_addr[ 5: 3] &  3'h7) ==  3'h4);  // 0x0000080 - 0x000009f
	assign	wb_netp_we  = wb_dio_we;
	assign	wb_netp_addr= wb_dio_addr;
	assign	wb_netp_data= wb_dio_data;
	assign	wb_netp_sel = wb_dio_sel;
	assign	wb_rtc_cyc = wb_dio_cyc;
	assign	wb_rtc_stb = wb_dio_stb && ((wb_dio_addr[ 5: 3] &  3'h7) ==  3'h5);  // 0x00000a0 - 0x00000bf
	assign	wb_rtc_we  = wb_dio_we;
	assign	wb_rtc_addr= wb_dio_addr;
	assign	wb_rtc_data= wb_dio_data;
	assign	wb_rtc_sel = wb_dio_sel;
	assign	wb_sio_cyc = wb_dio_cyc;
	assign	wb_sio_stb = wb_dio_stb && ((wb_dio_addr[ 5: 3] &  3'h7) ==  3'h6);  // 0x00000c0 - 0x00000df
	assign	wb_sio_we  = wb_dio_we;
	assign	wb_sio_addr= wb_dio_addr;
	assign	wb_sio_data= wb_dio_data;
	assign	wb_sio_sel = wb_dio_sel;
	assign	wb_flashcfg_err= 1'b0;
	assign	wb_gpsu_err= 1'b0;
	assign	wb_uart_err= 1'b0;
	assign	wb_cfg_err= 1'b0;
	assign	wb_mdio_err= 1'b0;
	assign	wb_dio_err= 1'b0;
	assign	wb_netb_err= 1'b0;
	assign	wb_bkram_err= 1'b0;
	assign	wb_flash_err= 1'b0;
	// info: @ERROR.WIRE sdram_err != wb_sdram
	// info: @ERROR.WIRE for sdram, = sdram_err, doesn't match the buses wire wb_sdram_err
	assign	wb_sdram_err = sdram_err;
	//
	// Connect the wb bus components together using the wbxbar()
	//
	//
	wbxbar #(
		.NM(2), .NS(10), .AW(27), .DW(32),
		.SLAVE_ADDR({
			// Address width    = 27
			// Address LSBs     = 2
			// Slave name width = 8
			{ 27'h4000000 }, //    sdram: 0x10000000
			{ 27'h2400000 }, //    flash: 0x09000000
			{ 27'h2000000 }, //    bkram: 0x08000000
			{ 27'h1c00000 }, //     netb: 0x07000000
			{ 27'h1800000 }, //   wb_dio: 0x06000000
			{ 27'h1400000 }, //     mdio: 0x05000000
			{ 27'h1000000 }, //      cfg: 0x04000000
			{ 27'h0c00000 }, //     uart: 0x03000000
			{ 27'h0800000 }, //     gpsu: 0x02000000
			{ 27'h0400000 }  // flashcfg: 0x01000000
		}),
		.SLAVE_MASK({
			// Address width    = 27
			// Address LSBs     = 2
			// Slave name width = 8
			{ 27'h4000000 }, //    sdram
			{ 27'h7c00000 }, //    flash
			{ 27'h7c00000 }, //    bkram
			{ 27'h7c00000 }, //     netb
			{ 27'h7c00000 }, //   wb_dio
			{ 27'h7c00000 }, //     mdio
			{ 27'h7c00000 }, //      cfg
			{ 27'h7c00000 }, //     uart
			{ 27'h7c00000 }, //     gpsu
			{ 27'h7c00000 }  // flashcfg
		}),
		.OPT_DBLBUFFER(1'b1))
	wb_xbar(
		.i_clk(i_clk), .i_reset(i_reset),
		.i_mcyc({
			wb_wbu_arbiter_cyc,
			wb_zip_cyc
		}),
		.i_mstb({
			wb_wbu_arbiter_stb,
			wb_zip_stb
		}),
		.i_mwe({
			wb_wbu_arbiter_we,
			wb_zip_we
		}),
		.i_maddr({
			wb_wbu_arbiter_addr,
			wb_zip_addr
		}),
		.i_mdata({
			wb_wbu_arbiter_data,
			wb_zip_data
		}),
		.i_msel({
			wb_wbu_arbiter_sel,
			wb_zip_sel
		}),
		.o_mstall({
			wb_wbu_arbiter_stall,
			wb_zip_stall
		}),
		.o_mack({
			wb_wbu_arbiter_ack,
			wb_zip_ack
		}),
		.o_mdata({
			wb_wbu_arbiter_idata,
			wb_zip_idata
		}),
		.o_merr({
			wb_wbu_arbiter_err,
			wb_zip_err
		}),
		// Slave connections
		.o_scyc({
			wb_sdram_cyc,
			wb_flash_cyc,
			wb_bkram_cyc,
			wb_netb_cyc,
			wb_dio_cyc,
			wb_mdio_cyc,
			wb_cfg_cyc,
			wb_uart_cyc,
			wb_gpsu_cyc,
			wb_flashcfg_cyc
		}),
		.o_sstb({
			wb_sdram_stb,
			wb_flash_stb,
			wb_bkram_stb,
			wb_netb_stb,
			wb_dio_stb,
			wb_mdio_stb,
			wb_cfg_stb,
			wb_uart_stb,
			wb_gpsu_stb,
			wb_flashcfg_stb
		}),
		.o_swe({
			wb_sdram_we,
			wb_flash_we,
			wb_bkram_we,
			wb_netb_we,
			wb_dio_we,
			wb_mdio_we,
			wb_cfg_we,
			wb_uart_we,
			wb_gpsu_we,
			wb_flashcfg_we
		}),
		.o_saddr({
			wb_sdram_addr,
			wb_flash_addr,
			wb_bkram_addr,
			wb_netb_addr,
			wb_dio_addr,
			wb_mdio_addr,
			wb_cfg_addr,
			wb_uart_addr,
			wb_gpsu_addr,
			wb_flashcfg_addr
		}),
		.o_sdata({
			wb_sdram_data,
			wb_flash_data,
			wb_bkram_data,
			wb_netb_data,
			wb_dio_data,
			wb_mdio_data,
			wb_cfg_data,
			wb_uart_data,
			wb_gpsu_data,
			wb_flashcfg_data
		}),
		.o_ssel({
			wb_sdram_sel,
			wb_flash_sel,
			wb_bkram_sel,
			wb_netb_sel,
			wb_dio_sel,
			wb_mdio_sel,
			wb_cfg_sel,
			wb_uart_sel,
			wb_gpsu_sel,
			wb_flashcfg_sel
		}),
		.i_sstall({
			wb_sdram_stall,
			wb_flash_stall,
			wb_bkram_stall,
			wb_netb_stall,
			wb_dio_stall,
			wb_mdio_stall,
			wb_cfg_stall,
			wb_uart_stall,
			wb_gpsu_stall,
			wb_flashcfg_stall
		}),
		.i_sack({
			wb_sdram_ack,
			wb_flash_ack,
			wb_bkram_ack,
			wb_netb_ack,
			wb_dio_ack,
			wb_mdio_ack,
			wb_cfg_ack,
			wb_uart_ack,
			wb_gpsu_ack,
			wb_flashcfg_ack
		}),
		.i_sdata({
			wb_sdram_idata,
			wb_flash_idata,
			wb_bkram_idata,
			wb_netb_idata,
			wb_dio_idata,
			wb_mdio_idata,
			wb_cfg_idata,
			wb_uart_idata,
			wb_gpsu_idata,
			wb_flashcfg_idata
		}),
		.i_serr({
			wb_sdram_err,
			wb_flash_err,
			wb_bkram_err,
			wb_netb_err,
			wb_dio_err,
			wb_mdio_err,
			wb_cfg_err,
			wb_uart_err,
			wb_gpsu_err,
			wb_flashcfg_err
		})
		);

	//
	// BUS-LOGIC for wbu
	//
	//
	// No class SINGLE peripherals on the "wbu" bus
	//

	//
	// No class DOUBLE peripherals on the "wbu" bus
	//

	// info: @ERROR.WIRE for wbu_arbiter matches the buses error name, wbu_wbu_arbiter_err
	assign	wbu_zip_err= 1'b0;
	//
	// Connect the wbu bus components together using the wbxbar()
	//
	//
	wbxbar #(
		.NM(1), .NS(2), .AW(28), .DW(32),
		.SLAVE_ADDR({
			// Address width    = 28
			// Address LSBs     = 2
			// Slave name width = 11
			{ 28'h8000000 }, //         zip: 0x20000000
			{ 28'h0000000 }  // wbu_arbiter: 0x00000000
		}),
		.SLAVE_MASK({
			// Address width    = 28
			// Address LSBs     = 2
			// Slave name width = 11
			{ 28'h8000000 }, //         zip
			{ 28'h8000000 }  // wbu_arbiter
		}),
		.OPT_DBLBUFFER(1'b1))
	wbu_xbar(
		.i_clk(i_clk), .i_reset(i_reset),
		.i_mcyc({
			wbu_wbu_cyc
		}),
		.i_mstb({
			wbu_wbu_stb
		}),
		.i_mwe({
			wbu_wbu_we
		}),
		.i_maddr({
			wbu_wbu_addr
		}),
		.i_mdata({
			wbu_wbu_data
		}),
		.i_msel({
			wbu_wbu_sel
		}),
		.o_mstall({
			wbu_wbu_stall
		}),
		.o_mack({
			wbu_wbu_ack
		}),
		.o_mdata({
			wbu_wbu_idata
		}),
		.o_merr({
			wbu_wbu_err
		}),
		// Slave connections
		.o_scyc({
			wbu_zip_cyc,
			wbu_wbu_arbiter_cyc
		}),
		.o_sstb({
			wbu_zip_stb,
			wbu_wbu_arbiter_stb
		}),
		.o_swe({
			wbu_zip_we,
			wbu_wbu_arbiter_we
		}),
		.o_saddr({
			wbu_zip_addr,
			wbu_wbu_arbiter_addr
		}),
		.o_sdata({
			wbu_zip_data,
			wbu_wbu_arbiter_data
		}),
		.o_ssel({
			wbu_zip_sel,
			wbu_wbu_arbiter_sel
		}),
		.i_sstall({
			wbu_zip_stall,
			wbu_wbu_arbiter_stall
		}),
		.i_sack({
			wbu_zip_ack,
			wbu_wbu_arbiter_ack
		}),
		.i_sdata({
			wbu_zip_idata,
			wbu_wbu_arbiter_idata
		}),
		.i_serr({
			wbu_zip_err,
			wbu_wbu_arbiter_err
		})
		);

	//
	// Declare the interrupt busses
	//
	// Interrupt busses are defined by anything with a @PIC tag.
	// The @PIC.BUS tag defines the name of the wire bus below,
	// while the @PIC.MAX tag determines the size of the bus width.
	//
	// For your peripheral to be assigned to this bus, it must have an
	// @INT.NAME.WIRE= tag to define the wire name of the interrupt line,
	// and an @INT.NAME.PIC= tag matching the @PIC.BUS tag of the bus
	// your interrupt will be assigned to.  If an @INT.NAME.ID tag also
	// exists, then your interrupt will be assigned to the position given
	// by the ID# in that tag.
	//
	assign	bus_int_vector = {
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		spio_int
	};
	assign	alt_int_vector = {
		1'b0,
		rtc_int,
		uartrx_int,
		uarttx_int,
		gpsutxf_int,
		gpsutx_int,
		gpsurx_int,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0
	};
	assign	sys_int_vector = {
		1'b0,
		uartrxf_int,
		uarttxf_int,
		gpsurxf_int,
		oledrgb_int,
		netrx_int,
		nettx_int,
		ck_pps,
		w_bus_int,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0,
		1'b0
	};


	//
	//
	// Now we turn to defining all of the parts and pieces of what
	// each of the various peripherals does, and what logic it needs.
	//
	// This information comes from the @MAIN.INSERT and @MAIN.ALT tags.
	// If an @ACCESS tag is available, an ifdef is created to handle
	// having the access and not.  If the @ACCESS tag is `defined above
	// then the @MAIN.INSERT code is executed.  If not, the @MAIN.ALT
	// code is exeucted, together with any other cleanup settings that
	// might need to take place--such as returning zeros to the bus,
	// or making sure all of the various interrupt wires are set to
	// zero if the component is not included.
	//
`ifdef	GPSTRK_ACCESS
	// Verilator lint_off UNUSED
	wire	[1:0]	ck_dbg;
	// Verilator lint_on  UNUSED

	gpsclock #(.DEFAULT_STEP(GPSCLOCK_DEFAULT_STEP))
		ppsck(i_clk, 1'b0, gps_pps, ck_pps, gps_led,
			wb_gck_cyc, wb_gck_stb, wb_gck_we,
			wb_gck_addr[2-1:0],
			wb_gck_data, // 32 bits wide
			wb_gck_sel,  // 32/8 bits wide
		wb_gck_stall, wb_gck_ack, wb_gck_idata,
			gps_tracking, gps_now, gps_step, gps_err, gps_locked,
			ck_dbg);

	// Verilator lint_off UNUSED
	assign	gps_dbg = { 29'b0, gps_now[63], gps_pps, i_gpsu_rx };
	// Verilator lint_on  UNUSED
`else	// GPSTRK_ACCESS
	wire	[31:0]	pre_step;
	assign	pre_step = { 16'h00, (({GPSCLOCK_DEFAULT_STEP[27:0],20'h00})
				>>GPSCLOCK_DEFAULT_STEP[31:28]) };
	always @(posedge i_clk)
		{ ck_pps, gps_step[31:0] } <= gps_step + pre_step;
	assign	gck_stall  = 1'b0;
	assign	gps_now    = 64'h0;
	assign	gps_err    = 64'h0;
	assign	gps_step   = 64'h0;
	assign	gps_led    = 1'b0;
	assign	gps_locked = 1'b0;

	assign	ck_pps = 1'b0;	// gck.INT.PPS.WIRE
`endif	// GPSTRK_ACCESS

`ifdef	GPSTRK_ACCESS
	gpsclock_tb #(.CLOCK_FREQUENCY_HZ(81247960))
		ppstb(i_clk, ck_pps, tb_pps,
			wb_gtb_cyc, wb_gtb_stb, wb_gtb_we,
			wb_gtb_addr[3-1:0],
			wb_gtb_data, // 32 bits wide
			wb_gtb_sel,  // 32/8 bits wide
		wb_gtb_stall, wb_gtb_ack, wb_gtb_idata,
			gps_err, gps_now, gps_step);

`ifdef	GPSTB
	assign	gps_pps = tb_pps;
`else
	assign	gps_pps = i_gps_pps;
`endif

`endif

`ifndef	ETHERNET_ACCESS
	// Ethernet packet memory declaration
	//
	// The only time this needs to be defined is when the ethernet module
	// itself isnt defined.  Otherwise, the access is accomplished by the
	// ethernet module

	memdev #(12)
		enet_buffers(i_clk,
			wb_netb_cyc, wb_netb_stb, wb_netb_we,
			wb_netb_addr[11-1:0],
			wb_netb_data, // 32 bits wide
			wb_netb_sel,  // 32/8 bits wide
		wb_netb_stall, wb_netb_ack, wb_netb_idata);

`else

// These don't need to be defined here, and indeed should not be defined here
// lest their definitions override those of the netb interface defined in the
// enetpackets module
//
//	assign	wb_netb_ack   = 1'b0;
//	assign	wb_netb_stall = 1'b0;
//	assign	wb_netb_data  = wb_netp_data;

`endif

`ifdef	ETHERNET_ACCESS
	enetpackets	#(.MEMORY_ADDRESS_WIDTH(12)
`ifdef	ENETRX_SCOPE
		, .RXSCOPE(1)
`else	// ENETRX_SCOPE
		, .RXSCOPE(0)
`endif
		)
		netctrl(i_clk, i_reset,
			wb_netb_cyc, wb_netb_stb, wb_netb_we,
			wb_netb_addr[11-1:0],
			wb_netb_data, // 32 bits wide
			wb_netb_sel,  // 32/8 bits wide
		wb_netb_stall, wb_netb_ack, wb_netb_idata,
			wb_netp_cyc, wb_netp_stb, wb_netp_we,
			wb_netp_addr[3-1:0],
			wb_netp_data, // 32 bits wide
			wb_netp_sel,  // 32/8 bits wide
		wb_netp_stall, wb_netp_ack, wb_netp_idata,
			o_eth_rstn,
			i_eth_rx_clk, i_eth_col, i_eth_crs, i_eth_rx_dv, i_eth_rxd,
				i_eth_rxerr,
			i_eth_tx_clk, o_eth_tx_en, o_eth_txd,
			netrx_int, nettx_int, netp_debug);
`else	// ETHERNET_ACCESS
	assign	nettx_int = 1'b0;	// netp.INT.NETTX.WIRE
	assign	netrx_int = 1'b0;	// netp.INT.NETRX.WIRE
`endif	// ETHERNET_ACCESS

	assign	wb_version_idata = `DATESTAMP;
	assign	wb_version_ack = wb_version_stb;
	assign	wb_version_stall = 1'b0;
`ifdef	OLEDRGB_ACCESS
	wboledrgb #(.CBITS(4)) oledrgbi(i_clk,
		wb_oledrgb_cyc, wb_oledrgb_stb, wb_oledrgb_we,
			wb_oledrgb_addr[2-1:0],
			wb_oledrgb_data, // 32 bits wide
			wb_oledrgb_sel,  // 32/8 bits wide
		wb_oledrgb_stall, wb_oledrgb_ack, wb_oledrgb_idata,
		o_oledrgb_sck, o_oledrgb_cs_n, o_oledrgb_mosi, o_oledrgb_dcn,
		{ o_oledrgb_reset_n, o_oledrgb_vccen, o_oledrgb_pmoden },
		oledrgb_int);
`else	// OLEDRGB_ACCESS
	assign	o_oledrgb_cs_n    = 1'b1;
	assign	o_oledrgb_sck     = 1'b1;
	assign	o_oledrgb_mosi    = 1'b1;
	assign	o_oledrgb_dcn     = 1'b1;
	assign	o_oledrgb_reset_n = 1'b0;
	assign	o_oledrgb_vccen   = 1'b0;
	assign	o_oledrgb_pmoden  = 1'b0;

	assign	oledrgb_int = 1'b0;	// oledrgb.INT.OLED.WIRE
`endif	// OLEDRGB_ACCESS

`ifdef	SDRAM_ACCESS
	assign	o_sdram_cyc  = wb_sdram_cyc;
	assign	o_sdram_stb  =(wb_sdram_stb);
	assign	o_sdram_we   = wb_sdram_we;
	assign	o_sdram_addr = wb_sdram_addr[27-1:0];
	assign	o_sdram_data = wb_sdram_data;
	assign	o_sdram_sel  = wb_sdram_sel;
	assign	wb_sdram_ack   = i_sdram_ack;
	assign	wb_sdram_stall = i_sdram_stall;
	assign	wb_sdram_idata = i_sdram_data;
	assign	sdram_err         = i_sdram_err;
	assign	wb_sdram_err   = sdram_err;

`else	// SDRAM_ACCESS

	//
	// In the case that there is no wb_sdram peripheral
	// responding on the wb bus
	assign	wb_sdram_ack   = 1'b0;
	assign	wb_sdram_err   = (wb_sdram_stb);
	assign	wb_sdram_stall = 0;
	assign	wb_sdram_idata = 0;

`endif	// SDRAM_ACCESS

`ifdef	INCLUDE_ZIPCPU
	//
	//
	// The ZipCPU/ZipSystem BUS master
	//
	//
	assign	zip_int_vector = { alt_int_vector[14:8], sys_int_vector[14:6] };
	zipsystem #(.RESET_ADDRESS(RESET_ADDRESS),
			.ADDRESS_WIDTH(ZIP_ADDRESS_WIDTH),
			.LGICACHE(10),.LGDCACHE(10),
			.START_HALTED(ZIP_START_HALTED),
`ifdef	VERILATOR
			.RESET_DURATION(20),
`else
			.RESET_DURATION(20_000),
`endif
			.EXTERNAL_INTERRUPTS(ZIP_INTS))
		swic(i_clk, (i_reset)||(i_cpu_reset),
			// Zippys wishbone interface
			wb_zip_cyc, wb_zip_stb, wb_zip_we,
			wb_zip_addr[27-1:0],
			wb_zip_data, // 32 bits wide
			wb_zip_sel,  // 32/8 bits wide
		wb_zip_stall, wb_zip_ack, wb_zip_idata,wb_zip_err,
			zip_int_vector, zip_cpu_int,
			// Debug wishbone interface
			wbu_zip_cyc, wbu_zip_stb, wbu_zip_we,
			wbu_zip_addr[1-1:0],
			wbu_zip_data, // 32 bits wide
			wbu_zip_sel,  // 32/8 bits wide
		wbu_zip_stall, wbu_zip_ack, wbu_zip_idata,
			zip_debug);
	assign	zip_trigger = zip_debug[31];
`else	// INCLUDE_ZIPCPU

	//
	// In the case that there is no wbu_zip peripheral
	// responding on the wbu bus
	assign	wbu_zip_ack   = 1'b0;
	assign	wbu_zip_err   = (wbu_zip_stb);
	assign	wbu_zip_stall = 0;
	assign	wbu_zip_idata = 0;

	assign	zip_cpu_int = 1'b0;	// zip.INT.ZIP.WIRE
`endif	// INCLUDE_ZIPCPU

`ifdef	CFG_ACCESS
`ifdef	VERILATOR
	reg	r_cfg_ack;

	initial	r_cfg_ack = 1'b0;
	always @(posedge i_clk)
		r_cfg_ack <= wb_cfg_stb;
	assign	wb_cfg_ack   = r_cfg_ack;
	assign	wb_cfg_stall = 1'b0;
	assign	wb_cfg_idata = 32'h00;
`else
	wbicapetwo #(ICAPE_LGDIV)
		cfgport(i_clk, wb_cfg_cyc, wb_cfg_stb, wb_cfg_we,
			wb_cfg_addr[5-1:0],
			wb_cfg_data, // 32 bits wide
			wb_cfg_sel,  // 32/8 bits wide
		wb_cfg_stall, wb_cfg_ack, wb_cfg_idata);
`endif
`else	// CFG_ACCESS

	//
	// In the case that there is no wb_cfg peripheral
	// responding on the wb bus
	assign	wb_cfg_ack   = 1'b0;
	assign	wb_cfg_err   = (wb_cfg_stb);
	assign	wb_cfg_stall = 0;
	assign	wb_cfg_idata = 0;

`endif	// CFG_ACCESS

	assign	wb_wbu_arbiter_cyc  = wbu_wbu_arbiter_cyc;
	assign	wb_wbu_arbiter_stb  = wbu_wbu_arbiter_stb;
	assign	wb_wbu_arbiter_we   = wbu_wbu_arbiter_we;
	assign	wb_wbu_arbiter_addr = wbu_wbu_arbiter_addr[27-1:0];
	assign	wb_wbu_arbiter_data = wbu_wbu_arbiter_data;
	assign	wb_wbu_arbiter_sel  = wbu_wbu_arbiter_sel;
	//
	assign	wbu_wbu_arbiter_stall = wb_wbu_arbiter_stall;
	assign	wbu_wbu_arbiter_ack   = wb_wbu_arbiter_ack;
	assign	wbu_wbu_arbiter_idata = wb_wbu_arbiter_idata;
	assign	wbu_wbu_arbiter_err   = wb_wbu_arbiter_err;
`ifdef	GPSUART_ACCESS
	wbuart #(.INITIAL_SETUP(31'h0000210f))
 		gpsu_uart(i_clk, 1'b0,
			wb_gpsu_cyc, wb_gpsu_stb, wb_gpsu_we,
			wb_gpsu_addr[2-1:0],
			wb_gpsu_data, // 32 bits wide
			wb_gpsu_sel,  // 32/8 bits wide
		wb_gpsu_stall, wb_gpsu_ack, wb_gpsu_idata,
 			i_gpsu_rx, o_gpsu_tx, w_gpsu_cts_n, w_gpsu_rts_n,
			gpsurx_int, gpsutx_int,
			gpsurxf_int, gpsutxf_int);
`else	// GPSUART_ACCESS
	assign	o_gpsu_tx    = 1'b1;
	assign	w_gpsu_rts_n = 1'b0;

	//
	// In the case that there is no wb_gpsu peripheral
	// responding on the wb bus
	assign	wb_gpsu_ack   = 1'b0;
	assign	wb_gpsu_err   = (wb_gpsu_stb);
	assign	wb_gpsu_stall = 0;
	assign	wb_gpsu_idata = 0;

	assign	gpsutx_int = 1'b0;	// gpsu.INT.GPSTX.WIRE
	assign	gpsutxf_int = 1'b0;	// gpsu.INT.GPSTXF.WIRE
	assign	gpsurx_int = 1'b0;	// gpsu.INT.GPSRX.WIRE
	assign	gpsurxf_int = 1'b0;	// gpsu.INT.GPSRXF.WIRE
`endif	// GPSUART_ACCESS

`ifdef	BUSPIC_ACCESS
	//
	// The BUS Interrupt controller
	//
	icontrol #(15)	buspici(i_clk, 1'b0,
			wb_buspic_cyc, wb_buspic_stb, wb_buspic_we,
			wb_buspic_data, // 32 bits wide
			wb_buspic_sel,  // 32/8 bits wide
		wb_buspic_stall, wb_buspic_ack, wb_buspic_idata,
			bus_int_vector, w_bus_int);
`else	// BUSPIC_ACCESS
	assign	w_bus_int = 1'b0;	// buspic.INT.BUS.WIRE
`endif	// BUSPIC_ACCESS

	assign	wb_buildtime_idata = `BUILDTIME;
	assign	wb_buildtime_ack = wb_buildtime_stb;
	assign	wb_buildtime_stall = 1'b0;
`ifdef	FLASH_ACCESS
	qflexpress #(.LGFLASHSZ(24), .OPT_CLKDIV(0),
		.NDUMMY(6), .RDDELAY(3),
		.OPT_STARTUP_FILE("spansion.hex"),
`ifdef	FLASHCFG_ACCESS
		.OPT_CFG(1'b1)
`else
		.OPT_CFG(1'b0)
`endif
		)
		flashi(i_clk, i_reset,
			// Primary memory reading inputs
			wb_flash_cyc, wb_flash_stb, wb_flash_we,
			wb_flash_addr[22-1:0],
			wb_flash_data, // 32 bits wide
			wb_flash_sel,  // 32/8 bits wide
		wb_flash_stall, wb_flash_ack, wb_flash_idata,
			// Configuration bus ports
			wb_flashcfg_cyc, wb_flashcfg_stb, wb_flashcfg_we,
			wb_flashcfg_data, // 32 bits wide
			wb_flashcfg_sel,  // 32/8 bits wide
		wb_flashcfg_stall, wb_flashcfg_ack, wb_flashcfg_idata,
			o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
			flash_dbg_trigger, flash_debug);
`else	// FLASH_ACCESS
	assign	o_qspi_sck  = 1'b1;
	assign	o_qspi_cs_n = 1'b1;
	assign	o_qspi_mod  = 2'b01;
	assign	o_qspi_dat  = 4'b1111;

	//
	// In the case that there is no wb_flash peripheral
	// responding on the wb bus
	assign	wb_flash_ack   = 1'b0;
	assign	wb_flash_err   = (wb_flash_stb);
	assign	wb_flash_stall = 0;
	assign	wb_flash_idata = 0;

`endif	// FLASH_ACCESS

`ifdef	GPSTRK_ACCESS
	assign	wb_subseconds_idata = gps_now[31:0];
`else
	always @(posedge i_clk)
	if (wb_subseconds_stb && wb_subseconds_we)
		r_subseconds_data <= wb_subseconds_data;
	else
		r_subseconds_data <= r_subseconds_data
			+ { 16'h0, RTC_CLKSTEP[31:16] };

	assign	wb_subseconds_idata = r_subseconds_data;
`endif
	always @(posedge i_clk)
	if (wb_zip_err)
	begin
		r_buserr_addr <= 0;
		r_buserr_addr[27-1:0] <= wb_zip_addr[27-1:0];
	end else if (wbu_wbu_err)
	begin
		r_buserr_addr <= 0;
		r_buserr_addr[28-1:0] <= wbu_wbu_addr[28-1:0];
	end
	assign	wb_buserr_stall= 1'b0;
	assign	wb_buserr_ack  = wb_buserr_stb;
	assign	wb_buserr_idata = { {(30-28){1'b0}},
			r_buserr_addr, 2'b00 };
`ifdef	WBUBUS_MASTER
	// The Host USB interface, to be used by the WB-UART bus
	rxuartlite	#(.TIMER_BITS(DBGBUSBITS),
				.CLOCKS_PER_BAUD(BUSUART[DBGBUSBITS-1:0]))
		rcv(i_clk, i_wbu_uart_rx,
				wbu_rx_stb, wbu_rx_data);
	txuartlite	#(.TIMING_BITS(DBGBUSBITS[4:0]),
				.CLOCKS_PER_BAUD(BUSUART[DBGBUSBITS-1:0]))
		txv(i_clk,
				wbu_tx_stb,
				wbu_tx_data,
				o_wbu_uart_tx,
				wbu_tx_busy);

`ifdef	INCLUDE_ZIPCPU
`else
	assign	zip_dbg_ack   = 1'b0;
	assign	zip_dbg_stall = 1'b0;
	assign	zip_dbg_data  = 0;
`endif
`ifndef	BUSPIC_ACCESS
	wire	w_bus_int;
	assign	w_bus_int = 1'b0;
`endif
	// Verilator lint_off UNUSED
	wire	[31:0]	wbu_wbu_tmp_addr;
	// Verilator lint_on  UNUSED
	wbuconsole #(.LGWATCHDOG(DBGBUSWATCHDOG))
	genbus(i_clk, wbu_rx_stb, wbu_rx_data,
			wbu_wbu_cyc, wbu_wbu_stb, wbu_wbu_we, wbu_wbu_tmp_addr, wbu_wbu_data,
			wbu_wbu_stall, wbu_wbu_ack,
			wbu_wbu_err, wbu_wbu_idata,
			w_bus_int,
			wbu_tx_stb, wbu_tx_data, wbu_tx_busy,
			//
			w_console_tx_stb, w_console_tx_data, w_console_busy,
			w_console_rx_stb, w_console_rx_data,
			//
			wbubus_dbg[0]);
	assign	wbu_wbu_sel = 4'hf;
	assign	wbu_wbu_addr = wbu_wbu_tmp_addr[(28-1):0];
`else	// WBUBUS_MASTER
`endif	// WBUBUS_MASTER

`ifdef	FLASHCFG_ACCESS
	// The Flash control interface is defined by the flash instantiation
	// hence we don't need to do anything to define it here.
`else	// FLASHCFG_ACCESS

	//
	// In the case that there is no wb_flashcfg peripheral
	// responding on the wb bus
	assign	wb_flashcfg_ack   = 1'b0;
	assign	wb_flashcfg_err   = (wb_flashcfg_stb);
	assign	wb_flashcfg_stall = 0;
	assign	wb_flashcfg_idata = 0;

`endif	// FLASHCFG_ACCESS

`ifdef	BUSCONSOLE_ACCESS
	wbconsole #(.LGFLEN(6)) console(i_clk, 1'b0,
			wb_uart_cyc, wb_uart_stb, wb_uart_we,
			wb_uart_addr[2-1:0],
			wb_uart_data, // 32 bits wide
			wb_uart_sel,  // 32/8 bits wide
		wb_uart_stall, wb_uart_ack, wb_uart_idata,
			w_console_tx_stb, w_console_tx_data, w_console_busy,
			w_console_rx_stb, w_console_rx_data,
			uartrx_int, uarttx_int, uartrxf_int, uarttxf_int);
`else	// BUSCONSOLE_ACCESS

	//
	// In the case that there is no wb_uart peripheral
	// responding on the wb bus
	assign	wb_uart_ack   = 1'b0;
	assign	wb_uart_err   = (wb_uart_stb);
	assign	wb_uart_stall = 0;
	assign	wb_uart_idata = 0;

	assign	uarttxf_int = 1'b0;	// uart.INT.UARTTXF.WIRE
	assign	uartrxf_int = 1'b0;	// uart.INT.UARTRXF.WIRE
	assign	uarttx_int = 1'b0;	// uart.INT.UARTTX.WIRE
	assign	uartrx_int = 1'b0;	// uart.INT.UARTRX.WIRE
`endif	// BUSCONSOLE_ACCESS

`ifdef	CLRLED_ACCESS
`ifdef	PWRCOUNT_ACCESS
	assign	clrled_counter = r_pwrcount_data[8:0];
`else
	always @(posedge i_clk)
		clrled_counter <= clrled_counter + 1;
`endif
	clrled clrled0(i_clk,
		(wb_clrled_stb)&&(wb_clrled_addr[1:0]==2'b00)&&(wb_clrled_we),
		wb_clrled_data, clrled_counter, clrled0_data,
			{ o_clr_ledr[0], o_clr_ledg[0], o_clr_ledb[0] });
	clrled clrled1(i_clk,
		(wb_clrled_stb)&&(wb_clrled_addr[1:0]==2'b01)&&(wb_clrled_we),
		wb_clrled_data, clrled_counter, clrled1_data,
			{ o_clr_ledr[1], o_clr_ledg[1], o_clr_ledb[1] });
	clrled clrled2(i_clk,
		(wb_clrled_stb)&&(wb_clrled_addr[1:0]==2'b10)&&(wb_clrled_we),
		wb_clrled_data, clrled_counter, clrled2_data,
			{ o_clr_ledr[2], o_clr_ledg[2], o_clr_ledb[2] });
	clrled clrled3(i_clk,
		(wb_clrled_stb)&&(wb_clrled_addr[1:0]==2'b11)&&(wb_clrled_we),
		wb_clrled_data, clrled_counter, clrled3_data,
			{ o_clr_ledr[3], o_clr_ledg[3], o_clr_ledb[3] });

	initial	r_clrled_ack = 1'b0;
	always @(posedge i_clk)
		r_clrled_ack <= wb_clrled_stb;

	always @(posedge i_clk)
	case(wb_clrled_addr[1:0])
	2'b00: r_clrled_data <= clrled0_data;
	2'b01: r_clrled_data <= clrled1_data;
	2'b10: r_clrled_data <= clrled2_data;
	2'b11: r_clrled_data <= clrled3_data;
	endcase

	assign	wb_clrled_ack   = r_clrled_ack;
	assign	wb_clrled_stall = 1'b0;
	assign	wb_clrled_idata = r_clrled_data;

`else	// CLRLED_ACCESS
	assign	o_clr_ledr = 0;
	assign	o_clr_ledg = 0;
	assign	o_clr_ledb = 0;
`endif	// CLRLED_ACCESS

`ifdef	SPIO_ACCESS
	spio #(.NBTN(4), .NLEDS(4), .NSW(4)) spioi(i_clk,
		wb_spio_cyc, wb_spio_stb, wb_spio_we,
			wb_spio_data, // 32 bits wide
			wb_spio_sel,  // 32/8 bits wide
		wb_spio_stall, wb_spio_ack, wb_spio_idata,
		i_sw, i_btn, o_led, spio_int);
`else	// SPIO_ACCESS
	assign	o_led = 0;
	assign	spio_int = 1'b0;	// spio.INT.SPIO.WIRE
`endif	// SPIO_ACCESS

`ifdef	RTC_ACCESS
`ifdef	GPSTRK_ACCESS
	rtcgps	#(RTC_CLKSTEP) thertc(i_clk, i_reset,
		wb_rtc_cyc, wb_rtc_stb, wb_rtc_we,
			wb_rtc_addr[3-1:0],
			wb_rtc_data, // 32 bits wide
			wb_rtc_sel,  // 32/8 bits wide
		wb_rtc_stall, wb_rtc_ack, wb_rtc_idata,
		rtc_int, rtc_ppd,
		gps_tracking, ck_pps, gps_step[47:16], rtc_pps);
`else
	rtclight #(32'h34dcca) thertc(i_clk, i_reset,
		wb_rtc_cyc, wb_rtc_stb, wb_rtc_we,
			wb_rtc_addr[3-1:0],
			wb_rtc_data, // 32 bits wide
			wb_rtc_sel,  // 32/8 bits wide
		wb_rtc_stall, wb_rtc_ack, wb_rtc_idata,
		rtc_int, rtc_pps, rtc_ppd);
`endif
`else	// RTC_ACCESS
	assign	rtc_pps = 1'b0;
	assign	rtc_ppd = 1'b0;
	assign	rtc_int = 1'b0;	// rtc.INT.RTC.WIRE
`endif	// RTC_ACCESS

`ifdef	BKRAM_ACCESS
	memdev #(.LGMEMSZ(16), .EXTRACLOCK(1))
		bkrami(i_clk, i_reset,
			wb_bkram_cyc, wb_bkram_stb, wb_bkram_we,
			wb_bkram_addr[14-1:0],
			wb_bkram_data, // 32 bits wide
			wb_bkram_sel,  // 32/8 bits wide
		wb_bkram_stall, wb_bkram_ack, wb_bkram_idata);
`else	// BKRAM_ACCESS

	//
	// In the case that there is no wb_bkram peripheral
	// responding on the wb bus
	assign	wb_bkram_ack   = 1'b0;
	assign	wb_bkram_err   = (wb_bkram_stb);
	assign	wb_bkram_stall = 0;
	assign	wb_bkram_idata = 0;

`endif	// BKRAM_ACCESS

`ifdef	PWRCOUNT_ACCESS
	initial	r_pwrcount_data = 32'h0;
	always @(posedge i_clk)
	if (r_pwrcount_data[31])
		r_pwrcount_data[30:0] <= r_pwrcount_data[30:0] + 1'b1;
	else
		r_pwrcount_data[31:0] <= r_pwrcount_data[31:0] + 1'b1;

	assign	wb_pwrcount_stall = 1'b0;
	assign	wb_pwrcount_ack   = wb_pwrcount_stb;
	assign	wb_pwrcount_idata = r_pwrcount_data;
`else	// PWRCOUNT_ACCESS
`endif	// PWRCOUNT_ACCESS

`ifdef	RTCDATE_ACCESS
	//
	// The Calendar DATE
	//
	rtcdate	rtcdatei(i_clk, rtc_ppd,
		wb_rtcdate_cyc, wb_rtcdate_stb, wb_rtcdate_we,
			wb_rtcdate_data, // 32 bits wide
			wb_rtcdate_sel,  // 32/8 bits wide
		wb_rtcdate_stall, wb_rtcdate_ack, wb_rtcdate_idata);
`else	// RTCDATE_ACCESS
`endif	// RTCDATE_ACCESS

`ifdef	NETCTRL_ACCESS
	// Verilator lint_off UNUSED
	wire[31:0]	mdio_debug;
	// Verilator lint_on  UNUSED
	enetctrl #(2)
		mdio(i_clk, i_reset, wb_mdio_cyc, wb_mdio_stb, wb_mdio_we,
			wb_mdio_addr[5-1:0],
			wb_mdio_data, // 32 bits wide
			wb_mdio_sel,  // 32/8 bits wide
		wb_mdio_stall, wb_mdio_ack, wb_mdio_idata,
			o_mdclk, o_mdio, i_mdio, o_mdwe, mdio_debug);
`else	// NETCTRL_ACCESS
	assign	o_mdclk = 1'b1;
	assign	o_mdio  = 1'b1;
	assign	o_mdwe  = 1'b0;

	//
	// In the case that there is no wb_mdio peripheral
	// responding on the wb bus
	assign	wb_mdio_ack   = 1'b0;
	assign	wb_mdio_err   = (wb_mdio_stb);
	assign	wb_mdio_stall = 0;
	assign	wb_mdio_idata = 0;

`endif	// NETCTRL_ACCESS



endmodule // main.v