wboledbw.txt

################################################################################
##
## Filename:	auto-data/wboledbw.txt
##
## Project:	AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose:	To describe how to interact with an OLED device driver, in order
##		to drive an OLED display.
##
## Creator:	Dan Gisselquist, Ph.D.
##		Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
## target there if the PDF file isn't present.)  If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License:	GPL, v3, as defined and found on www.gnu.org,
## {{{
##		http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=oled
@NADDR=4
@DEVID=OLEDBW
@ACCESS=@$(DEVID)_ACCESS
@SLAVE.TYPE=DOUBLE
@SLAVE.BUS=wb32
@MASTER.TYPE=CPU
@MASTER.BUS=wbwide
@MASTER.PREFIX=@$(MASTER.BUS.NAME)_@$(PREFIX)m
@MASTER.ANSPREFIX=pf_
@INT.OLED.WIRE=oled_int
@INT.OLED.PIC=syspic
@MAIN.PORTLIST=
		// OLED control interface (roughly SPI)
		o_oled_sck, o_oled_mosi, o_oled_dcn
@MAIN.IODECL=
	// OLEDBW interface
	output	wire		o_oled_sck, o_oled_mosi, o_oled_dcn;
@MAIN.DEFNS=
	// OLEDBW
	// {{{
	// Verilator lint_off UNUSED
	wire	[1:0]	w_oled_csn;
	wire		ign_@$(PREFIX)_valid, ign_@$(PREFIX)_last,
			ign_@$(PREFIX)_id;
	wire	[7:0]	ign_@$(PREFIX)_data;
	wire	[31:0]	@$(PREFIX)_debug;
	// Verilator lint_on  UNUSED
	// }}}
@MAIN.INSERT=
	spicpu #(
		// {{{
		.ADDRESS_WIDTH(@$(MASTER.BUS.AWID)),
		.DATA_WIDTH(@$(MASTER.BUS.WIDTH)),
		.NCE(2),
		.OPT_MANUAL(1'b1), .OPT_LITTLE_ENDIAN(1'b0),
		.OPT_START_HALTED(1'b1), .OPT_SHARED_MISO(1'b1)
		// }}}
	) u_@$(PREFIX) (
		// {{{
		.i_clk(@$(SLAVE.BUS.CLOCK.WIRE)), .i_reset(@$(SLAVE.BUS.CLOCK.RESET)),
		@$(SLAVE.ANSIPORTLIST),
		@$(MASTER.ANSIPORTLIST),
		.o_spi_csn(w_oled_csn), .o_spi_sck(o_oled_sck),
		.o_spi_mosi(o_oled_mosi), .i_spi_miso(1'b0),
		.M_AXIS_TVALID(ign_@$(PREFIX)_valid),
		.M_AXIS_TREADY(1'b1),
		.M_AXIS_TDATA( ign_@$(PREFIX)_data),
		.M_AXIS_TLAST( ign_@$(PREFIX)_last),
		.M_AXIS_TID(   ign_@$(PREFIX)_id),
		//
		.o_interrupt(oled_int),
		.i_sync_signal(rtc_pps),
		.o_debug(@$(PREFIX)_debug)
		// }}}
	);

	assign	o_oled_dcn = w_oled_csn[0];
@MAIN.ALT=
	assign	o_oled_sck     = 1'b1;
	assign	o_oled_mosi    = 1'b1;
	assign	o_oled_dcn     = 1'b1;

@REGS.N=4
@REGS.0= 0 R_OLED		OLED
@REGS.1= 1 R_OLED_OV		OLEDOV
@REGS.2= 2 R_OLED_ADDR		OLEDADDR
@REGS.3= 3 R_OLED_CLK		OLEDCLK
@BDEF.DEFN=
typedef	struct OLEDBW_S {
	unsigned	o_cmd, o_override, o_addr, o_clk;
} OLEDBW;

@BDEF.IONAME=_oled
@BDEF.IOTYPE=OLEDBW
@BDEF.OSDEF= _BOARD_HAS_OLEDBW
@BDEF.OSVAL= static volatile @$(BDEF.IOTYPE) *const @$(BDEF.IONAME) = ((@$(BDEF.IOTYPE) *)@$(REGBASE));
@RTL.MAKE.GROUP=WBSPI
@RTL.MAKE.SUBD=wbspi
@RTL.MAKE.FILES=spicpu.v