dspic: Fix for config SRAM and FLASH (zephyrproject-rtos#23)

Modified the configuration in SOC to get the SRAM and FLASH address and
size from device tree node.

Signed-off-by: Udhayanandhan Jayakumar <[email protected]>

Author: Udhayanandhan-Jayakumar

dts/dspic/p33ak128mc106.dtsi

@@ -37,11 +37,11 @@
 	soc: soc {
 	compatible = "microchip,p33ak128mc106-soc";
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 
-		flash0: flash@800004 {
+		flash0: flash@800000 {
 			compatible = "zephyr,flash";
-			reg = <0x800004 0x1FFFC>;
+			reg = <0x800000 0x20000>;
 			label = "FLASH";
 		};
 

soc/microchip/dspic33/dspic33a/Kconfig.defconfig.p33ak128mc106

@@ -6,17 +6,17 @@ if SOC_P33AK128MC106
 config UART_CONSOLE
 	default n
 
-config FLASH_SIZE
-	default 128
-
-config FLASH_BASE_ADDRESS
-	default 0x00800000
-
 config SRAM_SIZE
-	default 80
+  default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM),0,K)
 
 config SRAM_BASE_ADDRESS
-	default 0x010000
+  default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))
+
+config FLASH_SIZE
+  default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+  default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
 
 config MAIN_STACK_SIZE
 	default 128