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| 1 | +#include <stdbool.h> |
| 2 | +#include <stddef.h> |
| 3 | +#include <stdint.h> |
| 4 | +#include <types.h> |
| 5 | + |
| 6 | +#include <log.h> |
| 7 | + |
| 8 | +#include <common.h> |
| 9 | + |
| 10 | +#include <sys-clk.h> |
| 11 | +#include <reg-ncat.h> |
| 12 | + |
| 13 | +#include <mmu.h> |
| 14 | + |
| 15 | +#include <sys-gpio.h> |
| 16 | +#include <sys-spi.h> |
| 17 | +#include <sys-uart.h> |
| 18 | +#include <sys-dram.h> |
| 19 | +#include <sys-sdcard.h> |
| 20 | + |
| 21 | +sunxi_serial_t uart_dbg = { |
| 22 | + .base = SUNXI_UART3_BASE, |
| 23 | + .id = 3, |
| 24 | + .gpio_tx = {GPIO_PIN(GPIO_PORTB, 6), GPIO_PERIPH_MUX7}, |
| 25 | + .gpio_rx = {GPIO_PIN(GPIO_PORTB, 7), GPIO_PERIPH_MUX7}, |
| 26 | +}; |
| 27 | + |
| 28 | +sunxi_spi_t sunxi_spi0 = { |
| 29 | + .base = SUNXI_SPI0_BASE, |
| 30 | + .id = 0, |
| 31 | + .clk_rate = 75 * 1000 * 1000, |
| 32 | + .gpio_cs = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX4}, |
| 33 | + .gpio_sck = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX4}, |
| 34 | + .gpio_mosi = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX4}, |
| 35 | + .gpio_miso = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX4}, |
| 36 | + .gpio_wp = {GPIO_PIN(GPIO_PORTC, 4), GPIO_PERIPH_MUX4}, |
| 37 | + .gpio_hold = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX4}, |
| 38 | +}; |
| 39 | + |
| 40 | +sdhci_t sdhci0 = { |
| 41 | + .name = "sdhci0", |
| 42 | + .id = 0, |
| 43 | + .reg = (sdhci_reg_t *) 0x04020000, |
| 44 | + .voltage = MMC_VDD_27_36, |
| 45 | + .width = MMC_BUS_WIDTH_4, |
| 46 | + .clock = MMC_CLK_50M, |
| 47 | + .removable = 0, |
| 48 | + .isspi = FALSE, |
| 49 | + .skew_auto_mode = TRUE, |
| 50 | + .sdhci_pll = CCU_MMC_CTRL_PLL_PERIPH1X, |
| 51 | + .gpio_clk = {GPIO_PIN(GPIO_PORTF, 2), GPIO_PERIPH_MUX2}, |
| 52 | + .gpio_cmd = {GPIO_PIN(GPIO_PORTF, 3), GPIO_PERIPH_MUX2}, |
| 53 | + .gpio_d0 = {GPIO_PIN(GPIO_PORTF, 1), GPIO_PERIPH_MUX2}, |
| 54 | + .gpio_d1 = {GPIO_PIN(GPIO_PORTF, 0), GPIO_PERIPH_MUX2}, |
| 55 | + .gpio_d2 = {GPIO_PIN(GPIO_PORTF, 5), GPIO_PERIPH_MUX2}, |
| 56 | + .gpio_d3 = {GPIO_PIN(GPIO_PORTF, 4), GPIO_PERIPH_MUX2}, |
| 57 | +}; |
| 58 | + |
| 59 | +dram_para_t dram_para = { |
| 60 | + .dram_clk = 792, |
| 61 | + .dram_type = 3, |
| 62 | + .dram_zq = 0x7b7bfb, |
| 63 | + .dram_odt_en = 0x00, |
| 64 | + .dram_para1 = 0x000010d2, |
| 65 | + .dram_para2 = 0, |
| 66 | + .dram_mr0 = 0x1c70, |
| 67 | + .dram_mr1 = 0x42, |
| 68 | + .dram_mr2 = 0x18, |
| 69 | + .dram_mr3 = 0, |
| 70 | + .dram_tpr0 = 0x004a2195, |
| 71 | + .dram_tpr1 = 0x02423190, |
| 72 | + .dram_tpr2 = 0x0008b061, |
| 73 | + .dram_tpr3 = 0xb4787896,// unused |
| 74 | + .dram_tpr4 = 0, |
| 75 | + .dram_tpr5 = 0x48484848, |
| 76 | + .dram_tpr6 = 0x00000048, |
| 77 | + .dram_tpr7 = 0x1620121e,// unused |
| 78 | + .dram_tpr8 = 0, |
| 79 | + .dram_tpr9 = 0,// clock? |
| 80 | + .dram_tpr10 = 0, |
| 81 | + .dram_tpr11 = 0x00340000, |
| 82 | + .dram_tpr12 = 0x00000046, |
| 83 | + .dram_tpr13 = 0x34000100, |
| 84 | +}; |
| 85 | + |
| 86 | +void clean_syterkit_data(void) { |
| 87 | + /* Disable MMU, data cache, instruction cache, interrupts */ |
| 88 | + arm32_mmu_disable(); |
| 89 | + printk(LOG_LEVEL_INFO, "disable mmu ok...\n"); |
| 90 | + arm32_dcache_disable(); |
| 91 | + printk(LOG_LEVEL_INFO, "disable dcache ok...\n"); |
| 92 | + arm32_icache_disable(); |
| 93 | + printk(LOG_LEVEL_INFO, "disable icache ok...\n"); |
| 94 | + arm32_interrupt_disable(); |
| 95 | + printk(LOG_LEVEL_INFO, "free interrupt ok...\n"); |
| 96 | +} |
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