From e276f1184ede0ee0710f2ac42aa4700e6e52385a Mon Sep 17 00:00:00 2001 From: haxar Date: Tue, 9 Aug 2022 12:16:28 -0700 Subject: [PATCH] boot: Add 1BL initialization for ROM less southbridges --- boot_rom/2bBootStartBios.c | 233 +++++++++++++++++++++++++++++++------ boot_rom/2bBootStartup.S | 144 ++++++++++++++++------- boot_rom/2bconsts.h | 71 ----------- boot_rom/2bload.h | 131 +++++++++++++++++---- boot_rom/Xcodes.h | 30 ++++- boot_rom/bootrom.ld | 63 +++++----- drivers/pci/pci.c | 1 - include/consts.h | 49 ++++++-- lib/imagebld/imagebld.c | 92 ++++++--------- scripts/ldscript-crom.ld | 42 ++++--- 10 files changed, 579 insertions(+), 277 deletions(-) delete mode 100644 boot_rom/2bconsts.h diff --git a/boot_rom/2bBootStartBios.c b/boot_rom/2bBootStartBios.c index 3443d6b5..987d280d 100644 --- a/boot_rom/2bBootStartBios.c +++ b/boot_rom/2bBootStartBios.c @@ -22,55 +22,213 @@ int BufferINlen; unsigned char *BufferOUT; int BufferOUTPos; -extern int decompress_kernel(char*out, char *data, int len); +extern int decompress_kernel(char *out, char *data, int len); -u32 PciWriteDword(unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg_off, unsigned int dw) +void BootSystemInitialization(void) { - - u32 base_addr = 0x80000000; - base_addr |= ((bus & 0xFF) << 16); // bus # - base_addr |= ((dev & 0x1F) << 11); // device # - base_addr |= ((func & 0x07) << 8); // func # - base_addr |= ((reg_off & 0xff)); - - IoOutputDword(0xcf8, base_addr ); - IoOutputDword(0xcfc ,dw); - - return 0; -} - -u32 PciReadDword(unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg_off) -{ - u32 base_addr = 0x80000000; - base_addr |= ((bus & 0xFF) << 16); // bus # - base_addr |= ((dev & 0x1F) << 11); // device # - base_addr |= ((func & 0x07) << 8); // func # - base_addr |= ((func & 0x07) << 8); - base_addr |= ((reg_off & 0xff)); - - IoOutputDword(0xcf8, base_addr); - return IoInputDword(0xcfc); + const u32 base = NV2A_MMIO_BASE; + register u32 res; + + /* check to see if we're an Original Xbox first */ + if (PciReadDword(BUS_0, DEV_0, FUNC_0, 0x00) == 0x02a510de) { /* Original Xbox PCI 0:0.0 ID [10de:02a5] */ + outb(0x02, 0x00ee); /* Turn LED green on OpenXenium, if connected */ + } else { + /* do something else if we're not */ + outb(0x90, 0x0080); + outb(0x03, 0x00ee); /* Turn LED yellow on OpenXenium, if connected */ + while (1); + } + + /* translated to C from Xcodes.h */ + PciWriteDword(BUS_0, DEV_1, FUNC_0, 0x84, 0x00008001); /* AMD-768 System Management (PM) IO BAR0 */ + PciWriteDword(BUS_0, DEV_1, FUNC_0, 0x10, 0x00008001); /* AMD-768 System Management (PM) IO BAR0 */ + PciWriteDword(BUS_0, DEV_1, FUNC_0, 0x04, 0x00000003); + outb(0x08, 0x8049); /* PM49 - TCO timer halt */ + outb(0x00, 0x80d9); /* PMD9 - GPIO25 input mode */ + outb(0x01, 0x8026); /* PM26 */ + PciWriteDword(BUS_0, DEV_1e, FUNC_0, 0x4c, 0x00000001); + PciWriteDword(BUS_0, DEV_1e, FUNC_0, 0x18, 0x00010100); + PciWriteDword(BUS_0, DEV_0, FUNC_0, 0x84, 0x07ffffff); + PciWriteDword(BUS_0, DEV_1e, FUNC_0, 0x20, base | 0x00f00000 | (base >> 16)); /* was 0x0ff00f00 */ + PciWriteDword(BUS_0, DEV_1e, FUNC_0, 0x24, 0xf7f0f000); + PciWriteDword(BUS_1, DEV_0, FUNC_0, 0x10, base); /* was 0x0f000000; set NV2A MMIO BAR0 higher */ + PciWriteDword(BUS_1, DEV_0, FUNC_0, 0x14, 0xf0000000); + PciWriteDword(BUS_1, DEV_0, FUNC_0, 0x04, 0x00000007); + PciWriteDword(BUS_0, DEV_1e, FUNC_0, 0x04, 0x00000007); +#ifndef MCPXREVD5 + writel(0x07633461, base + 0x0010b0); /* NV_PBUS_DEBUG_CTRIM_0 */ +#else + writel(0x01000010, base + 0x0010b0); /* NV_PBUS_DEBUG_CTRIM_0 */ +#endif + writel(0x66660000, base + 0x0010cc); /* NV_PBUS_DEBUG_CTRIM_6 */ + res = readl(base + 0x101000); /* NV_PEXTDEV_BOOT_0 */ + res &= 0x000c0000; /* NV_PEXTDEV_BOOT_0_STRAP_EMRS */ + if (!res) { /* NV_PEXTDEV_BOOT_0_STRAP_EMRS_MICRON */ + res = readl(base + 0x101000); /* NV_PEXTDEV_BOOT_0 */ + res &= 0xe1f3ffff; + res |= 0x80000000; /* NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE */ + writel(res, base + 0x101000); /* NV_PEXTDEV_BOOT_0 */ + writel(0xeeee0000, base + 0x0010b8); /* NV_PBUS_DEBUG_CTRIM_2 */ + } else if (res == 0x000c0000) { /* NV_PEXTDEV_BOOT_0_STRAP_EMRS_REDUCED_DRIVE */ + res = readl(base + 0x101000); /* NV_PEXTDEV_BOOT_0 */ + res &= 0xe1f3ffff; + res |= 0x860c0000; /* NV_PEXTDEV_BOOT_0_STRAP_{EMRS_REDUCED_DRIVE,OVERWRITE} | 0x06000000 */ + writel(res, base + 0x101000); /* NV_PEXTDEV_BOOT_0 */ + writel(0xffff0000, base + 0x0010b8); /* NV_PBUS_DEBUG_CTRIM_2 */ + } else { + res = readl(base + 0x101000); /* NV_PEXTDEV_BOOT_0 */ + res &= 0xe1f3ffff; + res |= 0x820c0000; /* NV_PEXTDEV_BOOT_0_STRAP_{EMRS_REDUCED_DRIVE,OVERWRITE} | 0x02000000 */ + writel(res, base + 0x101000); /* NV_PEXTDEV_BOOT_0 */ + writel(0x11110000, base + 0x0010b8); /* NV_PBUS_DEBUG_CTRIM_2 */ + } + writel(0x00000009, base + 0x0010d4); /* NV_PBUS_DEBUG_CTRIM_7_CCDP_TRIM */ + writel(0x00000000, base + 0x0010b4); /* NV_PBUS_DEBUG_CTRIM_1_INIT */ + writel(0x00005866, base + 0x0010bc); /* NV_PBUS_DEBUG_CTRIM_3_C[0-3]_DELAY */ + writel(0x0351c858, base + 0x0010c4); /* NV_PBUS_DEBUG_CTRIM_4_C[0-6]_DELAY */ + writel(0x30007d67, base + 0x0010c8); /* NV_PBUS_DEBUG_CTRIM_5_C{0,1,2,3,7}_DELAY */ + writel(0x00000000, base + 0x0010d8); /* NV_PBUS_DEBUG_CTRIM_8_DQSOB_[0-7]_INIT */ + writel(0xa0423635, base + 0x0010dc); /* NV_PBUS_DEBUG_CTRIM_9_NV_{PA0,PA1,PA2,PA3,CM,TM,NB}_TRIM */ + writel(0x0c6558c6, base + 0x0010e8); /* NV_PBUS_DEBUG_CTRIM_10_M_{NW,FB,PA0,PA1,PA2,PA3,NB}_TRIM */ + writel(0x03070103, base + 0x100200); /* NV_PFB_CFG0_{PART_4,EXTBANK_1,BURST_INT_{RD2RD,WR2WR,RD2PRE},AUTO_PRE_{RD,WR}} */ + writel(0x11000016, base + 0x100410); /* NV_PFB_WBC_{HWM_22,ATOMIC_CPU_READS,32B_WRITE_BLOCKS_READS} */ + writel(0x84848888, base + 0x100330); /* NV_PFB_ARB_XFER_SZ */ + writel(0xffffcfff, base + 0x10032c); /* NV_PFB_ARB_TIMEOUT */ + writel(0x00000001, base + 0x100328); /* NV_PFB_ARB_PREDIVIDER_DIV_1 */ + writel(0x000000df, base + 0x100338); /* NV_PFB_ARB_DIFF_BANK_{EXT,LP,ZO,TX,ZR,CR,CW} */ + + /* initialize SMBus controller */ + PciWriteDword(BUS_0, DEV_1, FUNC_1, 0x04, 0x00000001); + PciWriteDword(BUS_0, DEV_1, FUNC_1, 0x14, SMBUS | 1); + PciWriteDword(BUS_0, DEV_1, FUNC_1, 0x18, SMBUS+0x200 | 1); + outb(0x70, SMBUS+0x200); + + /* initialize video encoder */ + /* + * It is necessary to write to the video encoder, as the PIC + * snoops the I2C traffic and will reset us if it doesn't see what + * it judges as 'appropriate' traffic. Conexant is the most urgent, + * as on v1.0 Xboxes, the PIC was very strict and reset us earlier + * than later models. + */ + do { + /* Conexant (CX25871) video encoder */ + smbus_set_addr(0x8a); + smbus_write_start(0xba, 0x3f); /* SLAVER | DACOFF | DACDIS{D,C,B,A} */ + if (smbus_cycle_completed()) { + smbus_write(0x6c, 0x46); /* EN_REG_RD | EACTIVE | FLD_MODE[1] */ + smbus_write(0xb8, 0x00); /* autoconfiguration register */ + smbus_write(0xce, 0x19); /* OUT_MUXC[0] | OUT_MUXB[1] | OUT_MUXA[0] */ + smbus_write(0xc6, 0x9c); /* EN_BLANKO | {V,H}SYNCI | IN_MODE[2] */ + smbus_write(0x32, 0x08); /* IN_MODE[3] */ + smbus_write(0xc4, 0x01); /* EN_OUT */ + break; + } + + /* Focus (FS454) video encoder */ + smbus_set_addr(0xd4); + smbus_write_start(0x0c, 0x00); + if (smbus_cycle_completed()) { + smbus_write(0x0d, 0x20); + break; + } + + /* Xcalibur video encoder */ + smbus_set_addr(0xe0); + smbus_write_start(0x00, 0x00); + if (smbus_cycle_completed()) { + smbus_write(0xb8, 0x00); + break; + } + } while (0); + + smbus_set_addr(0x20); /* set PIC address; write command */ + smbus_write(0x01, 0x00); + smbus_set_addr(0x21); /* set PIC address; read command */ + res = smbus_read(0x01); /* if SMC version does not match ... ????? */ + + writel(0x00011c01, base + 0x680500); /* NV_PRAMDAC_NVPLL_COEFF - NVCLK clock speed == 233 MHz */ + writel(0x000a0400, base + 0x68050c); /* NV_PRAMDAC_PLL_COEFF_SELECT_{NVSOURCE_PROG,VS_PCLK{,2}_TV_PCLK */ + writel(0x00000000, base + 0x001220); /* NV_PBUS_FBIO_CALEN */ + writel(0x00000000, base + 0x001228); /* NV_PBUS_FBIO_CALSEL */ + writel(0x00000000, base + 0x001264); /* NV_PBUS_TVDIO_CALEN */ + writel(0x00000010, base + 0x001210); /* NV_PBUS_FBIO_CFG_CLK_EDGE_EARLY */ + res = readl(base + 0x101000); /* NV_PEXTDEV_BOOT_0 */ + res &= 0x06000000; /* NV_PEXTDEV_BOOT_0_STRAP_USER */ + if (!res) { /* NV_PEXTDEV_BOOT_0_STRAP_EMRS_MICRON */ + writel(0x48480848, base + 0x001214); /* NV_PBUS_FBIO_DLY */ + writel(0x88888888, base + 0x00122c); /* NV_PBUS_FBIO_ADRDRV */ + } else { /* NV_PEXTDEV_BOOT_0_STRAP_EMRS_REDUCED_DRIVE */ + writel(0x09090909, base + 0x001214); /* NV_PBUS_FBIO_DLY */ + writel(0xaaaaaaaa, base + 0x00122c); /* NV_PBUS_FBIO_ADRDRV */ + } + writel(0xffffffff, base + 0x001230); /* NV_PBUS_FBIO_CLKDRV */ + writel(0xaaaaaaaa, base + 0x001234); /* NV_PBUS_FBIO_DATDRV */ + writel(0xaaaaaaaa, base + 0x001238); /* NV_PBUS_FBIO_DQSDRV */ + writel(0x8b8b8b8b, base + 0x00123c); /* NV_PBUS_FBIO_ADRSLW */ + writel(0xffffffff, base + 0x001240); /* NV_PBUS_FBIO_CLKSLW */ + writel(0x8b8b8b8b, base + 0x001244); /* NV_PBUS_FBIO_DATSLW */ + writel(0x8b8b8b8b, base + 0x001248); /* NV_PBUS_FBIO_DQSSLW */ + writel(0x00000001, base + 0x1002d4); /* NV_PFB_PRE_CMD_PRECHARGE_1 */ + writel(0x00100042, base + 0x1002c4); /* NV_PFB_EMRS_{A{1,6},BA0}_1 */ + writel(0x00100042, base + 0x1002cc); /* NV_PFB_EMRS_EXT_{A{1,6},BA0}_1 */ + writel(0x00000011, base + 0x1002c0); /* NV_PFB_MRS_A{0,4}_1 */ + writel(0x00000011, base + 0x1002c8); /* NV_PFB_MRS_EXT_A{0,4}_1 */ + writel(0x00000032, base + 0x1002c0); /* NV_PFB_MRS_A{1,4,5}_1 */ + writel(0x00000032, base + 0x1002c8); /* NV_PFB_MRS_EXT_A{1,4,5}_1 */ + writel(0x00000132, base + 0x1002c0); /* NV_PFB_MRS_A{1,4,5,8}_1 */ + writel(0x00000132, base + 0x1002c8); /* NV_PFB_MRS_EXT_A{1,4,5,8}_1 */ + writel(0x00000001, base + 0x1002d0); /* NV_PFB_REF_CMD_REFRESH_1 */ + writel(0x00000001, base + 0x1002d0); /* NV_PFB_REF_CMD_REFRESH_1 */ + writel(0x80000000, base + 0x100210); /* NV_PFB_REFCTRL_VALID_1 */ + writel(0xaa8baa8b, base + 0x00124c); /* NV_PBUS_DISPIO_PADCTL */ + writel(0x0000aa8b, base + 0x001250); /* NV_PBUS_TVDIO_PADCTL */ + writel(0x081205ff, base + 0x100228); /* NV_PFB_TIMING2 */ + writel(0x00010000, base + 0x001218); /* NV_PBUS_FBIO_RAM_VREF_ENABLED */ + res = PciReadDword(BUS_0, DEV_1, FUNC_0, 0x60); + res |= 0x00000400; + PciWriteDword(BUS_0, DEV_1, FUNC_0, 0x60, res); + PciWriteDword(BUS_0, DEV_1, FUNC_0, 0x4c, 0x0000fdde); + PciWriteDword(BUS_0, DEV_1, FUNC_0, 0x9c, 0x871cc707); + res = PciReadDword(BUS_0, DEV_1, FUNC_0, 0xb4); + res |= 0x00000f00; + PciWriteDword(BUS_0, DEV_1, FUNC_0, 0xb4, res); + PciWriteDword(BUS_0, DEV_0, FUNC_3, 0x40, 0xf0f0c0c0); + PciWriteDword(BUS_0, DEV_0, FUNC_3, 0x44, 0x00c00000); + PciWriteDword(BUS_0, DEV_0, FUNC_3, 0x5c, 0x04070000); + PciWriteDword(BUS_0, DEV_0, FUNC_3, 0x6c, 0x00230801); /* FSB clock speed == 133 MHz; no override */ + PciWriteDword(BUS_0, DEV_0, FUNC_3, 0x6c, 0x01230801); /* FSB clock speed == 133 MHz; override */ + writel(0x03070103, base + 0x100200); /* NV_PFB_CFG0_{PART_4,EXTBANK_1,BURST_INT_{RD2RD,WR2WR,RD2PRE},AUTO_PRE_{RD,WR}} */ + writel(0x11448000, base + 0x100204); /* NV_PFB_CFG1_{COL_8,ROW{A,B}_12,BANK{A,B}_2} */ + PciWriteDword(BUS_0, DEV_2, FUNC_0, 0x3c, 0x00000000); + + /* report memory size to PIC scratch register */ + smbus_set_addr(0x20); /* set PIC address; write command */ + smbus_write(0x13, 0x0f); + smbus_write(0x12, 0xf0); + + /* execution continues in 2bBootStartup.S */ + goto *0xfffc1000; } -void BootAGPBUSInitialization(void) +static INLINE void BootAGPBUSInitialization(void) { - u32 temp; - PciWriteDword(BUS_0, DEV_1, FUNC_0, 0x54, PciReadDword(BUS_0, DEV_1, FUNC_0, 0x54) | 0x88000000 ); - - PciWriteDword(BUS_0, DEV_0, FUNC_0, 0x64, (PciReadDword(BUS_0, DEV_0, FUNC_0, 0x64))| 0x88000000 ); + register u32 res; - temp = PciReadDword(BUS_0, DEV_0, FUNC_0, 0x6C); - IoOutputDword(0xcfc , temp & 0xFFFFFFFE); - IoOutputDword(0xcfc , temp ); + PciWriteDword(BUS_0, DEV_1, FUNC_0, 0x54, PciReadDword(BUS_0, DEV_1, FUNC_0, 0x54) | 0x88000000); + PciWriteDword(BUS_0, DEV_0, FUNC_0, 0x64, PciReadDword(BUS_0, DEV_0, FUNC_0, 0x64) | 0x88000000); - PciWriteDword(BUS_0, DEV_0, FUNC_0, 0x80, 0x00000100); + res = PciReadDword(BUS_0, DEV_0, FUNC_0, 0x6c); + outl(res & 0xfffffffe, PCI_CFG_DATA); + outl(res, PCI_CFG_DATA); + PciWriteDword(BUS_0, DEV_0, FUNC_0, 0x80, 0x00000100); } /* ------------------------- Main Entry for after the ASM sequences ------------------------ */ -extern void BootStartBiosLoader ( void ) { - +void BootStartBiosLoader(void) +{ // do not change this, this is linked to many many scipts unsigned int PROGRAMM_Memory_2bl = 0x00100000; unsigned int CROMWELL_Memory_pos = 0x03A00000; @@ -210,3 +368,4 @@ extern void BootStartBiosLoader ( void ) { while(1); } + diff --git a/boot_rom/2bBootStartup.S b/boot_rom/2bBootStartup.S index defbd26f..0f9d18da 100644 --- a/boot_rom/2bBootStartup.S +++ b/boot_rom/2bBootStartup.S @@ -23,37 +23,7 @@ Xcalibur support by Lehner Franz (franz@caos.at) */ -#include "2bconsts.h" - -#define xcode_peek(val1) .byte 0x2; .long val1 ; .long 0x0 ; -#define xcode_poke(val1,val2) .byte 0x3; .long val1 ; .long val2 ; -#define xcode_pciout(val1,val2) .byte 0x4; .long val1 ; .long val2 ; -#define xcode_pciin_a(val1) .byte 0x5; .long val1 ; .long 0x0 ; - -#define xcode_bittoggle(val1,val2) .byte 0x6; .long val1 ; .long val2 ; - -#define xcode_ifgoto(val1,val2) .byte 0x8; .long val1 ; .long (9*(val2-1)) ; - -#define xcode_outb(val1,val2) .byte 0x11; .long val1 ; .long val2 ; -#define xcode_inb(val1) .byte 0x12; .long val1 ; .long 0x0 ; - -#define xcode_poke_a(val1) .byte 0x7; .long 0x3; .long val1 ; -#define xcode_pciout_a(val1) .byte 0x7; .long 0x4; .long val1 ; -#define xcode_outb_a(val1) .byte 0x7; .long 0x11; .long val1 ; - -#define xcode_goto(val1) .byte 0x9; .long 0x0; .long (9*(val1-1)); - -#define xcode_END(val1) .byte 0xEE; .long val1 ; .long 0x0; - -#define SMBUS 0x0000c000 - - -#define SMB_xcode_Write(val1,val2); xcode_outb(SMBUS+8, val1); \ - xcode_outb(SMBUS+6, val2); \ - xcode_outb(SMBUS+2, 0x0000000a); \ - xcode_inb(SMBUS); \ - xcode_ifgoto(0x00000010,-1); \ - xcode_outb(SMBUS, 0x00000010); +#include "consts.h" .code32 @@ -85,9 +55,9 @@ .long 0xffffffff .long 0xffffffff - .org 0x40 - .long _start_checksum // This number will be overwritten - // With imagebld, but we need a temp value + .org 0x40 // imagebld temporary values + .long _start_checksum + .long _reset_vector_base .org 0x6c .long 0x00000107 @@ -288,13 +258,13 @@ tableGdtDescriptor: .word 0x30 .long tableGdt - .word 0x0 // fill Word, so we get alliged again + .word 0 // fill word for alignment tableIdtDescriptor: .word 2048 .long 0x400000 - .word 0x0 // fill Word, so we get alliged again + .word 0 // fill word for alignment initaftermemcpy: /* @@ -360,7 +330,6 @@ reload_cs: movl $0x40000000, %eax outl %eax, %dx - // CPU Whoami ? sesless ? mov $0x80000080, %eax movw $0xcf8, %dx @@ -369,7 +338,104 @@ reload_cs: movl $0x100, %eax outl %eax, %dx - - // this can be found in BootResetAction.c + // this can be found in 2bBootStartBios.c jmp BootStartBiosLoader + +/* Initial 16-bit x86 Reset Vector Block */ +.section .reset_vector_base, "ax" + +/* + * This is where the nForce specific table resides & is needed + * on nForce boards to start execution at the reset vector. + * Called "nVMB" in vendor BIOS. Structure is not known. + */ + + .byte 0x65, 0xd0, 0x16, 0x2b, 0x3c, 0x34, 0x33, 0x33, 0x03, 0x03, 0x03, 0x03, 0x0e, 0x1c, 0x1c, 0x1c + .byte 0x03, 0x1c, 0xe0, 0x00, 0x8a, 0x70, 0xe4, 0xf8, 0x31, 0xd3, 0x67, 0x65, 0xd0, 0x0d, 0xe3, 0x00 + .byte 0xc0, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 + .byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + .byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + .byte 0x03, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + .byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + .byte 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + .byte 0xd9, 0x40, 0x24, 0x00, 0x00, 0xdb, 0x17, 0x1d, 0xd9, 0x40, 0x25, 0x00, 0x00, 0xdb, 0x17, 0x1d + .byte 0xd9, 0x40, 0x25, 0x00, 0x00, 0xdb, 0x17, 0x1d, 0xd9, 0x40, 0x26, 0x00, 0x00, 0xdb, 0x17, 0x1d + .byte 0xd9, 0x40, 0x23, 0x00, 0x00, 0xe4, 0x27, 0x25, 0xd9, 0x40, 0x24, 0x00, 0x00, 0xe4, 0x27, 0x25 + .byte 0xd9, 0x40, 0x25, 0x00, 0x00, 0xe4, 0x27, 0x25, 0xd9, 0x40, 0x26, 0x00, 0x00, 0xe4, 0x27, 0x25 + .byte 0xd9, 0x40, 0x20, 0x00, 0x00, 0xe4, 0x17, 0x25, 0xd9, 0x40, 0x21, 0x00, 0x00, 0xe4, 0x17, 0x25 + .byte 0xd9, 0x40, 0x21, 0x00, 0x00, 0xe4, 0x17, 0x25, 0xd9, 0x40, 0x22, 0x00, 0x00, 0xe4, 0x17, 0x25 + .byte 0xd9, 0x40, 0x22, 0x00, 0x00, 0xdb, 0x17, 0x1d, 0xd9, 0x40, 0x23, 0x00, 0x00, 0xdb, 0x17, 0x1d + .byte 0xd9, 0x40, 0x23, 0x00, 0x00, 0xdb, 0x17, 0x1d, 0xd9, 0x40, 0x24, 0x00, 0x00, 0xdb, 0x17, 0x1d + +.section .reset_vector.start, "ax" + +.align 16 + +gdt: + + .byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0x00 dummy + .byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x9b, 0xcf, 0x00 // 0x08 code32 + .byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x9b, 0xcf, 0x00 // 0x10 code32 + .byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x93, 0xcf, 0x00 // 0x18 data32 + .byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x9b, 0x8f, 0x00 // 0x20 code16 (8f indicates 4K granularity, ie, huge limit) + .byte 0xff, 0xff, 0x00, 0x00, 0x00, 0x93, 0x8f, 0x00 // 0x28 data16 + +gdt_end: + +.align 8 + +gdt_desc: + + .word gdt_end - gdt + .long gdt + .word 0 // fill word for alignment + +.align 8 + +idt_desc: + + .word 0 + .long 0 + .word 0 // fill word for alignment + +.align 16 + +start_32: + + xor %eax, %eax + mov $0x18, %al // Set SS, DS, and ES to a data32 segment with maximum limit. + mov %eax, %ds + mov %eax, %es + mov %eax, %ss + xor %eax, %eax // Clear FS and GS + mov %eax, %fs + mov %eax, %gs + + // Use function attribute "naked" if jumping to C, + // as RAM is not yet available to set a valid stack. + + // this can be found in 2bBootStartBios.c + jmp BootSystemInitialization + +.align 16 + +.code16 + +start_16: + + cli // Disable interrupts + in $0xee, %al // Enable A20 (pull A20M# high via OpenXenium QPI, if connected) + xor %eax, %eax + mov %eax, %cr3 // Invalidate TLB + lgdtl %cs:gdt_desc // Load GDT + lidtl %cs:idt_desc // Load null IDT + mov %cr0, %eax // Enable "Protected Mode" + or $0x1, %al // - Bit 0: Protected Mode Enable + mov %eax, %cr0 + ljmpl $0x10, $start_32 + +.section .reset_vector, "ax" + + jmp start_16 + diff --git a/boot_rom/2bconsts.h b/boot_rom/2bconsts.h deleted file mode 100644 index 763f6a71..00000000 --- a/boot_rom/2bconsts.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * - * includes for startup code in a form usable by the .S files - * - */ - - /*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - ***************************************************************************/ - -#define PCI_CFG_ADDR 0x0CF8 -#define PCI_CFG_DATA 0x0CFC - -#define MTRR_DEF 0x2ff -#define MTRR_DEF_TYPE 0x800 -#define MTRR_PHYSBASE 0x200 -#define MTRR_LAST 0x20F -#define WB_CACHE 6 -#define BASE0_H 0 -#define BASE0_L WB_CACHE -#define MASK0_H 0x0F -#define MASK0_L 0xFC000800 -#define BASE1_H 0 -#define BASE1_L 0xFFF80005 -#define MASK1_H 0x0F -#define MASK1_L 0x0FFF80800 - -#define I2C_IO_BASE 0xc000 - -#define BUS_0 0 -#define BUS_1 1 - -#define DEV_0 0 -#define DEV_1 1 -#define DEV_2 2 -#define DEV_3 3 -#define DEV_4 4 -#define DEV_5 5 -#define DEV_6 6 -#define DEV_7 7 -#define DEV_8 8 -#define DEV_9 9 -#define DEV_a 0xa -#define DEV_b 0xb -#define DEV_c 0xc -#define DEV_d 0xd -#define DEV_e 0xe -#define DEV_f 0xf -#define DEV_10 0x10 -#define DEV_11 0x11 -#define DEV_12 0x12 -#define DEV_13 0x13 -#define DEV_14 0x14 -#define DEV_15 0x15 -#define DEV_16 0x16 -#define DEV_17 0x17 -#define DEV_18 0x18 -#define DEV_19 0x19 -#define DEV_1a 0x1a -#define DEV_1b 0x1b -#define DEV_1c 0x1c -#define DEV_1d 0x1d -#define DEV_1e 0x1e -#define DEV_1f 0x1f - -#define FUNC_0 0 diff --git a/boot_rom/2bload.h b/boot_rom/2bload.h index a7a48137..dbb0409b 100644 --- a/boot_rom/2bload.h +++ b/boot_rom/2bload.h @@ -10,7 +10,7 @@ * * ***************************************************************************/ -#include "2bconsts.h" +#include "consts.h" #include "stdint.h" #include "cromwell_types.h" @@ -47,34 +47,124 @@ enum { /* ---------------------------- IO primitives ----------------------------------------------------------- */ -static __inline void IoOutputByte(u16 wAds, u8 bValue) { - __asm__ __volatile__ ("outb %b0,%w1": :"a" (bValue), "Nd" (wAds)); +static INLINE void IoOutputByte(u16 wAds, u8 bValue) +{ + __asm__ __volatile__ ("outb %b0,%w1" : : "a" (bValue), "Nd" (wAds)); } -static __inline void IoOutputWord(u16 wAds, u16 wValue) { - __asm__ __volatile__ ("outw %0,%w1": :"a" (wValue), "Nd" (wAds)); - } +static INLINE void IoOutputWord(u16 wAds, u16 wValue) +{ + __asm__ __volatile__ ("outw %0,%w1" : : "a" (wValue), "Nd" (wAds)); +} + +static INLINE void IoOutputDword(u16 wAds, u32 dwValue) +{ + __asm__ __volatile__ ("outl %0,%w1" : : "a" (dwValue), "Nd" (wAds)); +} + +static INLINE u8 IoInputByte(u16 wAds) +{ + register u8 ret; + + __asm__ __volatile__ ("inb %w1,%0" : "=a" (ret) : "Nd" (wAds)); + + return ret; +} + +static INLINE u16 IoInputWord(u16 wAds) +{ + register u16 ret; + + __asm__ __volatile__ ("inw %w1,%0" : "=a" (ret) : "Nd" (wAds)); + + return ret; +} + +static INLINE u32 IoInputDword(u16 wAds) +{ + register u32 ret; + + __asm__ __volatile__ ("inl %w1,%0" : "=a" (ret) : "Nd" (wAds)); + + return ret; +} + +static INLINE void PciWriteDword(u32 bus, u32 dev, u32 func, u32 off, u32 data) +{ + register u32 addr = 0x80000000; + + addr |= (bus & 0xff) << 16; // bus # + addr |= (dev & 0x1f) << 11; // device # + addr |= (func & 0x07) << 8; // func # + addr |= (off & 0xff); // reg offset + + outl(addr, PCI_CFG_ADDR); + outl(data, PCI_CFG_DATA); +} + +static INLINE u32 PciReadDword(u32 bus, u32 dev, u32 func, u32 off) +{ + register u32 addr = 0x80000000; + + addr |= (bus & 0xff) << 16; // bus # + addr |= (dev & 0x1f) << 11; // device # + addr |= (func & 0x07) << 8; // func # + addr |= (off & 0xff); // reg offset + + outl(addr, PCI_CFG_ADDR); + return inl(PCI_CFG_DATA); +} + +static INLINE void smbus_set_addr(u8 addr) +{ + outb(0xff, SMBUS); /* clear any status */ + outb(addr, SMBUS + 4); /* set host address */ +} + +static INLINE u8 smbus_wait(void) +{ + register u8 ret; + + while ((ret = inb(SMBUS)) & SMBUS_HST_BSY); /* host controller busy loop */ + outb(SMBUS_HCYC_STS, SMBUS); /* clear host cycle complete status */ + + return ret; +} + +static INLINE int smbus_cycle_completed(void) +{ + return smbus_wait() == SMBUS_HCYC_STS; +} + +static INLINE void smbus_write_start(u8 cmd, u8 data) +{ + outb(cmd, SMBUS + 8); /* set host command */ + outb(data, SMBUS + 6); /* set host data */ + outb(0x0a, SMBUS + 2); /* set host start; CYCTYPE == read or write byte | HOSTST */ +} -static __inline void IoOutputDword(u16 wAds, u32 dwValue) { - __asm__ __volatile__ ("outl %0,%w1": :"a" (dwValue), "Nd" (wAds)); +static INLINE void smbus_write(u8 cmd, u8 data) +{ + smbus_write_start(cmd, data); + smbus_wait(); } -static __inline u8 IoInputByte(u16 wAds) { - unsigned char _v; - __asm__ __volatile__ ("inb %w1,%0":"=a" (_v):"Nd" (wAds)); - return _v; +static INLINE void smbus_read_start(u8 cmd) +{ + outb(cmd, SMBUS + 8); /* set host command */ + outb(0x0a, SMBUS + 2); /* set host start; CYCTYPE == read or write byte | HOSTST */ } -static __inline u16 IoInputWord(u16 wAds) { - u16 _v; - __asm__ __volatile__ ("inw %w1,%0":"=a" (_v):"Nd" (wAds)); - return _v; +static INLINE u8 smbus_read_data(void) +{ + return inb(SMBUS + 6); /* get host data */ } -static __inline u32 IoInputDword(u16 wAds) { - u32 _v; - __asm__ __volatile__ ("inl %w1,%0":"=a" (_v):"Nd" (wAds)); - return _v; +static INLINE u8 smbus_read(u8 cmd) +{ + smbus_read_start(cmd); + smbus_wait(); + return smbus_read_data(); } // boot process @@ -85,6 +175,7 @@ int I2cResetFrontpanelLed(void); ////////// BootResetActions.c +void BootSystemInitialization(void) __attribute__((section(".reset_vector.1bl"),aligned(16),naked)); void BootStartBiosLoader(void); ///////// BootPerformPicChallengeResponseAction.c diff --git a/boot_rom/Xcodes.h b/boot_rom/Xcodes.h index e6574438..437c7769 100644 --- a/boot_rom/Xcodes.h +++ b/boot_rom/Xcodes.h @@ -23,6 +23,34 @@ Xcalibur support by Lehner Franz (franz@caos.at) */ +#define xcode_peek(val1) .byte 0x2; .long val1 ; .long 0x0 ; +#define xcode_poke(val1,val2) .byte 0x3; .long val1 ; .long val2 ; +#define xcode_pciout(val1,val2) .byte 0x4; .long val1 ; .long val2 ; +#define xcode_pciin_a(val1) .byte 0x5; .long val1 ; .long 0x0 ; + +#define xcode_bittoggle(val1,val2) .byte 0x6; .long val1 ; .long val2 ; + +#define xcode_ifgoto(val1,val2) .byte 0x8; .long val1 ; .long (9*(val2-1)) ; + +#define xcode_outb(val1,val2) .byte 0x11; .long val1 ; .long val2 ; +#define xcode_inb(val1) .byte 0x12; .long val1 ; .long 0x0 ; + +#define xcode_poke_a(val1) .byte 0x7; .long 0x3; .long val1 ; +#define xcode_pciout_a(val1) .byte 0x7; .long 0x4; .long val1 ; +#define xcode_outb_a(val1) .byte 0x7; .long 0x11; .long val1 ; + +#define xcode_goto(val1) .byte 0x9; .long 0x0; .long (9*(val1-1)); + +#define xcode_END(val1) .byte 0xEE; .long val1 ; .long 0x0; + +#define SMB_xcode_Write(val1,val2) \ + xcode_outb(SMBUS+8, val1); \ + xcode_outb(SMBUS+6, val2); \ + xcode_outb(SMBUS+2, 0x0000000a); \ + xcode_inb(SMBUS); \ + xcode_ifgoto(0x00000010,-1); \ + xcode_outb(SMBUS, 0x00000010); + //The bytecode interpreter begins here xcode_pciout(0x80000884, 0x00008001); xcode_pciout(0x80000810, 0x00008001); @@ -291,7 +319,7 @@ // mov eax, 0xfffc1000 // jmp eax // nop - xcode_poke(0x00000000, 0xfc1000B8); + xcode_poke(0x00000000, 0xfc1000b8); xcode_poke(0x00000004, 0x90e0ffff); diff --git a/boot_rom/bootrom.ld b/boot_rom/bootrom.ld index a60ca1fa..69f799e3 100644 --- a/boot_rom/bootrom.ld +++ b/boot_rom/bootrom.ld @@ -1,33 +1,39 @@ OUTPUT_FORMAT ("elf32-i386"); OUTPUT_ARCH(i386); + MEMORY { - ram (rwx) : ORIGIN = 0, LENGTH = 64M - rom (rx) : ORIGIN = 0xFFFC0000, LENGTH = 256K + RAM (RW) : ORIGIN = 0, LENGTH = 64M + ROM (RX) : ORIGIN = 0xfffc0000, LENGTH = 256K /* this should be changed depending on the actual size of the ROM */ } - RAM_CODE = 0x00100000; -/* this should be changed depending the actual size of the rom */ -ROM_SIZE = 256K; -LOW_ROM = 0xfffc0000; - - -TOP_ROM = ( LOW_ROM + ROM_SIZE - 512 ); -TOP_ROM_LOAD = ( ROM_SIZE - 512 ); +ROM_BASE = ORIGIN(ROM); +ROM_SIZE = LENGTH(ROM); +ROM_END = ROM_BASE + ROM_SIZE; -SECTIONS { - /DISCARD/ : { *(.note.gnu.property) } +RESET_VECTOR_BLOCK_SIZE = 4K; +RESET_VECTOR_BLOCK_BASE = ROM_END - RESET_VECTOR_BLOCK_SIZE; - /* ROM Part of the programm */ +SECTIONS +{ + /* ROM allocations */ - .low_rom LOW_ROM : AT ( 0x0 ){ + .low_rom ROM_BASE : AT ( 0 ) { *(.low_rom); _end_rom = . ; } - /* RAM Part of the programm */ + .reset_vector (RESET_VECTOR_BLOCK_BASE) : AT (RESET_VECTOR_BLOCK_BASE - ROM_BASE) { + _reset_vector_base = .; + *(.reset_vector_base) + *(.reset_vector.*) + . = ALIGN(RESET_VECTOR_BLOCK_SIZE) - 16; + *(.reset_vector) + } >ROM = 0x00 + + /* RAM allocations */ .text (RAM_CODE) : AT( SIZEOF(.low_rom) ) { _ram_location = .; @@ -35,7 +41,7 @@ SECTIONS { *(.text); *(.text.*) *(.eh_frame) - _start_checksum = _start_ramcopy - LOW_ROM; + _start_checksum = _start_ramcopy - ROM_BASE; } .data (RAM_CODE + SIZEOF(.text)) : AT( SIZEOF(.low_rom) + SIZEOF(.text)) { @@ -47,7 +53,7 @@ SECTIONS { *(.got.*); } - .rodata ( RAM_CODE + SIZEOF(.text) + SIZEOF(.data) ) : AT ( SIZEOF(.low_rom) + SIZEOF(.text) + SIZEOF(.data)) { + .rodata ( RAM_CODE + SIZEOF(.text) + SIZEOF(.data) ) : AT ( SIZEOF(.low_rom) + SIZEOF(.text) + SIZEOF(.data)) { *(.rodata); *(.rodata.str1.1); *(.rodata.str1.4); @@ -67,19 +73,22 @@ SECTIONS { BSS_END = .; } - /* We need to copy the .data section to to upper memory */ + /* We need to copy the .data section to upper memory */ - _size_ramcopy = SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.rodata) + SIZEOF(.bss); + _size_ramcopy = SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.rodata) + SIZEOF(.bss); _size_sha1hash = SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.rodata); -/* - .high_rom TOP_ROM : AT (TOP_ROM_LOAD) { - _start_top_rom = . ; - . = . + ( 512 - sizeof_top ); - *(.high_rom); - _end_top_rom = . ; - } = 0x90909090 -*/ + /DISCARD/ : { + *(.note.gnu.property) + *(.comment) + *(.note.GNU-stack) + *(.eh_frame) + *(.rela.eh_frame) + *(.shstrtab) + *(.symtab) + *(.strtab) + *(.got.plt) + } } BSS_SIZE = BSS_END - BSS_BASE; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index cd63a41e..74100ca5 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -329,7 +329,6 @@ void BootPciPeripheralInitialization(void) { __asm__ __volatile__ ( "cli" ); - PciWriteDword(BUS_0, DEV_1, 0, 0x80, 2); // v1.1 2BL kill ROM area if(PciReadByte(BUS_0, DEV_1, 0, 0x8)>=0xd1) { // check revision PciWriteDword(BUS_0, DEV_1, 0, 0xc8, 0x8f00); // v1.1 2BL <-- death } diff --git a/include/consts.h b/include/consts.h index 3f44816c..a09f0a63 100644 --- a/include/consts.h +++ b/include/consts.h @@ -16,20 +16,54 @@ * * ***************************************************************************/ +#define INLINE __inline__ __attribute__((always_inline)) +#define PACKED __attribute__((packed)) + +#define inb(addr) IoInputByte((addr)) +#define inw(addr) IoInputWord((addr)) +#define inl(addr) IoInputDword((addr)) +#define outb(val,addr) IoOutputByte((addr), (val)) +#define outw(val,addr) IoOutputWord((addr), (val)) +#define outl(val,addr) IoOutputDword((addr), (val)) +#define readb(addr) (*(volatile u8 *)(addr)) +#define readw(addr) (*(volatile u16 *)(addr)) +#define readl(addr) (*(volatile u32 *)(addr)) +#define writeb(val,addr) ((*(volatile u8 *)(addr)) = (val)) +#define writew(val,addr) ((*(volatile u16 *)(addr)) = (val)) +#define writel(val,addr) ((*(volatile u32 *)(addr)) = (val)) + #define PCI_CFG_ADDR 0x0CF8 #define PCI_CFG_DATA 0x0CFC +#define MTRR_DEF 0x2ff +#define MTRR_DEF_TYPE 0x800 +#define MTRR_PHYSBASE 0x200 +#define MTRR_LAST 0x20F +#define WB_CACHE 6 +#define BASE0_H 0 +#define BASE0_L WB_CACHE +#define MASK0_H 0x0F +#define MASK0_L 0xFC000800 +#define BASE1_H 0 +#define BASE1_L 0xFFF80005 +#define MASK1_H 0x0F +#define MASK1_L 0x0FFF80800 #define TIMER_IO 0x8008 #define TIMER_FREQ 0x369E99 -#define I2C_IO_BASE 0xC000 +#define I2C_IO_BASE 0xC000 +#define SMBUS I2C_IO_BASE +#define SMBUS_HST_BSY 0x08 /* PME0 - host controller busy */ +#define SMBUS_HCYC_STS 0x10 /* PME0 - host cycle complete status */ #define SERIAL_PORT 0x3F8 #define SERIAL_IRQ 4 #define SERIAL_THR 0 #define SERIAL_LSR 5 +#define NV2A_MMIO_BASE 0xfd000000 + #define BUS_0 0 #define BUS_1 1 @@ -67,12 +101,13 @@ #define DEV_1f 0x1f #define FUNC_0 0 -/* -#define boot_post_macro(value) \ - movb $(value), %al ;\ - outb %al, $0x80 -*/ +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7 #endif // _Consts_H_ - diff --git a/lib/imagebld/imagebld.c b/lib/imagebld/imagebld.c index a695e000..4ee15574 100644 --- a/lib/imagebld/imagebld.c +++ b/lib/imagebld/imagebld.c @@ -11,6 +11,7 @@ #include #include +#include #include "sha1.h" #include "md5.h" @@ -43,7 +44,6 @@ struct Checksumstruct { struct BiosIdentifier { - unsigned char Magic[4]; // AUTO unsigned char HeaderVersion; unsigned char XboxVersion; // Which Xbox Version does it Work ? (Options) @@ -52,10 +52,18 @@ struct BiosIdentifier { unsigned char Option1; unsigned char Option2; unsigned char Option3; + unsigned char Padding1; unsigned int BiosSize; // in Bytes +#if 0 // disabled to make use of the reset vector with MCPX X2 southbridges char Name[32]; unsigned char MD5Hash[16]; -}; +#else + char Name[20]; + unsigned int nForceTableOffset; // nForce boards read this table before executing at the reset vector + unsigned char Padding2[8]; + unsigned char ResetVector[16]; +#endif +} __attribute__((packed)); void showUsage(); @@ -69,14 +77,14 @@ void shax(unsigned char *result, unsigned char *data, unsigned int len) } -void writeBiosIdentifier(unsigned char *cromimage, int biosSize) { +void writeBiosIdentifier(unsigned char *cromimage, int biosSize, unsigned int resetvectorbase) { struct BiosIdentifier *BiosHeader = (struct BiosIdentifier *)&cromimage[biosSize-sizeof(struct BiosIdentifier)]; - MD5_CTX hashcontext; - unsigned char digest[16]; +// MD5_CTX hashcontext; + memset(BiosHeader, 0, offsetof(typeof(*BiosHeader), ResetVector)); memcpy(BiosHeader->Magic,"AUTO",4); BiosHeader->HeaderVersion=1; BiosHeader->BiosSize= biosSize; - sprintf(BiosHeader->Name,"Cromwell %s",CROMWELL_VERSION); + snprintf(BiosHeader->Name, sizeof(BiosHeader->Name), "Cromwell %s", CROMWELL_VERSION); BiosHeader->XboxVersion = BiosID_Version10 | BiosID_Version11 | @@ -89,9 +97,11 @@ void writeBiosIdentifier(unsigned char *cromimage, int biosSize) { BiosHeader->VideoEncoder = BiosID_VideoEncoder_Conexant | BiosID_VideoEncoder_Focus; - MD5Init(&hashcontext); - MD5Update(&hashcontext, cromimage, biosSize-16); - MD5Final(BiosHeader->MD5Hash, &hashcontext); +// MD5Init(&hashcontext); +// MD5Update(&hashcontext, cromimage, biosSize-16); +// MD5Final(BiosHeader->MD5Hash, &hashcontext); + + BiosHeader->nForceTableOffset = resetvectorbase; } int xberepair ( const char * xbeimage, @@ -289,13 +299,14 @@ int romcopy ( unsigned char *flash256; unsigned char *flash1024; unsigned char *crom; - unsigned int freeflashspace = 256*1024; - unsigned int romsize=0; - unsigned int a=0; + signed int freeflashspace = 256*1024; + unsigned int romsize=0; + unsigned int a=0; struct Checksumstruct bootloaderstruct ; - unsigned int bootloaderpos; - unsigned int temp; - struct stat fileinfo; + unsigned int bootloaderpos; + unsigned int resetvectorbase; + unsigned int temp; + struct stat fileinfo; loaderimage = malloc(256*1024); flash256 = malloc(256*1024); @@ -334,40 +345,15 @@ int romcopy ( // Ok, we have loaded both images, we can continue - // this is very nasty, but simple , we Dump a GDT to the TOP rom - - memset(&loaderimage[0x3fe00],0x90,512); - memset(&loaderimage[0x3ffd0],0x00,32); - loaderimage[0x3ffcf] = 0xfc; - loaderimage[0x3ffd0] = 0xea; - loaderimage[0x3ffd2] = 0x10; - loaderimage[0x3ffd3] = 0xfc; - loaderimage[0x3ffd4] = 0xff; - loaderimage[0x3ffd5] = 0x08; - loaderimage[0x3ffd7] = 0x90; - - loaderimage[0x3ffe0] = 0xff; - loaderimage[0x3ffe1] = 0xff; - loaderimage[0x3ffe5] = 0x9b; - loaderimage[0x3ffe6] = 0xcf; - loaderimage[0x3ffe8] = 0xff; - loaderimage[0x3ffe9] = 0xff; - loaderimage[0x3ffed] = 0x93; - loaderimage[0x3ffee] = 0xcf; - - loaderimage[0x3fff4] = 0x18; - loaderimage[0x3fff5] = 0x00; - loaderimage[0x3fff6] = 0xd8; - loaderimage[0x3fff7] = 0xff; - loaderimage[0x3fff8] = 0xff; - loaderimage[0x3fff9] = 0xff; - - // We have dumped the GDT now, we continue - - memcpy(&bootloaderpos,&loaderimage[0x40],4); // This can be foun in the 2bBootStartup.S - memset(&loaderimage[0x40],0x0,4); // We do not need this helper sum anymore + bootloaderpos = *(unsigned int *)&loaderimage[0x40]; // This can be found in 2bBootStartup.S + resetvectorbase = *(unsigned int *)&loaderimage[0x44]; + *(unsigned int *)&loaderimage[0x40] = 0; // Not needed anymore + *(unsigned int *)&loaderimage[0x44] = 0; memcpy(&bootloaderstruct,&loaderimage[bootloaderpos],sizeof(struct Checksumstruct)); + // Apply the SmartXX bios identifier data + writeBiosIdentifier(loaderimage, 256*1024, resetvectorbase); + memcpy(flash256,loaderimage,256*1024); memcpy(flash1024,loaderimage,256*1024); @@ -381,9 +367,8 @@ int romcopy ( bootloaderstruct.compressed_image_start = temp; bootloaderstruct.compressed_image_size = romsize; - //freeflashspace = freeflashspace - 512; // We decrement the TOP ROM - // We have no TOP ROM anymore - freeflashspace = freeflashspace - bootloaderstruct.compressed_image_start; + freeflashspace -= 4*1024; // decrement for the Reset Vector Block at the top of ROM + freeflashspace -= bootloaderstruct.compressed_image_start; bootloaderstruct.Biossize_type = 0; // Means it is a 256 kbyte Image memcpy(&flash256[bootloaderpos],&bootloaderstruct,sizeof(struct Checksumstruct)); @@ -435,12 +420,10 @@ int romcopy ( #endif // In 1MB flash we need the Image 2 times, as ... you know - memset(&flash1024[(0*256*1024)+bootloaderstruct.compressed_image_start],0xff,256*1024-bootloaderstruct.compressed_image_start-512); memcpy(&flash1024[3*256*1024],&flash1024[0],256*1024); // Ok, the 2BL loader is ready, we now go to the "Kernel" - memset(&flash256[bootloaderstruct.compressed_image_start+20+romsize],0xff,256*1024-(bootloaderstruct.compressed_image_start+20+romsize)-512); - // The first 20 bytes of the compressed image are the checksum + // The first 20 bytes of the compressed image are the checksum memcpy(&flash256[bootloaderstruct.compressed_image_start+20],&crom[0],romsize); SHA1Reset(&context); SHA1Input(&context,&flash256[bootloaderstruct.compressed_image_start+20],romsize); @@ -461,9 +444,6 @@ int romcopy ( printf("\n"); #endif - //Apply the SmartXX bios identifier data - writeBiosIdentifier(flash256, 256*1024); - writeBiosIdentifier(flash1024, 1024*1024); // Write the 256 /1024 Kbyte Image Back f = fopen(binname256, "w"); fwrite(flash256, 1, 256*1024, f); diff --git a/scripts/ldscript-crom.ld b/scripts/ldscript-crom.ld index 470aa81c..86d46a0c 100644 --- a/scripts/ldscript-crom.ld +++ b/scripts/ldscript-crom.ld @@ -1,33 +1,27 @@ -/* - * loader script - */ - OUTPUT_FORMAT ("elf32-i386"); OUTPUT_ARCH(i386); + MEMORY { - ram (rwx) : ORIGIN = 0, LENGTH = 64M - rom (rx) : ORIGIN = 0x03A00000, LENGTH = 2M + RAM (RW) : ORIGIN = 0, LENGTH = 64M + ROM (RX) : ORIGIN = 0x03a00000 /* 58MiB */, LENGTH = 256K /* this should be changed depending on the actual size of the ROM */ } -/* this should be changed depending the actual size of the rom */ -ROM_SIZE = 256K; -LOW_ROM = 0x03A00000; /* 58MB */ - -SECTIONS { - /DISCARD/ : { *(.note.gnu.property) } +ROM_BASE = ORIGIN(ROM); +ROM_SIZE = LENGTH(ROM); +ROM_END = ROM_BASE + ROM_SIZE; +SECTIONS +{ /* ROM allocations */ - .text LOW_ROM : AT ( 0 ){ - _start_low_rom = . ; + .text ROM_BASE : AT ( 0 ) { *(.text); *(.text.*) *(.eh_frame) - _end_low_rom = . ; } - .rodata (LOW_ROM + SIZEOF(.text)) : AT (SIZEOF(.text)) { + .rodata (ROM_BASE + SIZEOF(.text)) : AT (SIZEOF(.text)) { *(.rodata); *(.rodata.str1.1); *(.rodata.str1.32); @@ -45,7 +39,7 @@ SECTIONS { /* RAM allocations */ - .data (LOW_ROM + SIZEOF(.text) + SIZEOF(.rodata)) : AT( SIZEOF(.text) + SIZEOF(.rodata) ) { + .data (ROM_BASE + SIZEOF(.text) + SIZEOF(.rodata)) : AT( SIZEOF(.text) + SIZEOF(.rodata) ) { _start_data = .; *(.data); *(.data.*); @@ -58,7 +52,7 @@ SECTIONS { /* the data (initialized globals) is moved to ram by the startup code */ - .bss (LOW_ROM + SIZEOF(.text) + SIZEOF(.rodata) + SIZEOF(.data)) : AT( SIZEOF(.text) + SIZEOF(.rodata) + SIZEOF(.data)) { + .bss (ROM_BASE + SIZEOF(.text) + SIZEOF(.rodata) + SIZEOF(.data)) : AT( SIZEOF(.text) + SIZEOF(.rodata) + SIZEOF(.data)) { BSS_BASE = .; _bss = .; *(.bss) @@ -70,6 +64,18 @@ SECTIONS { } _end_complete_rom = SIZEOF(.text) + SIZEOF(.rodata) + SIZEOF(.data) + SIZEOF(.bss); + + /DISCARD/ : { + *(.note.gnu.property) + *(.comment) + *(.note.GNU-stack) + *(.eh_frame) + *(.rela.eh_frame) + *(.shstrtab) + *(.symtab) + *(.strtab) + *(.got.plt) + } } BSS_SIZE = BSS_END - BSS_BASE;