swd.adoc

th.swd

Synopsis

Store two 32-bit values to memory from two GPRs.

Mnemonic

th.swd rd1, rd2, (rs1), imm2, 3

Encoding

{reg:[
    { bits:  7, name: 0xb, attr: ['custom-0, 32 bit'] },
    { bits:  5, name: 'rd1' },
    { bits:  3, name: 0x5, attr: ['Mem-Store'] },
    { bits:  5, name: 'rs1' },
    { bits:  5, name: 'rd2' },
    { bits:  2, name: 'imm2' },
    { bits:  5, name: 0x1c },
]}

Description

This instruction loads two 32-bit values into the two GP registers rd1 and rd2 from the address rs1 + (zero_extend(imm2) << 3).

Note, that there is no atomicity guarantee for this instruction. I.e., an implementation can realize this instruction in form of two memory transactions and an exception can be handled in-between, in which case the whole instruction will be re-executed.

Operation

addr := rs1 + (zero_extend(imm2) << 3)
mem[addr+3:addr] := reg[rd1][31:0]
mem[addr+7:addr+4] := reg[rd2][31:0]

Permission

This instruction can be executed in all privilege levels.

Exceptions

This instruction triggers the same exceptions that two corresponding SW instructions would trigger.

Included in

Extension
XTheadMemPair ([xtheadmempair])