swib.adoc

th.swib

Synopsis

Store indexed word, increment address before storage.

Mnemonic

th.swib rd, (rs1), imm5, imm2

Encoding

{reg:[
    { bits:  7, name: 0xb, attr: ['custom-0, 32 bit'] },
    { bits:  5, name: 'rd' },
    { bits:  3, name: 0x5, attr: ['Mem-Store'] },
    { bits:  5, name: 'rs1' },
    { bits:  5, name: 'imm5' },
    { bits:  2, name: 'imm2' },
    { bits:  5, name: 0x09 },
]}

Description

This instruction increments the value in rs1 by (sign_extend(imm5) << imm2) and writes the result back to rs1. After the increment of rs1, this instruction stores an 32-bit value from the GP register rd to the (incremented) address rs1.

Operation

rs1 := rs1 + (sign_extend(imm5) << imm2)
mem[rs1+3:rs1] := rd

Permission

This instruction can be executed in all privilege levels.

Exceptions

This instruction triggers the same exceptions that a corresponding SW instruction would trigger.

Included in

Extension
XTheadMemIdx ([xtheadmemidx])